亚微米GaAs MESFET二维数值模拟

本文用计入热电子效应的动量能量守恒模型讨论了亚微米GaAs MESFET二维数值模拟。为了减少计算量进行了模型简化和算法选择。文中给出并分析了三种典型器件的模用范果,根据模拟结果,研究了小尺寸器件中的速度过冲效应并得出常规的漂移扩散模型的适拟结围。     

Submicrometer GaAs MESFET with shallow channel and very high transconductance

A 0.5-µm GaAs MESFET with a 25-nm thin channel, 400- mS/mm maximum transconductance, and 580-mS/V.mm K value is presented. This extremely high K value was obtained using an electron-beam fabricated recessed-gate MESFET structure on a highly doped (9.10¹⁷cm^-3) MBE-grown channel layer with 2600-cm²/V.s mobility. The use of thin channels and a buried p-layer also reduced the output conductance and other short-channel effects dramatically. As a result, these scaled MESFET's are very promising for high-speed digital logic circuits.     

Long-term transient radiation-resistant GaAs FET's

The amplitude of long term, pulse-radiation-induced transients in ion implanted GaAs FET's has been reduced by up to two orders of magnitude by the addition of a deep buried p-layer beneath the active n-layer. The p-layer was formed by ion implantation of Be to depth of 0.8 µm below the Si implanted n-active channel. Backgating was also greatly reduced as indicated by a much smaller amplitude transient response following application of a positive gate pulse and by the absence of light sensitivity and looping in the current/ voltage (I-V) characteristics.     

GaAs Ultra-High-Speed Prescaler/Phase Frequency Comparator Using LSCFL (Short Paper)

A high-speed, low-power prescaler/phase frequency comparator (PFC) medium scale integration (MSI) circuit for a phase-locked stable oscillator is designed and fabricated using GaAs MESFET low-power source-coupled FET logic (LSCFL) circuitry. The construction of the 1/64 frequency divider prescaler/PFC is designed to obtain high-speed and low-power operation. The fabrication process used is buried p-layer SAINT with a 0.5-µm gate length. The fabricated prescaler/PFC MSI circuit, mounted on a newly developed high-frequency package, operates up to 7.6 GHz with a power dissipation of 730 mW.     

Improvement of alpha-particle-induced soft-error immunity in a GaAsSRAM by a buried p-layer

Alpha-particle-induced soft-error immunity in a 1-kB GaAs SRAM was improved by a buried p-layer, which was formed in isolation regions as well as in FET regions and was designed to be completely depleted. The mean time between failures exceeded 10⁴ at an alpha-particle fluence of about 2.0×10⁴ cm^-2-s^-1 with a 1.0-μCi²⁴¹Am source. The alpha-particle energy had a peak at 4.0 MeV and was distributed from nearly 0 to 4.6 MeV. This value is five orders of magnitude better than that for a conventional SRAM without a buried p-layer. This improvement in the soft-error immunity can be achieved without increasing the access time or the power consumption by depleting the p-layer completely. Also discussed is the possibility of using a conductive p-layer scheme for higher integration of GaAs SRAMs     

A lightly doped deep drain GaAs MESFET structure for linearamplifiers of personal handy-phone systems

An improved GaAs MESFET structure, named a buried p-layer lightly doped deep drain (BP-LD3) structure, is proposed. This structure can be fabricated by the conventional self-aligned gate and selective ion implantation technologies, and the FET characteristics show a high transconductance, a high breakdown voltage, and a low drain-source resistance. The lightly doped deep drain characterizing this structure was introduced on the basis of a two-dimensional numerical analysis including an impact ionization for a buried p-layer lightly doped drain (BP-LDD) structure which has been applied for high-speed digital ICs. The simulated results clarified that a low breakdown voltage of the BP-LDD structure originates from a high rate of carrier generation due to the impact ionization in the lightly doped drain region. The reason is that both electric field and current density become high in the region. In the new BP-LD3 structure, the electron current expands due to the deep formation of lightly doped drain, therefore impact ionization is reduced. This BP-LD3 structure was fabricated and the FET characteristics were compared with those of the conventional BP-LDD structure, and a structure which is now being studied for linear amplifiers of 1.9 GHz personal handy-phone systems. The measured breakdown voltage of 8.1 V, transconductance of 360 mS/mm, and drain-source resistance of 2.5 Ω/mm for the BP-LD3 structure indicate high potentiality for analog applications     

Comparison of SiC, GaAs, and Si RF MESFET power densities

The maximum power density of Si, GaAs, and 4H-SiC MESFET's was modeled using material parameters, a planar MESFET cross section, and a piecewise linear MESFET drain characteristic. The maximum power density for the Si, GaAs, and 4H-SiC was calculated to be 0.45 W/mm, 0.78 W/mm, and 17.37 W/mm at drain voltages of 8.4 V, 8.3 V, and 105 V, respectively. Modeling power density as a function of drain voltage showed that, for low voltage applications, the GaAs MESFET has the highest power density because of its high electron mobility and very low channel resistance (R_on). For high voltage applications, the 4H-SiC MESFET has the highest absolute power density because of the higher breakdown voltage of this material. Experiment data agree qualitatively with the modeled results     

Optically-controlled ion-implanted GaAs MESFET characteristic withopaque gate

An analytical modelling has been carried out for an ion-implanted GaAs MESFET having a Schottky gate opaque to incident radiation. The radiation is absorbed in the device through the spacings of source, gate, and drain unlike the other model where gate is transparent/semitransparent. Continuity equations have been solved for the excess carriers generated in the neutral active region, the extended gate depletion region and the depletion region of active (n) and substrate (p) junction. The photovoltage across the channel and the p-layer junction and that across the Schottky junction due to generation in the arc region of the gate depletion layer are the two important controlling parameters. The I-V characteristics and the transconductance of the device have been evaluated and discussed     

Below 10 ps/gate operation with buried p-layer SAINT FETs

GaAs SAINT FETs with a p-layer buried under the active layer have achieved below 10 ps/gate (9.9 ps/gate) operation for the first time in semiconductor devices. The p-layer formed by Be+ implantation is completely depleted by the built-in potential. It has successfully alleviated the short channel effects without increasing parastic capacitance.     

改善GaAs MESFET输出功率线性的载流子浓度分布设计与制备

经过对GaAs MESFET输出功率及其线性失真的综合分析,提出了无拖尾双峰n~+n载流子浓度分布的最佳设计。用Si离子注入和Be注入埋层方法,以及优化的快速退火技术,满意地制备出所希望的无拖尾双峰n~+n浓度分布。用于DX571功率GaAs MESFET器件时的研究表明,与常规注入分布的器件相比,无拖尾n浓度分布器件在4GHz下测得的1dB增益压缩功率输出增加了0.4W;在输入信号提高50mW情况下增益仍为9dB,漏极效率提高3％,加上n~+注入后饱和压降又下降0.3V,预计其线性输出功率能力将会有进一步改善。     

AlGaAs/GaAs MESFET IC with Ni buried gate technology

Ni buried gate technology for threshold voltage control using a Ni-GaAs reaction by a heat treatment is developed and successfully applied to AlGaAs/GaAs heterostructure MESFET IC's. Switching delay time of 36.7 ps with the power-delay product of 10 fJ (1-V supply voltage) was obtained at 83 K for a ring oscillator with 1.5-µm gate FET's. This technology, together with the saturated resistor loads, promises to simplify the process for AlGaAs/GaAs MESFET LSI's by not requiring active-layer etching.     

High-Speed and Low-Power GaAs Phase Frequency Comparator

A high-speed and low-power consumption phase frequency comparator (PFC) for a phase lock stable oscillator was designed and fabricated with a GaAs MESFET BFL circuit for the first time. The threshold voltage, gate width, and gate length of GaAs MESFET's in the PFC were determined by circuit simulations for a high-speed and low-power operation. The fabrication process used buried p-layer SAINT-FET's with 0.5-µm gate length. The fabricated PFC performed stable phase and frequency comparison up to 600 MHz at only 60 mW. Using dislocation-free wafers, the fabrication yield in the laboratory was more than 90 percent.     

A GaAs Power MESFET Operating at 3.3V Drain Voltage for Digital Hand-Held Phone

A GaAs power metal semiconductor field effect transistor (MESFET) operating at a voltage as low as 3.3V has been developed with the best performance for digital hand-held phone. The device has been fabricated on an epitaxial layer with a low-high doped structure grown by molecular beam epitaxy. The MESFET, fabricated using 0.8 μm design rule, showed a maximum drain current density of 330 mA/mm at V_gs = 0.5V and a gate-to-drain breakdown voltage of 28 V. The MESFET tested at a 3.3 V drain bias and a 900 MHz operation frequency displayed an output power of 32.5-dBm and a power added efficiency of 68%. The associate power gain at 20 dBm input power and the linear gain were 12.5dB and 16.5dB, respectively. Two tone testing measured at 900.00MHz and 900.03MHz showed that a third-order intercept point is 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order intermodulation.     

A low-distortion K-band GaAs power FET

A K-band low-distortion GaAs power MESFET was developed by incorporating a pulse-type channel doping profile using molecular-beam-epitaxial technology and a novel 0.3-μm T-shaped gate. The low-distortion FETs offer about 10 to 15 dBc improvement in second-harmonic distortion compared to devices fabricated on a uniformity doped active layer. Significantly larger power load-pull contours are obtained with the low-distortion devices, indicating the improved linearity of these devices. In an 8-20-GHz single-stage broad-band amplifier, up to 10 dBc improvement in harmonic performance was achieved using the low-distortion device. This low-distortion device exhibits very linear transconductance as a function of the gate bias. A typical 750-μm-gate-width device is capable of 26 dBm of output power with 6 dB of gain, and power-added efficiency in excess of 35% when measured at 18 GHz. At 25 GHz, the device is capable of 24 dBm of output power with 5 dB associated gain     

A self-aligned quarter-to-half-micrometer buried-gate GaAs junction FET

We present a reliable but simple self-aligned technology to fabricate very short buried-gate (0.25-0.5 µm) GaAs JFET. The device has a buried p-n junction gate to control the channel current, but in particular, there is another Schottky contact connecting with the source to define the real channel length. The transconductance is 180 mS/mm and the gate leakage current density is only about one-hundredth of the conventional MESFET. Furthermore, there is no backgate effect regardless of how close two devices are neighbored. This technology and device structure are especially useful in GaAs integrated circuits.     

A high-speed and highly uniform submicrometer-gate BPLDD GaAsMESFET for GaAs LSIs

The authors present formation conditions for ion-implanted regions of a GaAs buried p-layer lightly doped drain (BPLDD) MESFET that can improve short-channel effect, V_th uniformity, and FET operating speed, simultaneously. For 0.7-μm gates, a Mg⁺ dose of 2×10¹² cm^-2 at 300 keV and a Si⁺ dose of 2×10¹² cm^-2 at 50 keV are suitable for the p layer and n' layer, respectively. A σV _th of 7 mV is realized. Gate-edge capacitance of the 0.7-μm-gate BPLDD that consists of both overlap capacitance and fringing capacitance is successfully reduced to 0.5 fF/μm, which is about 50% of that of a non-LDD buried p-layer (BP) FET. Another parasitic capacitance due to the p-layer was found to have less effect on the speed than the gate-edge one. Consequently, the gate propagation delay time of the BPLDD can be reduced to 15 ps at power dissipation of 1 mW/gate, which is about 65% of that of a BP. Applying the 0.7-μm-gate BPLDD to 16-kb SRAMs, the authors have obtained a maximum access time of less than 5 ns with a galloping test pattern     

An accurate photonic capacitance model for GaAs MESFETs

A new set of pseudoempirical equations is presented in order to simulate the optical and bias dependencies of GaAs MESFET junction capacitances, which is valid for the whole I-V plane. The variations induced in the small-signal equivalent circuit by the optical illumination are extracted from on-wafer scattering parameter measurements. New linear and quasi-logarithmic variations versus the incident optical power are shown for gate-drain and gate-source (Cgd and Cgs) capacitances. Furthermore, experimental results are in very good agreement with the simulated values for a wide range of optical power and bias conditions. Large signal MESFET models show a better fit with measured S-parameters than those previously published, leading to a greater degree of confidence in the design of photonic monolithic microwave integrated circuits     

A 3.5 V, 1.3 W GaAs power multi-chip IC for cellular phones

A GaAs power multi-chip IC (MCIC) operable at a voltage of 3.5 V designed for cellular phones has been developed. The MCIC is able to deliver an output power of 1.3 W with a power-added efficiency of 60% in a frequency range from 890 to 950 MHz. This consists of two GaAs MESFET's, three GaAs passive matching chips, and a printed circuit board on which biasing networks are disposed. These are mounted on an aluminum nitride (AlN) package, occupying a half volume of conventional power hybrid IC's, i.e., only 0.4 cc. In order to improve the low voltage operation characteristics, a GaAs power MESFET operable at a low voltage of 3.5 V with an output power of 32 dBm and a power-added efficiency of 65% is developed, and microstrip lines having high impedance characteristics are incorporated also in order to minimize the conductor loss of matching network. The MCIC would be highly useful to develop compact cellular phones with advanced characteristics     

A planar gate double beryllium implanted GaAs power MESFET for lowvoltage digital wireless communication application

An ion-implanted planar gate power MESFET for low voltage digital wireless communication system including DCS1800 (digital cellular system at 1800 MHz) and CDMA (code division multiple access) handset applications has been developed. The process for the device developed contains double Be implantation to reduce the surface and substrate defect trapping effects. The MESFET process developed has very little gate recess (less then 200 Å), which greatly improves the uniformity and the yield of the wafer. The 1 μm×20 mm MESFET manufactured using this planar gate technology exhibits an output power of 32.98 dBm and power added efficiency over 53% with gain of 11.2 dB when tested at 1.9 GHz under 3.6 V drain bias voltage and 80 mA quiescent drain current. The pinch off voltage of the 20 mm devices within a wafer is -2.81 V with a standard deviation of 120 mV. The device was also tested at 3.6 V and 1.9 GHz for CDMA application. Under the IS-95 CDMA modulation at 28 dBm output power, the device gain is 10.7 dB and the device has an adjacent channel power rejection (ACPR) of -29.5 dBc at 1.25 MHz offset frequency and -44.9 dBc at 2.25 MHz offset. The test data shows that the double Be implanted devices developed using the planar gate technology have very good linearity and efficiency and can be used for the low voltage DCS1800 and CDMA handset applications     

Power optimization of high-efficiency microwave MESFET oscillators

Achieving high output power and efficiency in GaAs MESFET oscillators is mainly hampered by the device's parasitics, its static I-V characteristics, and the circuit embedding impedance. In this paper, the derivation of the relationship between oscillator output power and various circuit and device parameters is presented. From these analytical expressions, optimum operating conditions for maximum oscillator output power and efficiency are determined. The analysis method employed here is based upon a quasi-linear approach and an open-loop model of the oscillator. The design procedure is verified by measurements on an experimental circuit, which have demonstrated a dc/radio-frequency conversion efficiency of 54%