A wide-band current-controlled oscillator using bipolar-JFET technology

A 256K/spl times/1 bit NMOS dynamic RAM, fabricated using conventional n-channel two-layer polysilicon gate technology, is described. The memory cell was laid out in 5.7 /spl mu/m/spl times/12.5 /spl mu/m, and the die measured 4.84 mm/spl times/8.59 mm which can use a standard 300 mil 16 pin DIP. Reduction of the bit line capacitance was accomplished using the second polysilicon layer for the bit line. Through the use of large memory cell capacitance and special device coating techniques, alpha particle immunity was increased. The memory offers a 160 ns typical access time, 350 ns cycle time, and 250 mW active power dissipation.     

Reduce Afterpulsing of Single Photon Avalanche Diodes Using Passive Quenching With Active Reset

In this paper, we report a passive-quenching-with-active-reset circuit designed to reduce afterpulsing for single photon avalanche diodes. This circuit uses a large resistor to passively quench the avalanche current and a transistor to actively reset the device to the operating voltage after a specified hold-off time. Afterpulsing can be reduced by minimizing the stray capacitance of the package to reduce the total charge flow during avalanche. Proof of principle is demonstrated with discrete components. It is expected that by integrating the transistor with the avalanche photodiode the stray capacitance can be minimized to significantly reduce afterpulsing.     

Current gain and switching speed in a three-terminal nonequilibrium superconducting device

A three-terminal nonequilibrium superconducting device controlled by the tunnel-injection of quasi-particles is fabricated and experimentally investigated. The device used in the present experiments has a sandwich structure consisting of NbN and Pb-alloy films. The dc current gain is measured as a function of the current density of the two junctions and the injected power. A current gain larger than unity is obtained when the current density ratio (the acceptor to the injector current) increases. The turn-on time is measured in an experimental circuit using a Josephson sampling technique. The output waveform rises succeeding a turn-on delay of 300 ps after the input current changes. The rise time of the output waveform consists of two parts. About 70 percent of the full output amplitude occurs within 300 ps and the remaining is slow with a time constant of over 1 ns. Also pointed out in the paper are the problems of obtaining a device with large device gain and with high switching speed. Finally, the possibility of using this device in logic circuits is discussed.     

Fast bistable wavelength switching characteristics in two-electrodedistributed feedback laser

Fast bistable wavelength switching between two longitudinal modes separated by 1.7 nm was achieved in a two-electrode distributed feedback laser with inhomogeneous excitation. As a result, a fast wavelength switching time less than 200 ps was observed in this device. In addition, high-speed repetitive wavelength switching operation up to 1 GHz was achieved. This indicates that the device is capable of repetitive wavelength switching within 1 ns, including delay time and rise time     

离散色散光域傅里叶变换的延时和带宽扩展研究

光域傅里叶变换为射频频谱分析提供了一种新的解决方案。光域傅里叶变换主要受限于大的二阶色散的获得,而离散傅里叶变换只需要控制离散点的相位,理论上可以解决大色散的获得问题。文章利用光纤环作为离散色散器件,用线性调频信号作为待测信号,进行了光域离散傅里叶变换的研究。该系统是一个快速傅里叶变换系统,每次变换用时约2.07 ns。用示波器观测线性调频信号变换前与变换后的波形延迟,可以测出该系统的变换延时,约为100 ns,其延时大小主要取决于系统中的光纤长度。该系统可以实现对信号的不间断处理。为了扩展系统的瞬时带宽,对片上集成光微环组方案的可实现性进行了分析。     

Theoretical modification of the negative Miller capacitance during the switching transients of IGBTs

The insulated gate bipolar transistor (IGBT) has negative Miller capacitance during switching transients. It has conventionally been attributed to the voltage dependency of the Miller capacitance. However this explanation has physical ambiguity, yet, it lacks a discussion of the conditions for the occurrence of negative Miller capacitance as well. We argue that it is the current dependence to the Miller capacitance that results in the negative case. In this paper, we provide a modification to the theoretical analysis of this phenomenon. The occurrence condition for it and the device parameters about it are discussed. It is discovered that the negative Miller capacitance must occur during the turn-off process for any IGBT, while it is relatively difficult during the turn-on process. At the device design level, the current gain of the PNP transistor in the IGBT is an important factor for the negative Miller capacitance.     

Optically Activated 4H-SiC p-i-n Diodes for High-Power Applications

To realize the benefits of SiC power electronics and optically controlled device technology, we present in this letter optically activated SiC p-i-n diodes for high-temperature and high-power applications. The diodes were fabricated on an n-type 4H-SiC substrate, and measurements show that, when tested at a reverse bias of 1000 V, the diode was switched on by a single UV (337.1 nm) laser pulse with 1.2-mJ optical energy. The FWHM is about 180 ns with a rise time of less than 10 ns and a fall time of about 200 ns. The response time is primarily limited by the RC time constant from the junction capacitance of the diode and the current-limiting resistor in the test circuit. This initial work forms the basis for the further development of high-power high-speed SiC bistable switches.     

A study of on-resistance and switching characteristics of the power MOSFET under cryogenic conditions

The decrease in on-resistance of power MOSFETs operation under cryogenic temperature leads to a considerable reduction in heat generation inside the device. An experimental measurement of on-resistances at 77K, 173K, 243K and 295K was carried out by applying cryogenic cooling techniques. The decrease in on-resistance and capacitance associated with the temperature led to an enhancement of overall time response of the MOSFETs. Another advantage associated with operating MOSFETs under cryogenic temperature is the decrease of the internal thermal resistance. The present work demonstrated that by exposing the device to cryogenic conditions, it is possible to implement high frequency, high power applications with MOSFET devices.     

Memory switching effects in a-Si/c-Si heterojunction bipolarstructures

The authors report a three-terminal undoped amorphous silicon (a-Si)/p-n crystalline silicon (c-Si) structure, which exhibits OFF and ON states. An OFF state is characterized by a current in the structure in the low nanoampere range due to the large resistance of the undoped a-Si layer, while in the ON state the structure exhibits a large conductance and its current is determined in practice by the load resistance. Reversible switching between the two states with a rise time of about 40 ns and a fall time of about 200 ns was achieved by applying appropriate positive or negative current pulses to the base of the c-Si p-n junction. The structure can be integrated into a standard bipolar process, and, being of a size suitable for VLSI applications, may be useful as a basic three-terminal memory cell     

Current-voltage characteristics, small-signal parameters, and switching times of GaAs FET's

A new two-dimensional model of a GaAs FET is proposed. The model takes into account diffusion processes and Gunn-domain formation under the gate but it requires a very small computer time. The electric-field profiles under the gate, current-voltage characteristics, the dependences of the transconductance and gate-to-source capacitance on the drain voltage, and the dependences of a characteristic switching time and power-delay product on the device thickness are calculated. The results of the calculation agree well with the experimental data found earlier by other authors. The proposed model can be used for a computer-aided design of GaAs FET amplifiers and logic elements and also for a comparative study of GaAs and InP MESFET's.     

The method of estimating delay in switching circuits and the figure of merit of a switching transistor

A simple method of estimating delay in a switching network is outlined. The simplicity of formulas thus obtained makes them readily applicable for circuit comparisons or device optimization purposes. It is shown that a term involving the product of base resistance and diffusion capacitance forms a major limitation on high-speed, voltage-driven circuits. This method is applicable to a general class of switching problems.     

Optically-controlled switching characteristics of silicon MESFETs

The switching time of a silicon MESFET device can be controlled by photons incident on the transparent or semitransparent gate, which may be treated as the virtual gate in addition to usual gate. Studies have been made on the optically-controlled switching characteristics of the Silicon MESFET which show that the internal gate-source capacitance increases with increasing radiation flux density under normally OFF conditions and decreases under normally ON conditions. Further, the drain-to-source resistance is found to be reduced with increasing radiation flux density at a particular value of absorption coefficient (or wavelength of radiation). The effect of radiation becomes predominant over the impurity concentration at flux-density ≥ 10¹⁸/m². Also it is observed that RC time constant decreases initially with increasing radiation up to 10¹⁸/m². At a radiation intensity equal to 10¹⁹/m², the RC time constant gradually decreases with increased doping level.     

All-optical switching using color centers in an irradiated phosphorus-doped fiber

We report on all-optical switching of a 900-nm signal in a two-mode silica fiber based upon a resonant nonlinearity introduced by phosphorus color centers in a 22-cm irradiated P/sub 2/O/sub 5/-SiO/sub 2/ fiber. Full switching was observed with only 1 /spl mu/J of absorbed 532-nm pump energy, with a projected response time under 10 ns. This switch required a peak power two orders of magnitude lower than for a fiber Kerr effect device operated under identical conditions.     

CMOS gigabit-per-second switching

An analysis and experimental results for a 600-Mb/s 1.2-μm CMOS space switch chip are provided. The high bit rate is achieved with a tree architecture, which is relatively insensitive to on-chip stray capacitance. Computer simulations indicate that bit rates in excess of 1 Gb/s are achievable with 1-μm CMOS and circuit/layout optimization. An obstacle to achieving high bit rate is crosstalk, which is primarily caused by chip packaging and not by the chip itself. Even the best discrete packaging technologies result in excessive crosstalk when 32 outputs switch simultaneously at 600 Mb/s. Tolerable crosstalk was achieved by limiting outputs to two per power supply pin. A major increase in bit rate can be obtained by switching bytes (8 b parallel) of information. This requires on-chip information storage and reclocking to maintain synchronization between the eight parallel bits. Experiments with a second-generation synchronous switch chip have demonstrated switching at 311 MB/s, which corresponds to an STS-48 rate of 2.488 Gb/s     

Smart in-plane switching of nanowires embedded liquid crystal matrix

Ultra-thin, high yield semiconductor CdS nanowires (NW's) have been successfully fabricated by the conventional hydrothermal method using ethylenediamine (EDA). This novel hydrothermal approach deals with solvent and ligands exchange process by surfactant injection into solution-phase route, at a fixed holding time and temperature. It is found to be crucial to fabricate large distribution of uniform CdS-NW's width varies up to 7–10 nm. With these extended in thermotropic liquid crystals (e.g. Pimelic acid with undecyloxy benzoic acid; PA+11BAO) matrix producing skein-worm like nanostructures. Liquid crystals (LC) constitute a fascinating class of soft condensed matter characterized by the counter intuitive combination of nanomaterials fluidity and long-range order. Comprehensive graphical response behaviours are performed to investigate dielectric relaxations and phase variance optical switching through this novel nanocomposite device. Moreover, smart electro-optic switching approach is quite promising as well as applicable to other nanomaterials also, and it utilizes the currently mature high contrast liquid crystal switching. This article emerges capacitance vs. voltage hysteresis in a Preisach model fitting analysis. The remarkable signature of a reversal and bi-stable DC switching is also realized in the induced smectic binary composite system upon the application of an appropriate electric field. Electrical and optical tuning interaction of the composites may allow for engineering of practical applications in novel switchable devices.     

A slew-rate controlled output driver using PLL as compensation circuit

A slew-rate controlled output driver adopting the delay compensation method has been implemented using 0.18-/spl mu/m CMOS process for storage device interface. A phase-locked loop (PLL) is used to generate compensation current and constant delay time. The compensation current reduces the slew-rate variation over process, voltage, and temperature variation of the output driver. The constant delay time, which is generated by the replica of the voltage-controlled oscillator in the PLL, reduces the slew-rate variation over load capacitance variation. Such an output driver has 25% less variation at slew rate than that of the conventional output driver. The proposed output driver is able to meet UDMA100 interface that specifies load capacitance ranging from 15 to 40 pF and slew rate from 0.4 to 1.0 V/ns.     

A 65 mW 128K EB-ROM

A low power read-only memory (128K EB-ROM) has been developed using direct electron-beam data writing and 2 /spl mu/m VLSI fabrication technology. Programming of information in the ROM is accomplished by selective use of a field oxide in place of a thin gate oxide. The memory cell array is divided into eight current discharge (CD) units. Only one of the eight CD units, which contains a selected cell, is activated by the 3-bit extra decoder. The large capacitance enlarged by the Miller effect is markedly reduced. Moreover, the total capacitance to be precharged is also reduced. High performance output buffer circuitry is adopted, which has a high logic threshold voltage. As a result, the fabricated 128K EB-ROM is capable of 65 mW power dissipation under 400 ns cycle time and 5 V DC supply voltage conditions and 200 ns access time. Memory cell and chip dimensions are 8 /spl mu/m/spl times/7.75/spl mu/m and 3.75 mm/spl times/5.5 mm, respectively.     

A new bistable laser diode configuration for all optical switching

A new bistable laser diode configuration for all optical switching has been suggested and its equivalent circuit model is developed. For switching the device to the high state (set) a TE mode optical pulse is required, which is the oscillating mode of the laser, whereas a TM mode pulse is used to bring the output to a low state (reset). But the wavelength of the set and reset pulses are the same as that of the lasing wavelength of the device. The static and dynamic characteristics are studied by simulating the equivalent circuit model using the circuit simulation program PSPICE. It is found that as the carrier lifetime τ_a of the absorption section increases, the width of the optical pulse required for reset increases nonlinearly. The rise and fall times are found to be 0.15 and 0.16 ns, respectively, for a τ _a, of 3 ns     

Influence of the gate internal impedance on losses in a power MOStransistor switching at a high frequency in the ZVS mode

In order to use a power metal oxide semiconductor (MOS) transistor switching in the zero voltage mode at high frequencies, the output capacitance has to be maximal and the input capacitance minimal. These characteristics are available in the datasheets. Nevertheless, to choose a transistor ideal for such an application, having minimal losses, additional characterizations have to be done in order to complete the datasheets. In particular, it is necessary to make sure that all the cells of the MOS transistor can be opened in a time shortly before the voltage rise time at turn-off, in order to reduce as low as possible the turn-off losses. The present paper points out that the gate to source impedance characterizes the ability of the device to turn-off very quickly and the knowledge of that parameter is useful to choose a MOS transistor having minimal losses in very high frequency zero voltage switching (ZVS) applications     

256-Mb DRAM circuit technologies for file applications

256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces manufacturing costs. An experimental 256-Mb DRAM has been designed and fabricated by combining the proposed circuit techniques and a 0.25-μm phase-shift optical lithography, and its basic operations are verified. A 0.72-μm² double-cylindrical recessed stacked-capacitor (RSTC) cell is used to ensure a storage capacitance of 25 fF/cell. A typical access time under a 2-V power supply voltage was 70 ns. With the proper device characteristics, the simulated performances of the 256-Mb DRAM operating with a 1.5-V power supply voltage are a data-retention current of 53 μA and an access time of 48 ns