Finite element analysis for grinding of wire-sawn silicon wafers: a designed experiment

Silicon is the primary semiconductor material used to fabricate microchips. The quality of microchips depends directly on the quality of starting silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Surface grinding is one of the processes used to flatten the wire-sawn wafers. A major issue in grinding of wire-sawn wafers is the reduction and elimination of wire-sawing induced waviness. This paper presents the results of a finite element analysis for grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of four factors (wafer thickness, waviness wavelength, waviness height and grinding force) on effectiveness of waviness reduction. The implications of this study to manufacturing are also discussed.     

An experimental investigation into soft-pad grinding of wire-sawn silicon wafers

Silicon is the primary semiconductor material used to fabricate microchips. A series of processes are required to manufacture high-quality silicon wafers. Surface grinding is one of the processes used to flatten wire-sawn wafers. A major issue in grinding of wire-sawn wafers is reduction and elimination of wire-sawing induced waviness. Results of finite element analysis have shown that soft-pad grinding is very effective in reducing the waviness. This paper presents an experimental investigation into soft-pad grinding of wire-sawn silicon wafers. Wire-sawn wafers from a same silicon ingot were used for the study to ensure that these wafers have similar waviness. These wafers were ground using two different soft pads. As a comparison, some wafers were also ground on a rigid chuck. Effectiveness of soft-pad grinding in removing waviness has been clearly demonstrated.     

Fine grinding of silicon wafers: designed experiments

Silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure to develop cost-effective processes to manufacture silicon wafers. Fine grinding possesses great potential to reduce the overall cost for manufacturing silicon wafers. The uniqueness and the special requirements of fine grinding have been discussed in a paper published earlier in this journal. As a follow-up, this paper presents the results of a designed experimental investigation into fine grinding of silicon wafers. In this investigation, a three-variable two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feed-rate). The process outputs studied include grinding force, spindle motor current, cycle time, surface roughness and grinding marks.     

Fine grinding of silicon wafers: a mathematical model for grinding marks

The majority of today’s integrated circuits are constructed on silicon wafers. Fine-grinding process has great potential to improve wafer quality at a low cost. Three papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third paper developed a mathematical model for the chuck shape, addressing one of the technical barriers that have hindered the widespread application of this technology: difficulty and uncertainty in chuck preparation. As a follow up, this paper addresses another technical barrier: lack of understanding on grinding marks. A mathematical model to predict the locus of the grinding lines and the distance between two adjacent grinding lines is first developed. With the developed model, the relationships between grinding marks and various process parameters (wheel rotational speed, chuck rotational speed, and wheel diameter) are then discussed. Finally, results of pilot experiments to verify the model are discussed.     

ELID grinding of silicon wafers: A literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits. There have been continuous demands for higher quality silicon wafers with lower prices, and it becomes more and more difficult to meet these demands using current manufacturing processes. In recent years, research has been done on electrolytic in-process dressing (ELID) grinding of silicon wafers to explore its potential to become a viable manufacturing process. This paper reviews the literature on ELID grinding, covering its set-ups, wheel dressing mechanism, and experimental results. It also discusses the technical barriers that have to be overcome before ELID grinding can be used in manufacturing.     

A grinding-based manufacturing method for silicon wafers: generation mechanisms of central dimples on ground wafers

Silicon wafers are the fundamental building blocks for most integrated circuits. The lapping-based manufacturing method currently used to manufacture the majority of silicon wafers will not be able to meet the ever-increasing demand for flatter wafers and lower prices. A grinding-based manufacturing method has been investigated experimentally to demonstrate its potential to manufacture flat silicon wafers at a lower cost. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. This paper, as a follow up, addresses one of the reasons for the poor flatness at the wafer center: central dimples on ground wafers. A finite element model is developed to illustrate the generation mechanisms of central dimples. Then, effects of influencing factors (including Young's modulus and Poisson's ratio of the grinding wheel segment, dimensions of the wheel segment, grinding force, and chuck shape) on the central dimple sizes are studied. Pilot experimental results will be presented to substantiate the predicted results from the finite element model. This provides practical guidance to eliminate or reduce central dimples on ground wafers.     

A grinding-based manufacturing method for silicon wafers: an experimental investigation

The majority of semiconductors are built on silicon wafers. Future semiconductors will require flatter wafers with a lower price. The lapping-based manufacturing method currently used to manufacture silicon wafers will not be able to meet the ever-increasing demand cost-effectively. This paper reports an experimental investigation into a grinding-based manufacturing method, which has potential to manufacture flat silicon wafers at a lower cost. Background information on semiconductors and silicon wafers is presented first. After a discussion on drawbacks of the lapping-based method, the grinding-based method is described. Next, experimental results with the grinding-based method are presented and discussed. The results from this investigation have demonstrated the potential of the grinding-based method and revealed several directions for future work.     

Fine grinding of silicon wafers: effects of chuck shape on grinding marks

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon ingot into wafers. With continuing shrinkage of feature sizes of microchips, more stringent requirement is imposed on wafer flatness. Fine grinding of silicon wafers is a patented technology to produce super flat wafers at a low cost. Six papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented the mathematical models for the chuck shape and the grinding marks, respectively. The fifth paper developed a mathematical model for the wafer shape and the sixth paper studied machine configurations for spindle angle adjustments. This paper is a follow up of the above-mentioned work. A mathematical model to predict the depth of grinding marks for any chuck shape will be first developed. With the developed model, effects of the chuck shape (as well as the wheel radius) on the depth of grinding marks will be studied. Finally, results of pilot experiments to verify the model will be discussed.     

Fine grinding of silicon wafers: machine configurations for spindle angle adjustments

This paper addresses an important aspect of silicon wafer fine grinding: machine design. For any commercially available wafer grinders, spindle angle adjustments based on the wafer shape ground is almost inevitable in order to achieve flat wafers. However, there has been no commonly accepted guidance for the design of machine configurations to ensure the easiest adjustment. Practitioners doing spindle angle adjustments have been frustrated by the difficulties of achieving the adjustments on commercial wafer grinders. This paper first illustrates such difficulties with a machine configuration frequently cited in the literature. It then demonstrates the potential ease of spindle angle adjustments with a proposed machine configuration. Next, it shows mathematically that the proposed configuration (specifically, a pair of the axes for spindle angle adjustments) is uniquely determined once the wheel diameter and wafer diameter are known. It also shows that the proposed configuration is the best in terms of ease in spindle angle adjustments. The spindle angle adjustments will be more difficult with any other configurations deviating from the proposed one.     

Fine grinding of silicon wafers: a mathematical model for the wafer shape

Over 90% of semiconductors are built on silicon wafers. The fine grinding process has great potential to produce very flat wafers at a low cost. Four papers on fine grinding have been previously published by the authors. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented mathematical models for the chuck shape and the grinding marks, respectively. As a follow up, this paper develops a mathematical model for the wafer shape. After the model is described, its practical applications in wafer manufacturing are discussed.     

Simultaneous double side grinding of silicon wafers: a literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous double side grinding (SDSG) is one of the processes to flatten the wire-sawn wafers. This paper reviews the literature on SDSG of silicon wafers, covering the history, machine development (including machine configuration, drive and support systems, and control system), and process modeling (including grinding marks and wafer shape). It also discusses some possible topics for future research.     

Grinding wheels for manufacturing of silicon wafers: A literature review

Grinding is an important process for manufacturing of silicon wafers. The demand for silicon wafers with better quality and lower price presents tremendous challenges for the grinding wheels used in the silicon wafer industry. The stringent requirements for these grinding wheels include low damage on ground surfaces, self-dressing ability, consistent performance, long wheel lives, and low prices. This paper presents a literature review on grinding wheels for manufacturing of silicon wafers. It discusses recent development in abrasives, bond materials, porosity formation, and geometry design of the grinding wheels to meet the stringent requirements.     

Fine grinding of silicon wafers

Silicon wafers are used for the production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. As one of such processes, surface grinding of silicon wafers has attracted attention among various investigators and a limited number of articles can be found in the literature. However, no published articles are available regarding fine grinding of silicon wafers. In this paper, the uniqueness and the special requirements of the silicon wafer fine grinding process are introduced first. Then some experimental results on the fine grinding of silicon wafers are presented and discussed. Tests on different grinding wheels demonstrate the importance of choosing the correct wheel and an illustration of the proper selection of process parameters is included. Also discussed are the effects of the nozzle position and the flow rate of the grinding coolant.     

A study on surface grinding of 300 mm silicon wafers

Most of today's IC chips are made from 200 mm or 150 mm silicon wafers. It is estimated that the transition from 200 mm to 300 mm wafers will bring a die cost saving of 30–40%. To meet their customers' needs, silicon wafer manufacturers are actively searching for cost-effective ways to manufacture 300 mm wafers with high quality. This paper presents the results of a study on surface grinding of 300 mm silicon wafers. In this study, a three-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feedrate). The process outputs studied include spindle motor current, surface roughness, grinding marks and depth of subsurface cracks.     

Fine grinding of silicon wafers: a mathematical model for the chuck shape

Fine grinding of silicon wafers is a patented technology to manufacture super flat semiconductor wafers cost-effectively. Two papers on fine grinding were previously published in this journal, one discussed its uniqueness and special requirements, and the other presented the results of a designed experimental investigation. As a follow up, this paper presents a study aiming at overcoming one of the technical barriers that have hindered the widespread application of this technology, namely, the difficulty and uncertainty in chuck preparation. Although the chuck shape is critically important in fine grinding, there are no standard procedures for its preparation. Furthermore, the information on the relation between the set-up parameters and the resulting chuck shape is not readily available. In this paper, a mathematical model for the chuck shape is first developed. Then the model is used to predict the relations between the chuck shape and the set-up parameters. Finally, the results of the pilot experiments to verify the model are discussed.     

Grinding induced subsurface cracks in silicon wafers

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. To ensure high surface quality, the damage layer generated by each of the machining processes (such as lapping and grinding) has to be removed by its subsequent processes. Therefore it is essential to assess the subsurface damage for each machining process. This paper presents the observation of subsurface cracks in silicon wafers machined by surface grinding process. Based on cross-sectional microscopy methods, several crack configurations are identified. Samples taken from different locations on the wafers are examined to investigate the effects of sample location on crack depth. The effects of grinding parameters such as feedrate and wheel rotational speed on the depth of subsurface crack have been studied by a set of factorial design experiments. Furthermore, the relation between the depth of subsurface crack and the wheel grit size is experimentally determined.     

A finite element analysis of temperature variation in silicon wafers during wiresaw slicing

Temperature variation during slicing can cause undesirable warp and nanotopography on wafer surfaces, especially for large wafers. In this paper, a finite element model is constructed and presented to analyze and synthesize temperature variation of ingot during wiresaw slicing. The heat flux and natural convection boundary condition arising during slicing have been studied and incorporated in the model as well as the material removal. The model is designed to accommodate time-dependent boundary conditions and geometry which are integral to wiresaw slicing process. The results obtained from the model compare very well with the experimental results available in the literature. A method is proposed in order to obtain a relatively flat profile of temperature during slicing in order to reduce warp due to heat generation by intelligent control of boundary conditions. The method is tested using the model developed. The proposed method can be utilized by practitioners in order to obtain wafers with less warp and improved nanotopography due to thermal aspects in slicing using wiresaws.     

Edge-chipping reduction in rotary ultrasonic machining of ceramics: Finite element analysis and experimental verification

Rotary ultrasonic machining (RUM) is one of the machining processes for advanced ceramics. Edge chipping (or chamfer), commonly observed in RUM of ceramic materials, not only compromises geometric accuracy but also possibly causes an increase in machining cost. In this paper, a three-dimensional finite element analysis (FEA) model is developed to study the effects of three parameters (cutting depth, support length, and pretightening load) on the maximum normal stress and von Mises stress in the region where the edge chipping initiates. Two failure criteria (the maximum normal stress criterion and von Mises stress criterion) were used to predict the relation between the edge chipping thickness and the support length. Furthermore, a solution to reduce the edge chipping is proposed based upon the FEA simulations and verified by experiments.     

Investigations on the effects of multi-layered coated inserts in machining Ti-6Al-4V alloy with experiments and finite element simulations

This paper presents investigations on turning Ti-6Al-4V alloy with multi-layer coated inserts. Turning of Ti-6Al-4V using uncoated, TiAlN coated, and TiAlN + cBN coated single and multi-layer coated tungsten carbide inserts is conducted, forces and tool wear are measured. 3D finite element modelling is utilized to predict chip formation, forces, temperatures and tool wear on these inserts. Modified material models with strain softening effect are developed to simulate chip formation with finite element analysis and investigate temperature fields for coated inserts. Predicted forces and tool wear contours are compared with experiments. The temperature distributions and tool wear contours demonstrate some advantages of coated insert designs.     

Sensitivity analysis of a finite element model for the simulation of stainless steel tube extrusion

In this work, a sensitivity analysis has been performed on a finite element model of glass-lubricated extrusion of stainless steel tubes. Fifteen model parameters, including ram speed, billet and tool temperatures, friction coefficients and heat transfer coefficients, were considered. The aim of the study was to determine the parameters that are most important for the response of the extrusion force. The relationship between the model parameters and the responses was analyzed by a calculation of two different regression models: one linear polynomial model and one model that includes interaction terms. Additional simulations were then carried out to validate the regression models. The results show that the initial billet temperature is the factor that has the strongest impact on the extrusion force within the parameter ranges studied in this work. The goodness of prediction and goodness of fit are very good for both regression models.