Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

This paper introduces a design technique for coarse-grained reconfigurable architectures targeting digital signal processing (DSP) applications. The design procedure is analyzed in detail and an area-time-power efficient reconfigurable kernel architecture is presented. The proposed technique inlines flexibility into custom carry-save (CS) arithmetic datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a transformation, called uniformity transformation, imposed on the basic architectures of CS-multipliers and CS-chain-adders/subtractors. Experimental results including quantitative and qualitative comparisons with existing reconfigurable arithmetic cores and exploration results of the proposed reconfigurable architecture are provided.     

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.     

一种可重构阵列结构及其任务调度算法

提出了一种可以利用计算时间覆盖配置时间和数据传输时间的可重构阵列结构,并且针对该可重构阵列结构提出了一种表调度算法进行任务调度.在SOCDesigner平台上进行了软硬件协同仿真,对于IDCT,FFT,4×4矩阵乘法新可重构阵列相比原来的可重构阵列有平均约10%的速度提升.     

采用多核处理器进行可重构并行仿真的方法

文中对多传感器视觉信息处理算法进行分析,根据可重构处理器的并行计算参数模型提出了一种并行计算仿真的方法。多核处理器环境中,每个线程在独立的核上运行,线程间具有并发性。利用并发的线程模拟可重构阵列单元（PE）的运算方式,调用OpenMP设置多个线程并行执行,在多核计算机平台上模拟可重构处理器的计算过程。利用此方法能在没有具体的PE连接方案前,通过使用计算核模拟PE单元,将算法映射到多核处理器环境中。通过分析算法在多核计算机上的并发执行效率,来优化视觉信息算法在可重构阵列上的映射方案。     

粗粒度可重构结构的性能估计方法

在设计初期,估计粗粒度可重构结构的性能,对粗粒度可重构结构设计具有指导意义.在考虑局部数据存储器结构以及局部数据存储器与可重构阵列的接口结构的情况下,建立了粗粒度可重构结构的参数模型,使用改进的螺旋形绑定策略将应用算法DFG(Data Flow Graph)中的算子绑定到可重构阵列的处理单元上,提出了一种粗粒度可重构结构的性能估计方法.应用实例表明,在设计初期,该方法能得到周期精确的估计结果,有效地指导粗粒度可重构结构的设计.     

A New FPGA for DSP Applications Integrating BIST Capabilities

This work proposes a new FPGA architecture, to meet the requirements of signal processing and testing of current system-on-chip designs. The proposed architecture provides the hardware reuse and the reconfigurability advantages of an FPGA, not only for the system functionality, but also for the system testing, while keeping the performance level required by current signal processing applications. This paper presents the new FPGA model, along with preliminary experimental results that clearly show the possible advantages at the system level of merging design and test in a reconfigurable device.     

嵌入式可重构系统芯片的硬件验证平台设计

提出一种新的基于嵌入武可重构系统芯片的视频解码方案,采用了软硬件协同验证的方法.设计了相应的硬件验证平台,验证了H.264解码算法在可重构处理器上的可实现性.     

Control of hybrid nanopositioning systems for trajectory-tracking applications

In many industrial applications positioning systems are required to follow trajectory paths in the range of several centimeters and featuring at the same time a nanometre-range precision. Neither pure piezoelectric stages nor standard positioning systems with motor and spindle are able to meet such requirements as a single actuator, because of the small operation range on the one hand and inadequacies like backlash and friction on the other hand. Hybrid positioning systems, realized as a combination of a “coarse” and a “fine” actuator, aim to solve this problem. The wide range of applications enables a considerable market potential for such devices, but yields changing control requirements due to the high variety of possible positioned objects and positioning tasks and requires therefore a high-performance control system.In this paper a model-based control design for piezoelectric hybrid nanopositioning systems is presented. The proposed control consists of a multivariable state-feedback control on the basis of a novel plant representation offering a sufficient robustness. The designed control is realized and experimentally tested with a commercially available hybrid nanopositioning system featuring a DC drive, representing the coarse actuator, and a piezoelectric actuator utilized as fine actuator.     

A two-level reconfigurable architecture for digital signal processing

This paper describes a novel reconfigurable architecture for digital signal processing (DSP). This architecture consists of a two-level array of cells and interconnections. On the upper level, fundamental DSP operations such as multiplication and addition are mapped onto blocks of 4-bit cells. On the lower level, each cell uses a 4 × 4 matrix of smaller “elements” to perform the necessary computations. Cells also contain pipeline latches for increased throughput. The architecture features a simple VLSI implementation that combines the flexibility of memory elements with the speed of DOMINO logic. Initial prototypes have been fabricated using a modest 0.5-μm CMOS technology. Circuit simulations of the cell in 0.25-μm technology indicate that the design achieves a clock frequency of 200 MHz.     

A unified reconfigurable CORDIC processor for floating-point arithmetic

ABSTRACT

This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximises the sharing of common hardware circuit and achieves the area-delay efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 16384 × 16384 points target synthetic aperture radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T field programmable gate array platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.     

Reconfigurable Computing for Digital Signal Processing: A Survey

Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.     

A total cost approach to evaluating different reconfigurable architectures for baseband processing in wireless receivers

There is growing interest in the use of flexible digital signal processors for wireless systems, driven by the demands of time to market, cost pressure, the requirement for flexibility to cope with evolving standards, and rapidly increasing processing needs. Much of the discussion of these techniques involves terms like "efficient" or "cost-effective" without necessarily quantifying the terms. This article considers the various architectures applicable to a wideband CDMA node-B base station (ASIC, FPGA, traditional DSP, and two varieties of flexible DSP) and builds a quantitative total cost approach to evaluating them, including benchmarked performance data.     

Algorithmic aspects for functional partitioning and scheduling in hardware/software co-design

Hardware/software (HW/SW) partitioning and scheduling are the crucial steps during HW/SW co-design. It has been shown that they are classical combinatorial optimization problems. Due to the possible sequential or concurrent execution of the tasks, HW/SW partitioning and scheduling has become more difficult to solve optimally. In this paper more efficient heuristic algorithms are proposed for the HW/SW partitioning and scheduling. The proposed algorithm partitions a task graph by iteratively moving the task with highest benefit-to-area ratio in higher priority. The benefit-to-area ratio is updated in each iteration step to cater for the task concurrence. The proposed algorithm for task scheduling executes the task lying in hardware-only critical path in higher priority to enhance the task forecast. A large body of experimental results conclusively shows that the proposed heuristic algorithm for partitioning is superior to the latest efficient combinatorial algorithm (Tabu search) cited in this paper. Moreover, the Tabu search for partitioning has been further improved by utilizing the proposed heuristic solution as its initial solution. In addition, the proposed scheduling algorithm obtains the improvements over the most widely used approaches by up to 10% without large increase in running time. This work was presented in part at 2006 IEEE International Conference on Field Programmable Technology (ICFPT).     

A new reconfigurable Test Vector Generator for built-in self-test applications

This paper proposes a new approach to designing a BIST Test Vector Generator (TVG) for random vector-resistant circuits based on reconfigurable Cellular Automata Registers (CARs). Each CAR configuration is constructed by combining rules 90 and 150 and the same approach can also be applied to the Linear Feedback Shift Register (LFSR). The TVG thus designed is able to produce 100% fault coverage with short test time at the cost of low area overhead. To achieve this objective, a new method called the Rank Order Clustering (ROC) method, is introduced in order to fix a number of inputs at certain values when generating pseudorandom vectors. It is shown that the ROC method is very simple and efficient in fixing inputs at these values in terms of complexity. Experimental results have been conducted to demonstrate the applicability of the proposed approach in terms of hardware size and test application time.     

Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

A hybrid model for weekday replacements with infant mortality failures

A hybrid availability model of a repairable system with infant mortality failures is proposed. The hybrid model can efficiently represent different types of state transitions by the use of a hierarchy of models: (1) a time-discretized component submodel, which provides a piecewise-linear failure rate during an operating interval; (2) a phased-mission model, which transforms the state probability vector according to repair activity; and (3) a combinatorial model, which is used to predict the number of working units among a collection of identical components. The modeling approach is illustrated by predicting the expected number of working components for a multiple-component system where replacement components are ordered at the end of business hours each weekday end. Replacement occurs on the next weekday morning.     

Distributed fault detection for modular and reconfigurable robots with joint torque sensing: A prediction error based approach

A distributed fault detection scheme for modular and reconfigurable robots (MRRs) with joint torque sensing is proposed in this paper. With the proposed scheme, the joint torque command is filtered and compared with a filtered torque estimate derived from the nonlinear dynamic model of MRR with joint torque sensing. Common joint actuator faults are considered with fault detection being performed independently for each joint module. The proposed fault detection scheme for each module does not require motion states of any other module making it an ideal modular approach for fault detection of modular robots. Experimental results have confirmed the effectiveness of the proposed fault detection scheme.