A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems

In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on coarse-grain reconfigurable hardware. The reconfigurable hardware blocks are embedded in a heterogeneous reconfigurable system architecture. The fine-grain part is implemented by an embedded FPGA unit, while for the coarse-grain reconfigurable hardware our developed high-performance coarse-grain data-path is used. The design flow mainly consists of three steps; the analysis procedure, the mapping onto coarse-grain blocks, and the mapping onto the fine-grain hardware. In this work, the methodology is validated using five real-life applications; an OFDM transmitter, a medical imaging technique, a wavelet-based image compressor, a video compression scheme and a JPEG encoder. The experimental results show that the speedup, relative to an all-FPGA solution, ranges from 1.55 to 4.17 for the considered applications.     

Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

This paper introduces a design technique for coarse-grained reconfigurable architectures targeting digital signal processing (DSP) applications. The design procedure is analyzed in detail and an area-time-power efficient reconfigurable kernel architecture is presented. The proposed technique inlines flexibility into custom carry-save (CS) arithmetic datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a transformation, called uniformity transformation, imposed on the basic architectures of CS-multipliers and CS-chain-adders/subtractors. Experimental results including quantitative and qualitative comparisons with existing reconfigurable arithmetic cores and exploration results of the proposed reconfigurable architecture are provided.     

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.     

一种可重构阵列结构及其任务调度算法

提出了一种可以利用计算时间覆盖配置时间和数据传输时间的可重构阵列结构,并且针对该可重构阵列结构提出了一种表调度算法进行任务调度.在SOCDesigner平台上进行了软硬件协同仿真,对于IDCT,FFT,4×4矩阵乘法新可重构阵列相比原来的可重构阵列有平均约10%的速度提升.     

A fast force-directed simulated annealing for 3D IC partitioning

With the advent of three dimensional (3D) IC designs, new partitioning techniques that can take into account the 3D nature of designs are required. In this paper, a new force-directed simulated annealing (FSA) is introduced and used for 3D partitioning. The proposed force-directed simulated annealing introduces force as a new factor during the annealing process and replaces the random moves by probabilistic force-directed moves. Experimental results show that the force-directed move strategy speeds up the convergence and significantly improves the execution time of SA maintaining the quality of solution. FSA algorithm is effective for 3D IC partitioning and can be applied in other optimization problems.     

A General Reconfigurable Architecture for the BLAST Algorithm

The process of DNA sequence matching and database search is one of the major problems of the bioinformatics community. Major scientific efforts to address this problem have provided algorithms and software tools for molecular biologists since the early 1970s. At the algorithmic and software level BLAST is by far the most popular tool. It has been developed and continues to be maintained and distributed by the NCBI organization. The BLAST algorithm and software is computationally very intensive and as a result several computer vendors use it as a benchmark. On the other hand no systematic approach for hardware speedup of BLAST and its variants for different query and database size has been reported to date. In this paper we present our architecture that implements the BLAST algorithm for all of its major versions, and for any size of database and query. The system has been fully designed and partially implemented with reconfigurable logic. It consists of software and hardware parts and achieves a speedup of several times up to thousands of times vs general purpose computers.

A quad-polarization and frequency reconfigurable square ring slot loaded microstrip patch antenna for WLAN applications

In this paper, a novel polarization and frequency reconfigurable microstrip patch antenna which can switch between vertical and horizontal linear polarizations, left hand and right hand circular polarizations at two WLAN frequencies is presented. The orthogonal linear polarizations are achieved by a square microstrip patch antenna fed by two ports on adjacent sides. By introducing corner truncated perturbation on opposite corners of right diagonal of a square patch, orthogonal circular polarizations are achieved. By controlling the bias voltage of two PIN diodes loaded at perturbed corners, a single structure can achieve quad polarization states. Furthermore, by superimposing a square ring slot into the corner truncated square patch and incorporating four PIN diodes into the square ring slot, quad polarization are achieved at dual frequencies. Simulated and measured results indicate that the antenna can achieve quad polarization at two WLAN bands (5.15–5.35 GHz) and (5.75–5.85 GHz). The proposed antenna is simple, has low profile and can be scaled easily for other frequencies.     

应用于软件无线电的四阶可重构模拟基带滤波器

本文提出了一个应用于软件无线电的四阶可重构模拟基带滤波器。该滤波器采用有数字辅助的有源RC低通结构,可以灵活地改变滤波器的特性,比如截止频率,选择性,类型,噪声,增益和功耗。为了同时达到优化噪声和调节功耗的目的,这里采用了一种新的可配置运放结构。该芯片采用SMIC 0.13μm CMOS工艺制作。主体滤波器和频率校准电路的面积分别为1.8 × 0.8 mm2和0.48 × 0.25 mm2。测试结果表明,该滤波器可以提供巴特沃斯和切比雪夫两种响应,而且截止频率可以覆盖从280kHz 到15MHz的宽带范围,同时可调增益范围为0dB到18dB。在1.2V的电源电压下获得29dBm的IIP3。根据给定的协议,输入参考噪声密度在41 nV/Hz½ 到133 nV/Hz½之间变化,低频带和高频带模式分别消耗了5.46mW和8.74mW的功耗。     

A 4th-order reconfigurable analog baseband filter for software-defined radio applications

This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm² and 0.48×0.25 mm² areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）^1/2 according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.     

采用多核处理器进行可重构并行仿真的方法

文中对多传感器视觉信息处理算法进行分析,根据可重构处理器的并行计算参数模型提出了一种并行计算仿真的方法。多核处理器环境中,每个线程在独立的核上运行,线程间具有并发性。利用并发的线程模拟可重构阵列单元（PE）的运算方式,调用OpenMP设置多个线程并行执行,在多核计算机平台上模拟可重构处理器的计算过程。利用此方法能在没有具体的PE连接方案前,通过使用计算核模拟PE单元,将算法映射到多核处理器环境中。通过分析算法在多核计算机上的并发执行效率,来优化视觉信息算法在可重构阵列上的映射方案。     

粗粒度可重构结构的性能估计方法

在设计初期,估计粗粒度可重构结构的性能,对粗粒度可重构结构设计具有指导意义.在考虑局部数据存储器结构以及局部数据存储器与可重构阵列的接口结构的情况下,建立了粗粒度可重构结构的参数模型,使用改进的螺旋形绑定策略将应用算法DFG(Data Flow Graph)中的算子绑定到可重构阵列的处理单元上,提出了一种粗粒度可重构结构的性能估计方法.应用实例表明,在设计初期,该方法能得到周期精确的估计结果,有效地指导粗粒度可重构结构的设计.     

一种适用于极化捷变天线的可重构射频网络设计

介绍了一种适用于极化捷变天线的可重构射频网络.该射频网络由一个两路可重构Wilkinson功率分配器和两个45°/135°可重构移相器构成,通过控制PIN二极管的偏置电压,可实现两种单路（1:0和0:1）传输模式和三种两路（1:1,1:j和j:1）传输模式,即五种不同的工作模式切换.实测结果表明:该可重构射频网络在单路传输模式（相对带宽6.7%）下的插入损耗小于1.5 dB,输入端口的回波损耗大于12.1 dB;在两路传输模式（相对带宽4.3%）下的输出端口间隔离度大于23.6 dB,相位差为3.5~5.4°（1:1模式）和92.6~97.4°（1:j和j:1模式）,相位误差小于7.4°.     

Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems

In this paper, a four-stage method for synthesizing reconfigurable ASNoC topology is proposed for partially dynamically reconfigurable systems, where the topology is reconfigured dynamically at run-time along with the application's execution. Firstly, a simulated annealing based topology-aware integrated optimization framework is proposed to generate the proper schedule and floorplan of task modules. Secondly, based on the schedule and floorplan of task modules, an Integer Linear Programming (ILP)-based method and a heuristic method, are proposed to partition the communication requirements of the application into $T$ time intervals. Thirdly, we explore the proper positions of switches in the floorplan for global communications. Finally, considering the reconfiguration costs between adjacent time intervals, the routing path allocation problem is solved for time intervals in an iterative procedure to generate fine-grained dynamically reconfigurable ASNoC topologies. Experimental results show that, compared to the random partition of communication requirements, the proposed heuristic method and ILP-based method can achieve 5.4% and 10.0% power consumption improvement, respectively. And, the reconfigurable ASNoC can achieve 31.6% power consumption improvement when compared with static ASNoC.     

A New FPGA for DSP Applications Integrating BIST Capabilities

This work proposes a new FPGA architecture, to meet the requirements of signal processing and testing of current system-on-chip designs. The proposed architecture provides the hardware reuse and the reconfigurability advantages of an FPGA, not only for the system functionality, but also for the system testing, while keeping the performance level required by current signal processing applications. This paper presents the new FPGA model, along with preliminary experimental results that clearly show the possible advantages at the system level of merging design and test in a reconfigurable device.     

嵌入式可重构系统芯片的硬件验证平台设计

提出一种新的基于嵌入武可重构系统芯片的视频解码方案,采用了软硬件协同验证的方法.设计了相应的硬件验证平台,验证了H.264解码算法在可重构处理器上的可实现性.     

一种用于短距离无线通信的低功耗多频带可配置收发机

A reconfigurable multi-mode multi-band transceiver for low power short-range wireless communication applications is presented.Its low intermediate frequency(IF) receiver with 3 MHz IF carrier frequency and the direct-conversion transmitter support reconfigurable signal bandwidths from 250 kHz to 2 MHz and support a highest data rate of 3 Mbps for MSK modulation.An integrated multi-band PLL frequency synthesizer is utilized to provide the quadrature LO signals from about 300 MHz to 1 GHz for the transceiver multi-band application. The transceiver has been implemented in a 0.18μm CMOS process.The measurement results at the maximum gain mode show that the receiver achieves a noise figure(NF) of 4.9/5.5 dB and an input 3rd order intermodulation point(IIP3) of-19.6/-18.2 dBm in 400/900 MHz band.The transmitter working in 400/900 MHz band can deliver 10.2/7.3 dBm power to a 50Ωload.The transceiver consumes 32.9/35.6 mW in receive mode and 47.4/50.1 mW in transmit mode in 400/900 MHz band,respectively.     

基于Crossbar的可重构网络输入排队分域调度研究

为解决传统网络技术体系中交换结构无法满足大量差异化业务规模化应用的问题,本文基于可重构网络技术体系,采用选择关闭部分Crossbar交叉节点的分域模型,提出了分域调度的思想,分析并推导了承载组内的SDRR调度算法和域内最长队列优先调度算法。最后采用交换性能仿真平台对该调度算法进行了复杂度和时延的仿真比较,结果表明:分域调度的最长队列优先算法比一般最长队列优先算法相对复杂度低,且随着调度域个数增加,相对复杂度降低。在相同业务源输入条件下,Crossbar三分域调度算法的时延小于非分域调度算法的时延,接近公平输出排队调度算法的时延。     

A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

This paper presents a novel approach for designing a reconfigurable variable gain amplifier(VGA) for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning...     

一种新颖的可应用于多模多频接收机可配置的可变增益放大器

本文阐述了一种新颖的可应用于多模多频接收机射频前端可配置的可变增益放大器的设计方法。可变增益放大器包括增益放大电路,控制电路,直流失调消除电路和模式转换电路四个部分。这种结构可以在保证多模多频应用的前提下通过硬件复用最大化来节省芯片面积和功耗。电路采用0.18 um CMOS 工艺,在1.8V的供电电压下可实现5dB 至87dB的动态范围,电路的带宽（所有增益下）大于80 MHz。此外,直流失调消除电路有效抑制了直流失调成分至小于40mV。整个电路的功耗小于3mA,面积为705um*100um。     

一种适用于科研单位的混合组网方式

本文基于网络逻辑隔离概念,利用业务随行、VxLAN和SDN等网络新技术进行网络架构规划,在减少基础建设投资的前提下,通过精准逻辑隔离的方式对科研单位的办公网、科研网和数据中心网络进行整体架构设计.该方式在不能单独组网(传统物理隔离)的条件下实现了网络终端、服务器、试验装置的访问可控和权限可控,可保障科研单位的整体网络运...