Mechanism of hemispherical-grained Si formation for dynamic random access memory cells by rapid thermal chemical vapor deposition

An uneven coating made of hemispherical-grained Si (HSG) was formed on an amorphous Si layer by a rapid thermal chemical vapor deposition (CVD) (RTCVD) process. The uneven coating increases the effective surface area of a capacitor electrode in dynamic random access memory (DRAM) cells. The formation of the HSG consists of “seeding” and subsequent isothermal annealing stages. During the seeding stage, nanometer size Si single crystals are formed on the surface of the amorphous Si layer. During rapid thermal annealing at 665°C, under high vacuum, the Si grains grow linearly with increasing temperature and reach an average size of 95 nm after 20 sec. The nucleation and growth of the HSG occurs within a narrow range of temperature and time, which is sufficient for a short diffusion path of Si atoms on the surface of the amorphous Si layer, but insufficient for crystallization of the amorphous Si layer: The HSG coating increases the capacitance of a memory cell by a factor of 2.     

Study of Ni-Si thin-film interfacial reactions by coupling differential scanning calorimetry measurements and transmission electron microscopy analyses

In this paper, the solid-state interactions between a 500 nm thick Ni layer and a Si wafer are studied for temperatures up to 500 °C by coupling Differential Scanning Calorimetry (DSC) and Transmission Electron Microscopy (TEM). The phase transformation temperatures determined by DSC are about 250, 300, 350 and 410 °C. Dedicated samples were prepared to identify phase transformations occurring during heating up to these temperatures. TEM analyses show that the reaction product always consists of a continuous layer so that the nature of phase(s) formed at the interface can be determined. The reaction layer thickness is about 25, 50 and 150 nm for samples heated to 250, 300 and 350 °C, respectively. Moreover, from TEM diffraction patterns, it is shown that, for such a thick layer of Ni deposited on Si substrate, the first phase forming at the Ni/Si interface is the metastable Ni₃Si compound.     

Evaluation of PZT thin films on Ag coated Si substrates

Fabrication characteristics of hybrid thin film components are investigated. Lead zirconate titanate (PZT) films, thickness 10 μm, are fabricated by using laser ablation on the Ag electrode (about 1 μm thick) which is deposited on 200 μm Si substrates by evaporation. Composition close to the target material is obtained in PZT films even in air and without substrate heating. Low surface energy in the Ag−Si system causes spheroidization of the Ag layer on the fresh Si substrate, but the surface can be modified by grinding and oxidization. Only some cavities exist at the interface. The interface between the Ag electrode and PZT layer is physically continuous, as revealed by electron microscopy. After annealing at 750°C for 2 h, the PZT layer consists of the rhombohedral perovskite phase with a fraction of the pyrochlore phase. Detrimental interdiffusion between Pb and Si occurs during annealing if the PZT thin film is directly on the Si substrate. This is retarded by the presence of the Ag layer.     

Studies on the growth of CdTe on Si using ge interfacial layer in an organometallic vapor phase epitaxial system

Epitaxial CdTe layers were grown using organometallic vapor phase epitaxy on Si substrates with a Ge buffer layer. Ge layer was grown in the same reactor using germane gas and the reaction of germane gas with the native Si surface is studied in detail at low temperature. It is shown that germane gas can be used to “clean” the Si surface oxide prior to CdTe growth by first reducing the thin native oxide that may be present on Si. When Ge layer was grown on Si using germane gas, an induction period was observed before the continuous layer of Ge growth starts. This induction period is a function of the thickness of the native oxide present on Si and possible reasons for this behavior are outlined. Secondary ion mass spectrometry (SIMS) data show negligible outdiffusion and cross contamination of Ge in CdTe.     

A novel enhancement for hierarchical image coding

Hierarchical image coding usually codes a down-sampled version of an original image and then the difference between the original image and a reconstructed version that is interpolated from the down-sampled layer. In this paper, we demonstrate, for the first time, that when the bit-rate used to code the residual layer falls into a critical region (which covers almost all typical bit-rates used in practice), it often happens that all pixels in the down-sampled layer would be deteriorated if the corresponding coded residuals are added into them. To avoid this problem, we first propose a “naive” solution: no coded residuals will be added back into the down-sampled layer; whereas coded residuals will be added only into the interpolated pixels. Then, we propose to apply a constrained quantization technique during the coding of the residual layer so that all residual pixels at the interpolated positions will end up with an improved quality. To verify its effectiveness, we conduct extensive tests to show that the gap between the hierarchical coding scheme and its single-level counterpart (which is typically around 2–3 dB in the 2-level hierarchy) will be filled up by a rather big percentage.     

质子辐射导致CCD热像素产生的机制研究

空间高能质子作用于电荷耦合器件(CCD)产生的热像素是空间成像系统性能退化的主要原因之一。为深入认识质子辐射导致CCD产生热像素的规律和机制,对行间转移CCD进行了不同能量(3,10,23 MeV)的质子辐射试验,研究了辐射导致CCD暗信号的退化和热像素产生的规律。试验结果表明,在较低辐射注量1E9 p/cm²下,CCD的暗信号退化很小,但热像素急剧增加。质子辐射能量越大,产生的热像素数量越多。结合粒子输运计算与理论分析表明,热像素产生原因是质子与半导体材料中的原子非弹性碰撞而形成的团簇缺陷。     

Traps with near-midgap energies at the bonded Si/SiO<Subscript>2</Subscript> interface in silicon-on-insulator structures

Capture centers (traps) are studied in silicon-on-insulator (SOI) structures obtained by bonding and hydrogen-induced stratification. These centers are located at the Si/SiO₂ interface and in the bulk of the split-off Si layer. The parameters of the centers were determined using charge deep-level transient spectroscopy (Q-DLTS) with scanning over the rate window at fixed temperatures. Such a method allows one to study the traps near the Si midgap at temperatures near 295 K. It is shown that the density of traps with a continuous energy spectrum, which are located at the bonded Si/SiO₂ interface, decreases by more than four orders of magnitude at the mid-gap compared with the peak density observed at the activation energy E _a ≈0.2–0.3 eV. The capture centers are also found in the split-off Si layer of the fabricated SOI structures. Their activation energy at room temperature is E _a =0.53 eV, the capture cross section is 10^?19 cm², and the concentration is (0.7–1.7)×10¹³ cm^?3. It is assumed that these capture centers are related to deep bulk levels induced by electrically active impurities (defects) in the split-off Si layer close to the Si/SiO₂ interface.     

Special features of the formation of Ge(Si) islands on the relaxed Si1−xGex/Si(001) buffer layers

The results of studying the growth of self-assembled Ge(Si) islands on relaxed Si_1?xGe_x/Si(001) buffer layers (x≈25%), with a low surface roughness are reported. It is shown that the growth of self-assembled islands on the buffer SiGe layers is qualitatively similar to the growth of islands on the Si (001) surface. It is found that a variation in the surface morphology (the transition from dome-to hut-shaped islands) in the case of island growth on the relaxed SiGe buffer layers occurs at a higher temperature than for the Ge(Si)/Si(001) islands. This effect can be caused by both a lesser mismatch between the crystal lattices of an island and the buffer layer and a somewhat higher surface density of islands, when they are grown on an SiGe buffer layer.     

Effects of Si interlayer conditions on platinum ohmic contacts for p-type silicon carbide

A study of Pt ohmic contacts with Si interlayers on p-type SiC (7.0×10¹⁸ cm⁻³) was performed as a function of the Si interlayer thickness, deposition temperature, and dopant incorporation. All contacts were ohmic after annealing at 1100°C for 5 min in vacuum. The use of a Si layer was found to decrease the specific contact resistance (SCR) relative to Pt contacts that did not contain Si, regardless of the deposition conditions used in this study. The SCR values were reduced further by three independent effects: the deposition of the Si layer at 500°C, the incorporation of B in the layer, and the design of the Pt:Si layer thicknesses in a 1:1 atomic ratio. By combining all of these effects, the lowest average SCR values (2.89×10⁻⁴ Ω cm²) were obtained. After annealing for 5 min at 1100°C, x-ray diffraction of the contacts with the 1:1 Pt:Si ratio showed a single phase of PtSi. Analyses by cross-sectional transmission electron microscopy revealed no reaction of the films with the SiC substrate. The electrical characteristics of these contacts were stable after annealing at 400°C and 600°C for 96 h and 60 h, respectively. These results are in contrast to those observed for pure Pt contacts and for contacts containing a higher Pt:Si ratio.     

Visibility of Si nanoparticles embedded in an amorphous SiO2 matrix

The visibility of a Si crystalline nanoparticle of diameter 2 nm embedded in an amorphous SiO(2) layer is evaluated quantitatively by multislice calculation. The visibility depends on the crystal orientation of the Si nanoparticle, the thickness of the amorphous SiO(2) layer and the defocus. Scherzer defocus always gives the highest visibility at any crystal orientation. The visibility is higher when the incident beam is parallel to the (111) planes and the (111) fringes are most visible. The image of a Si nanoparticle is obscured by random images from the amorphous SiO(2) layer and the Si nanoparticle becomes invisible when it is misoriented or the amorphous layer is thicker than 60 nm. The probability that a Si nanoparticle can be distinguished from the random noise of amorphous images is 89% when the thickness of the amorphous SiO(2) layer is 12 nm, but this is reduced to 21% when the layer is 48 nm thick. These quantitative results are useful when estimating the density of Si nanoparticles including invisible nanoparticles.     

Comparative life‐cycle energy payback analysis of multi‐junction a‐SiGe and nanocrystalline/a‐Si modules

Despite the publicity of nanotechnologies in high tech industries including the photovoltaic sector, their life‐cycle energy use and related environmental impacts are understood only to a limited degree as their production is mostly immature. We investigated the life‐cycle energy implications of amorphous silicon (a‐Si) PV designs using a nanocrystalline silicon (nc‐Si) bottom layer in the context of a comparative, prospective life‐cycle analysis framework. Three R&D options using nc‐Si bottom layer were evaluated and compared to the current triple‐junction a‐Si design, i.e., a‐Si/a‐SiGe/a‐SiGe. The life‐cycle energy demand to deposit nc‐Si was estimated from parametric analyses of film thickness, deposition rate, precursor gas usage, and power for generating gas plasma. We found that extended deposition time and increased gas usages associated to the relatively high thickness of nc‐Si lead to a larger primary energy demand for the nc‐Si bottom layer designs, than the current triple‐junction a‐Si. Assuming an 8% conversion efficiency, the energy payback time of those R&D designs will be 0.7–0.9 years, close to that of currently commercial triple‐junction a‐Si design, 0.8 years. Future scenario analyses show that if nc‐Si film is deposited at a higher rate (i.e., 2–3 nm/s), and at the same time the conversion efficiency reaches 10%, the energy‐payback time could drop by 30%. Copyright © 2010 John Wiley & Sons, Ltd.     

Fabrication of thick, high-quality strained SiGe layer on ultra-thin silicon-on-insulator and modeling of film strain

Fabrication of a thick strained SiGe layer on bulk silicon is hampered by the lattice mismatch and difference in the thermal expansion coefficients between Si and SiGe, and a high Ge content leads to severe strain in the SiGe film. When the thickness of the SiGe film is above a critical value (90 nm for 18% Ge), drastic deterioration of the film properties as well as dislocations will result. In comparison, a silicon-on-insulator (SOI) substrate with a thin top Si layer can mitigate the problems and so a thick SiGe layer with high Ge concentration can conceivably be synthesized. In the work reported here, a 110 nm thick high-quality strained Si_0.82Ge_0.18 layer was fabricated on an ultra-thin SOI substrate with a 30 nm top silicon layer using ultra-high vacuum chemical vapor deposition (UHVCVD). The thickness of the SiGe layer is larger than the critical thickness on bulk Si. Cross-sectional transmission electron microscopy (XTEM) reveals that the SiGe layer is dislocation-free and the atoms at the SiGe/Si interface are well aligned, even though X-ray diffraction (XRD) data indicate that the SiGe film is highly strained. The strain factors determined from the XRD and Raman results agree well.     

Growth of high quality CdTe and ZnTe on Si substrates using organometallic vapor phase epitaxy

Epitaxial (100) CdTe and ZnTe layers with high crystalline quality have been grown on Si substrates by atmospheric pressure organometallic vapor phase epitaxy (OMVPE). A thin Ge interfacial layer grown at low temperature was used as a buffer layer prior to ZnTe and CdTe growth. The layers were characterized by Nomarski optical microscopy and double crystal x-ray diffraction. Double crystal rocking curves with full width at half maximum of about 110 and 250 arc-sec have been obtained for a 7 μm thick ZnTe layer and a 4 μm thick CdTe layer, respectively. The results presented demonstrate a novel method ofin-situ Si cleaning step without a high temperature deoxidation process to grow high quality CdTe and ZnTe on Si in a single OMVPE reactor.     

Formation of nickel disilicide using nickel implantation and rapid thermal annealing

Transmission electron microscopy (TEM), secondary ion mass spectroscopy (SIMS), and x-ray photoemission spectroscopy (XPS) have been used to investigate the nucleation, growth, and ripening behavior of nickel-disilicide precipitates formed by Ni implantation in an amorphous-Si layer on (100) Si and followed by a two-step annealing treatment. The TEM and XPS results show that amorphous-disilicide precipitates are formed in a depth of ∼21 nm in the amorphous-Si layer when pre-annealed at 380°C for 30 sec. It is also shown that the second-step annealing at temperatures in the range of 450–600°C causes the amorphous precipitates to transform to randomly oriented crystalline ones embedded in the amorphous-Si layer. Annealing above 550°C is shown to induce the crystallization of amorphous Si by solid-phase epitaxial growth (SPEG). It is further shown that, in a prolonged annealing at high temperatures, the disilicide has dissolved and reprecipitated on the Si surface. Based on the roles of the silicide-mediated crystallization (SMC), the dissolution and reprecipitation of silicides, and SPEG, possible mechanisms are given to explain how the surface-disilicide islands are formed during annealing at temperatures of 550–950°C.     

硅基HgCdTe面阵焦平面器件结构热应力分析

红外焦平面器件是一个多层结构,包含外延衬底、HgCdTe芯片、Si读出电路、互连In柱、粘结胶以及引线基板等,由于各层材料之间的热膨胀系数不同导致焦平面器件在工作中承受很大的热应力,热应力是导致红外焦平面器件失效的重要因素之一。本文运用一维模型以及有限元分析方法对硅基HgCdTe320×240焦平面器件结构进行热应力分析,结果表明,改变Si衬底厚度、粘结胶的杨氏模量以及基板的热膨胀系数,都会不同程度地影响HgCdTe薄膜上的受力,其中基板的热膨胀系数对HgCdTe薄膜所受的应力影响最大。通过选用合适的基板可以有效降低HgCdTe薄膜所受的应力,从而降低器件失效率。     

Reduction of the off-state current of polysilicon thin-filmtransistors by means of a polysilicon buffer layer

The off state current for polysilicon thin-film transistors for pixels in LCDs has been successfully reduced by introducing a polysilicon buffer layer between a polysilicon active layer fabricated by solid-phase-crystallisation (SPC) and a fused quartz substrate. Off-slate current of less than 1 pA under V_gs=-25 V at V_ds=3 V was obtained for n-channel single-gate coplanar transistors using the buffer layer (400 Å)     

Low threading dislocation density Ge deposited on Si (1 0 0) using RPCVD

Epitaxial Ge layer growth of low threading dislocation density (TDD) and low surface roughness on Si (1 0 0) surface is investigated using a single wafer reduced pressure chemical vapor deposition (RPCVD) system. Thin seed Ge layer is deposited at 300 °C at first to form two-dimensional Ge surface followed by thick Ge growth at 550 °C. Root mean square of roughness (RMS) of ∼0.45 nm is achieved. As-deposited Ge layers show high TDD of e.g. ∼4 × 10⁸ cm⁻² for a 4.7 μm thick Ge layer thickness. The TDD is decreasing with increasing Ge thickness. By applying a postannealing process at 800 °C, the TDD is decreased by one order of magnitude. By introducing several cycle of annealing during the Ge growth interrupting the Ge deposition, TDD as low as ∼7 × 10⁵ cm⁻² is achieved for 4.7 μm Ge thick layer. Surface roughness of the Ge sample with the cyclic annealing process is in the same level as without annealing process (RMS of ∼0.44 nm). The Ge layers are tensile strained as a result of a higher thermal expansion coefficient of Ge compared to Si in the cooling process down to room temperature. Enhanced Si diffusion was observed for annealed Ge samples. Direct band-to-band luminescence of the Ge layer grown on Si is demonstrated.     

Surface nanocrystalline Si structure and its surface passivation for highly efficient black Si solar cells

19.5% conversion efficiency crystalline silicon (Si) solar cells having simple structure without antireflection coating have been fabricated using the surface structure chemical transfer method which produces a nanocrystalline Si layer simply by contacting catalytic platinum with Si wafers in hydrogen peroxide plus hydrofluoric acid solutions. The reflectivity becomes less than 3% after the surface structure chemical transfer method due to formation of black Si. Deposition of phosphosilicate glass and heat treatment at 925 °C performed for formation of pn‐junction effectively passivate the nanocrystalline Si surface. With this phosphosilicate glass passivation plus the hydrogen treatment at 400 °C, the internal quantum efficiency is greatly improved and reaches 81% at a wavelength of 400 nm. Analysis of ellipsometry data shows that incident light with wavelength shorter than 400 nm is almost completely absorbed by the nanocrystalline Si layer. The high internal quantum efficiency for short wavelength light is attributed to effective surface passivation and the nanocrystalline Si layer band‐gap energy which decreases with the distance from the top of the network structure of the nanocrystalline Si layer. Copyright © 2017 John Wiley & Sons, Ltd.     

A Solution‐Processed UV‐Sensitive Photodiode Produced Using a New Silicon Nanocrystal Ink

This article presents a simple and effective method of functionalizing hydrogen‐terminated silicon (Si) nanocrystals (NCs) to form a high‐quality colloidal Si NC ink with short ligands that allow charge transport in nanocrystal solid films. Si NCs fabricated by laser‐pyrolysis and acid etching are passivated with allyl disulfide via ultraviolet (UV)‐initiated hydrosilylation to form a stable colloidal Si NC ink. Then a Si NC‐based photodiode is directly fabricated in air from this ink. Only a solution‐processed poly(3,4‐ethylenedioxy‐thiophene):poly(styrene sulfonate) (PEDOT: PSS) electron blocking layer and top‐ and bottom‐contacts are needed along with the Si NC layer to construct the device. A Schottky‐junction at the interface between the Si NC absorber layer and aluminum (Al) back electrode drives charge separation in the device under illumination. The unpackaged Si NC‐based photodiode exhibites a peak photoresponse of 0.02 A W^?1 to UV light in air, within an order of magnitude of the response of commercially available gallium phosphide (GaP), gallium nitride (GaN), and silicon carbide (SiC) based photodetectors. This provides a new pathway to large‐area, low‐cost solution‐processed UV photodetectors on flexible substrates and demonstrates the potential of this new silicon nanocrystal ink for broader applications in solution‐processed optoelectronics.     

SIMOX材料顶层硅膜中残余氧的行为

利用光致发光谱 (PL)和二次离子质谱 (SIMS)检测了不同退火条件下处理的 SIMOX材料的顶层硅膜 .实验结果显示 ,SIMOX顶层硅膜的 PL 谱有三个峰 :它们是能量为 1.10 e V的 a峰、能量为 0 .77e V的 b峰和能量为0 .75 e V的 c峰 .与 RBS谱相比 ,发现 a峰峰高及 b/ a峰值比是衡量顶层硅膜单晶完整性的标度 .谱峰 b起源于SIMOX材料顶层硅膜中残余氧 ,起施主作用 .SIMS测试结果显示 ,谱峰 c来源于 SIMOX材料顶层硅膜中的碳和氮 .