Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis

We address the problem of code generation for embedded DSP systems. In such systems, it is typical for one or more digital signal processors (DSPs), program memory, and custom circuitry to be integrated onto a single IC. Consequently, the amount of silicon area that is dedicated to program memory is limited, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints, which may include hard real-time constraints. Unfortunately, existing compiler technology is unable to generate dense, high-performance code for DSPs since it does not provide adequate support for the specialized architectural features of DSPs. These specialized features not only allow for the fast execution of common DSP operations, but they also allow for the generation of dense assembly code that specifies these operations. Thus, system designers often hand-program the embedded software in assembly, which is a very time-consuming task. In this paper, we focus on providing compiler support for one particular specialized architectural feature, namely the paged absolute addressing mode – this feature is found in two commercial DSPs, the Texas Instruments' TMS320C25 and TMS320C50 fixed-point DSPs; however, it may also be featured in application-specific processors (ASIPs). We present some machine-dependent code optimizations that improve code density by exploiting this architectural feature. Experimental results demonstrate that for a set of typical DSP benchmarks, some of our optimizations reduce overall code size and data memory consumption by an average of 5.0% and 16.0%, respectively. Our experimental vehicle throughout this research is the TMS320C25.     

Address Generation Optimization for Embedded High-Performance Processors: A Survey

Nowadays embedded systems are growing at an impressive rate and provide more and more sophisticated applications characterized by having a complex array index manipulation and a large number of data accesses. Those applications require high performance specific computation that general purpose processors can not deliver at a reasonable energy consumption. Very long instruction word architectures seem a good solution providing enough computational performance at low power with the required programmability to speed up the time to market. Those architectures rely on compiler effort to exploit the available instruction and data parallelism to keep the data path busy all the time. With the density of transistors doubling each 18 months, more and more sophisticated architectures with a high number of computational resources running in parallel are emerging. With this increasing parallel computation, the access to data is becoming the main bottleneck that limits the available parallelism. To alleviate this problem, in current embedded architectures, a special unit works in parallel with the main computing elements to ensure efficient feed and storage of the data: the address generator unit, which comes in many flavors. Future architectures will have to deal with enormous memory bandwidth in distributed memories and the development of address generators units will be crucial for effective next generation of embedded processors where global trade-offs between reaction-time, bandwidth, energy and area must be achieved. This paper provides a survey of methods and techniques that optimize the address generation process for embedded systems, explaining current research trends and needs for future.

Code Optimization Techniques in Embedded DSP Microprocessors

We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventional code generation methods typically result in inefficient code. In this paper we formulate and solve some optimization problems that arise in code generation for processors with irregular datapaths. In addition to instruction scheduling and register allocation, we also formulate the accumulator spilling and mode selection problems that arise in DSP microprocessors. We present optimal and heuristic algorithms that determine an instruction schedule simultaneously optimizing accumulator spilling and mode selection. Experimental results are presented.     

基于数字信号处理器的同步型波控系统

论述了基于多片数字信号处理器的同步型波控系统。由于相位计算是用软件实现的，硬件电路十分简单，功能较强。文章重点论述了这种波控系统的原理、组成和同步问题。     

基于MATLAB的SVPWM算法自动代码生成技术研究

摘要：针对DSP编程复杂,开发周期长的问题,给出了一种运用Matlab软件、Code Composer Studio（CCS）软件及其内嵌工具和链接软件自动生成SVPWM代码的方法。利用Matlab/Simulink仿真软件建立了相应的算法模型,验证模型的正确性之后,自动生成代码,并编译、下载到DSP平台中运行,产生的波形与理论相吻合。与手工编写代码的方法相比较,该方法简单易行,开发周期短,生成代码效率高。     

LS-DSP地址产生器生成算法与逻辑实现

由于传统的内嵌地址产生器不能有效地支持数字信号处理应用的需要,在开发面向航天应用的高速信号处理器LS-DSP时,设计支持数字信号处理应用的地址产生器成为LS-DSP开发中的重要环节。本文通过研究常用的数字信号处理计算的数据地址运算特点,提出了LS-DSP地址产生器的生成算法。在根据该算法逻辑实现LS-DSP地址产生器时,为了减小地址产生器面积,针对循环类地址计算又提出了一种快速的动态START、END产生方法。实验结果表明,LS-DSP使用本文的地址产生器比采用传统的地址产生器可有效的提高数字信号处理运算的速度。     

动目标检测雷达数字信号处理机自测试研究

根据ＭＴＤ 雷达数字信号处理机的特点,分别讨论了信号域测试与数据域测试的内建自测试（ＢＩＳＴ）方法,提出了一种新的数据域ＢＩＳＴ方法,并计算了这种测试方法的故障覆盖率．该方法已成功地应用于某ＭＴＤ雷达数字信号处理机．     

A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such as many general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, a QCELP vocoder, and an MPEG video decoder. The effects of CPU clock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.     

最差性能最优通用信号模型稳健波束形成算法

针对空间分布散射信号源的稳健波束形成问题,提出了一种新的通用信号模型稳健波束形成算法,不仅得到了封闭形式的最优加权矢量,而且获得了最优的性能改善.其中分析了与传统对角加载的关系,给出了最优加载量的计算方法,并得出具有最优负加载的解才可以获得最优的性能改善.最后的仿真分析验证了所提出算法的正确性和有效性,而且发现最优加权矢量只取决于给定的接收数据和未知的失配量,与失配约束参数的选择无关,而失配约束参数只是参与最优权计算的辅助参数.     

面向实时数字信号系统关键链路延时的NoC映射方法研究

该文在面向功耗优化的经典NoC设计平台和映射算法基础上,针对实时数字信号处理电路固有的实时性特征,提出了一种新的面向最小化系统关键链路延时的NoC自主映射模型MM-Map。该模型在满足处理单元处理容限和链路带宽的约束下,采用基本遗传算法完成延时目标的优化求解。实验结果表明,该模型能节约一定硬件资源的消耗,得到近似全局最优延时解,映射过程简单,收敛效果好。     

用于快速扩谱码捕获的数字匹配滤波器

提出了高速数字伪码匹配滤波器的几种实现方案,评估了其性能,比较了方案之间的优劣。模拟及电路综合的结果表明,文中提出的方案可以使器件工作于２５ Ｍ Ｈｚ 以上的速度,能满足绝大多数现有系统的要求。     

一种新的信号识别和扩频码捕获(SR/CA)算法

DS-SS系统中信号识别和扩频码捕获(SR/CA)会存在检测概率和虚警概率难以同时优化的矛盾,在分析现有SR/CA算法的基础上,提出了一种带有频偏估计的软SR/CA算法。通过引入高低双重判决门限和频偏估计校正环路,该算法在保持较低的虚警概率的条件下能提高信号的检测概率。数值仿真结果表明,软SR/CA算法结构相对传统的SR/CA算法能在检测概率和虚警概率之间取得较好的折衷。