The stability of polycrystalline silicon thin film resistors measured using excess noise

The resistance of thin films of polycrystalline silicon prepared by chemical vapour deposition is found to vary with time and with cycling the temperature or strain. These variations of resistance are compared with the magnitude and variations of the excess, , noise which is known to be an equilibrium resistance fluctuation. The noise is found to be sensitive to the detailed state of the specimen.     

A new computer-aided simulation model for polycrystalline silicon film resistors

A general transport theory for the I–V characteristics of a polycrystalline film resistor has been derived by including the effects of carrier degeneracy, majority-carrier thermionic-diffusion across the space charge regions produced by carrier trapping in the grain boundaries, and quantum mechanical tunneling through the grain boundaries. Based on the derived transport theory, a new conduction model for the electrical resistivity of polycrystalline film resitors has been developed by incorporating the effects of carrier trapping and dopant segregation in the grain boundaries. Moreover, an empirical formula for the coefficient of the dopant-segregation effects has been proposed, which enables us to predict the dependence of the electrical resistivity of phosphorus-and arsenic-doped polycrystalline silicon films on thermal annealing temperature.Phosphorus-doped polycrystalline silicon resistors have been fabricated by using ion-implantation with doses ranged from 1.6 × 10¹¹ to 5 × 10¹⁵/cm². The dependence of the electrical resistivity on doping concentration and temperature have been measured and shown to be in good agreement with the results of computer simulations. In addition, computer simulations for boron-and arsenic-doped polycrystalline silicon resistors have also been performed and shown to be consistent with the experimental results published by previous authors.     

Reliability of polysilicon thin film resistors with irreversible resistance transition

In this paper, the results of reliability testing (life testing at 125°C for 2000 h) and failure analysis of polysilicon thin film resistors with irreversible resistance transition are presented and discussed. The results of the life test show that electrical parameters of the polysilicon resistors (resistance before transition, transition voltage and resistance after transition) are satisfactorily stable during the life test. Also, calculated values of the mean time before failure (MTBF) and the mean time to failure (MTTF) on the basis of the life test data confirm that the polysilicon resistors have a satisfactory level of reliability for long-term applications. Finally, the results of failure analysis show that typical failure modes of the polysilicon resistors are open, while the responsible failure mechanism is electromigration of aluminum during the life test at the contact between the aluminum line and polysilicon film.     

快速热退火制备多晶硅薄膜的研究

采用等离子体增强化学气相沉积法(PECVD)沉积非晶硅薄膜,然后在快速热退火炉中进行退火。研究了升温速率、降温速率对晶化的影响。结果表明:退火中,升温速率越大,越不利于晶核的形成;降温速率较小时(100℃/60s),形成的晶粒尺寸较小,晶化情况较好,晶化率估算达64.56%。     

Gigaohm-range polycrystalline silicon resistors for microelectronic applications

The objective of this work was to investigate the conduction properties of very high resistance devices formed from undoped chemical-vapor-deposited polycrystalline silicon. Test structures having resistances as high as 600 GΩ at 5 V were fabricated, of a size suitable for microelectronic device applications. Detailed measurements of current-voltage characteristics in the dark and with photoexcitation, the effect of resistor length, and the temperature dependence of resistance, were made. The data is interpreted in terms of a model based on avalanche breakdown of the reverse-biased n⁺-i junction, with the current limited by the remaining quasi-neutral i-region. Theoretical current-voltage curves and the dependence of effective resistance on device length are calculated with the model, showing all the qualitative aspects of the data. Incorporation of gigaohm-range load resistors into a 16K CMOS static RAM cell is described. The work shows the dominant effects of grain boundaries in controlling current transport in undoped polysilicon, providing high-diffusivity paths for impurity diffusion, and apparently determining the reverse breakdown behavior of the junctions present.     

Modeling and optimization of monolithic polycrystalline silicon resistors

The processing parameters of monolithic polycrystalline silicon resistors are examined, and the effect of grain size on the sensitivity of polysilicon resistivity versus doping concentration is studied theoretically and experimentally. Because existing models for polysilicon do not accurately predict resistivity dependence on doping concentration as grain size increases above 600 Å, a modified trapping model for polysilicon with different grain sizes and under various applied biases is introduced. Good agreement between theory and experiments demonstrates that an increase in grain size from 230 to 1220 Å drastically reduces the sensitivity of polysilicon resistivity to doping levels by two orders of magnitude. Such an increase is achieved by modifications of the integrated-circuit processes. Design criteria for the optimization of monolithic polysilicon resistors have also been established based on resistivity control, thermal properties, and device geometry.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Hydrogenation of polycrystalline silicon thin film transistors byplasma ion implantation

Both n- and p-channel polycrystalline silicon (poly-Si) thin film transistors (TFT's) have been hydrogenated using the plasma ion implantation (PII) technique. Significant improvements in device characteristics have been obtained. Because PII is capable of greater dose rates than plasma immersion, it allows for significantly shorter process times than other methods investigated thus far     

Electrical trimming of heavily doped polycrystalline silicon resistors

The newly discovered phenomenon of resistance decrease in heavily doped polycrystalline silicon resistors by conduction of high current densiy has been investigated experimentally. Threshold values exist for the impurity concentration and for the applied current density for the occurrence of this phenomenon. Decreased resistance is stable as far as current higher than the threshold value is not applied thereafter. Applications to D/A converters and operational amplifiers are described. Electrical trimming of resistors in the circuits with accuracy of ±0.01 percent is easily attained.     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

Termination materials for thin film resistors

The resistance of a thin film resistor can be considered as consisting of three parts: 1) the resistance of the resistor material, 2) the resistance of the termination material, and 3) the interfacial resistance. The aging of the interfacial resistance can dominate the aging of low valued resistors, especially under corrosive conditions. The interfacial resistance using a distributed parameter analysis is treated and a figure of merit which can be used to describe the aging of the interface is defined. Also, a sensitive method of measuring this quantity is introduced and a sampling of data on several different termination material systems is presented. The best results were obtained with Ti-Pd-Au. The conclusions drawn from the figure of merit are corroborated by adhesion and thermocompression bond strength studies.     

Low temperature polycrystalline silicon thin film transistor withsilicon nitride ion stopper

The authors have fabricated a new low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) with silicon nitride (SiN _x) ion-stopper and laser annealed poly-Si. The fabricated poly-Si TFT using SiN_x as the ion-stopper as well as the gate insulator exhibited a field effect mobility of 110 cm²/Vs, subthreshold voltage of 5.5 V, subthreshold slope of 0.48 V/dec., and on/off current ratio of ~10⁶. Low off-state leakage current of 2.4×10^-2 A/μm at the drain voltage of 5 V and the gate voltage of -5 V was achieved     

A compatible technique for the formation of thin tantalum film resistors on silicon integrated circuits

A problem in the production of silicon integrated circuits has been yield limitation and applicability restriction due to the large variation and temperature sensitivity of diffused silicon resistors. Use of a thin-film resistive complement on silicon integrated circuits improves performance of many microcircuits heretofore made by the silicon planar process alone. The technique for thin-film on silicon integrated circuits is based on a two-metal resistor-conductor system: tantalum and aluminum. Tantalum was selected as the resistive material because it can be cathodically sputtered with ease, and a wide range of specific resistivity is available as a result of the controlled energy sputtering technique. The process involves production of the active element part of the circuit with standard silicon integrated circuit planar techniques, including contacting the cuts with deposited aluminum. The only deviation from the standard process lies in leaving some unetched SiO2surface area for resistor deposition. Tantalum is cathodically sputtered over the wafer, and delineated by standard photolithographic techniques to form resistor, conductor, and pad areas. A second layer of aluminum is then vacuum deposited over the wafer, and this is delineated to cover the pad and conductor areas of the tantalum with a high conductivity overlay. The exposed tantalum is then thermally stabilized and the final sheet resistivity adjusted by the resulting controlled sheet resistivity increase. The resulting circuits contain stable resistors with tolerance distributions of ±5 percent to ±10 percent, and TCR of -200 to -300 PPM/°C. The silicon active elements in the circuits do not degrade as a result of the thin-film resistor formation.     

激光直写制备薄膜铂电阻技术研究

为了研究激光直写技术在制备薄膜铂电阻中的应用,采用激光直写制备了薄膜厚度为2m的铂电阻。探讨了激光直写技术制备薄膜铂电阻的原理,以条形铂电阻为例,研究了激光参量对铂电阻形状的影响,在最优的激光脉冲频率18kHz、激光扫描速率100mm/s的参量下,制备了实际电阻约为0.37的条形薄膜铂电阻,最后检验了薄膜铂电阻的电阻值。结果表明,铂电阻的宽度分别随激光脉冲频率和激光扫描速率的增大而增大;制备的电阻边缘整齐,表面平整,电阻实际值与理论值只有0.8%的相对误差,吻合很好。     

Improving hydrogenation efficiency of polycrystalline silicon thin film transistors by a new approach

In this paper, a new hydrogenation process of poly-Si thin film for the fabrication of poly-Si thin film transistors (TFTs) is proposed. In the new approach, the hydrogenation of TFTs is performed before deposition of contact metal. N-channel and p-channel poly-Si TFTs with various channel lengths and widths were fabricated with the new and conventional processes for comparison. The results verified that the efficiency of hydrogenation has been improved remarkably by the new process. The field-effect mobility of carriers, the on state current, threshold voltage and the on/off states current ratio have been greatly improved, and the trap state density has been reduced significantly.     

High performance low temperature metal-induced unilaterallycrystallized polycrystalline silicon thin film transistors forsystem-on-panel applications

Thin film transistors (TFTs) with low-temperature processed metal-induced laterally crystallized (MILC) channels and self-aligned metal-induction crystallized (MIC) source and drain regions have been demonstrated recently as potential devices for realizing electronics on large-area, inexpensive glass panels. While these TFTs are better than their solid-phase crystallized counterparts in many device performance measures, they suffer from higher off-state leakage current and early drain breakdown. A new technology is proposed, employing metal-induced-unilateral crystallization (MIUC), which results in the removal from the edges of and within the channel region all major grain boundaries transverse to the drain current flow. Compared to the conventional “bilateral” MILC TFTs, the new MIUC devices are shown to have higher field-effect mobility, significantly reduced leakage current, better immunity to early drain breakdown, and much improved spatial uniformity of the device parameters. Thus they are particularly suitable for realizing low temperature CMOS systems on inexpensive glass panels     

An experimental study of the thermally activated processes in polycrystalline silicon thin film transistors

The thermally activated mechanisms that determine the electrical properties of polycrystalline silicon thin film transistors have been investigated. The study employed devices fabricated on long grains and different thickness polycrystalline films, which were obtained by excimer laser annealing crystallization. The transfer and the transient characteristics have been recorded and analysed in the linear operation regime. The temperature dependence of basic parameters such as leakage current, subthreshold swing and drain current overshoot transient amplitude was found to stem from the same thermally activated carriers generation mechanism. The dependence of thermally activated mechanisms on the film thickness suggests that the device operation is strongly related to polycrystalline material properties.     

Influence of polysilicon film thickness on radiation response of advanced excimer laser annealed polycrystalline silicon thin film transistors

This paper presents results of gamma irradiation effects in advanced excimer laser annealed polysilicon thin film transistors realized in polysilicon films having different thicknesses. It is shown that the thickness of polysilicon film has a strong influence on the degradation level of electrical parameters of irradiated thin film transistors, offering a possibility for optimization of these devices with the purpose to increase their reliability. The analysis was performed by monitoring of important electrical parameters, as well as of the density of irradiation induced oxide trapped charge and interface traps at the oxide–polysilicon interface, and the density of polysilicon grain boundary traps in the channel region of the transistors.