高速多级时钟网布线

提出了一种新的加载缓冲器的时钟布线算法.该算法根据时钟汇点的分布情况,在时钟布线之前对缓冲器进行预先布局,并将时钟树的拓扑生成及实体嵌入和层次式的缓冲器布局方法有机结合起来,使布线情况充分反映缓冲器对时钟网结构的影响.实验证明,与将缓冲器插入和布局作为后处理步骤相比,缓冲器预先插入和布局在很大程度上避免了布线的盲目性,并能更加有效地实现各时钟子树的延迟和负载的平衡.     

高速多级时钟网布线

提出了一种新的加载缓冲器的时钟布线算法 .该算法根据时钟汇点的分布情况 ,在时钟布线之前对缓冲器进行预先布局 ,并将时钟树的拓扑生成及实体嵌入和层次式的缓冲器布局方法有机结合起来 ,使布线情况充分反映缓冲器对时钟网结构的影响 .实验证明 ,与将缓冲器插入和布局作为后处理步骤相比 ,缓冲器预先插入和布局在很大程度上避免了布线的盲目性 ,并能更加有效地实现各时钟子树的延迟和负载的平衡 .     

用于协议一致性测试序列生成的状态规范化算法

这篇论文提出了一种方法，把ＥＦＳＭ描述协议的广泛性和ＦＳＭ测试序列生成方法的成熟性有机的结合起来，较圆满地解决了测试序列的可执行性、观察性、控制性问题，同时兼顾了数据流和控制流的全面测试。这种方法是基于两边靠拢的思想，一方面将非确定性的ＥＦＳＭ向确定性的ＤＦＳＭ规范化，另一方面修改ＦＳＭ的测试序列生成算法，使之能够同时测试数据流，也即能够处理输入、输出原语的参数问题。在本文中讲述了第一步的工作，提出了由ＥＦＳＭ到ＤＦＳＭ的规范化算法和其概念的严格定义，建立了用于算法描述和实现的ＥＦＳＭ向图概念。同时选择了一个较能完全体现ＥＦＳＭ特点的Ｑ．９２１协议讲述了其实现     

光波分复用技术讲座：第二章 掺铒光纤放大器的原理及其在DWDM中的应用

掺铒光纤放大器（ＥＤＦＡ）已成为密集波分复用（ＤＷＤＭ）系统中最关键的组成部分,从ＥＤＦＡ的原理出发,描述其工作过程,并简要介绍了各种状态下的性能特点。在ＤＷＤＭ系统中,ＥＤＦＡ同时放大多个波长,并级联使用,带来了功率及增益平衡等新问题,结合波分复用（ＷＤＭ）系统,讨论了ＥＤＦＡ的增益及功率均衡问题,对目前广泛使用的平衡增益和稳定功率的几种方法进行比较。     

砷化镓ASIC电路实用库的研究

本文提出了一种以ＧａＡｓＭＥＳＦＥＴ双层金属布线工艺和ＳＤＦＬ电路形式为基础的ＧａＡｓ６００门门阵列基片的结构，阐述了实用ＧａＡｓ单元库的设计准则和方法，并以全加器为例说明了宏单元库的电路形式、几何结构、内部布线及输入输出的考虑．实用ＧａＡｓ门阵列设计系统已在ＣＯＭＰＡＣＡＤ工作站上建立，文中给出一个用该系统设计的应用实例．     

深亚微米PESD MOSFET特性研究及优化设计

本文对多晶抬高源漏（ＰＥＳＤ）ＭＯＳＦＥＴ的结构作了描述，并对深亚微米ＰＥＳＤＭＯＳ－ＦＥＴ的特性进行了模拟和研究，看到ＰＥＳＤＭＯＳＦＥＴ具有比较好的短沟道特性和亚阈值特性，其输出电流和跨导较大，且对热载流子效应的抑制能力较强，因此具有比较好的性能．给出了ＰＥＳＤＭＯＳＦＥＴ的优化设计方法．当ＭＯＳＦＥＴ尺寸缩小到深亚微米范围时，ＰＥＳＤＭＯＳ－ＦＥＴ将成为一种较为理想的器件结构     

深亚微米PESD MOSFET特性研究及优化设计

本文对多晶抬高源漏（ＰＥＳＤ）ＭＯＳＦＥＴ的结构作了描述，并对深亚微米ＰＥＳＤＭＯＳ－ＦＥＴ的特性进行了模拟和研究，看到ＰＥＳＤＭＯＳＦＥＴ具有比较好的短沟道特性和亚阈值特性，其输出电流和跨导较大，且对热载流子效应的抑制能力较强，因此具有比较好的性能．给出了ＰＥＳＤＭＯＳＦＥＴ的优化设计方法．当ＭＯＳＦＥＴ尺寸缩小到深亚微米范围时，ＰＥＳＤＭＯＳ－ＦＥＴ将成为一种较为理想的器件结构     

EDFA增益均衡技术

ＥＤＦＡ对不同波长的光产生的增益不同,在ＥＤＦＡ级联的ＷＤＭ 系统中,这种增益不平坦（不同）的特性严重地影响着系统的性能,所以ＥＤＦＡ的增益均衡显得尤为重要。文中介绍了ＷＤＭ 光纤通信中对ＥＤＦＡ增益的不平坦进行均衡的几种方法,并对其进行了比较     

用FIFO设计HDTV编码器

在ＨＤＴＶ（高清晰度电视）编码器中,用ＭＰＥＧＺ对输入视频流进行压缩而输出是压缩的ＨＤＴＶ视频图像。ＦＩＦＯ（先进先出）存储器可用在ＨＤＴＶ编码器通路不同点上,主要是提供频率耦合。ＦＩＦＯ设置为×９和×１８配置,连接成１Ｍ深的存储体。ＦＩＦＯ写和读时钟为２７ＭＨｚ～７４ＭＨｚ。ＦＩＦＯ读和写操作同时执行。ＨＤＴＶ需要有高性能的基础部件,如音频和视频压缩器。为使ＨＤＴＶ广播信号适合ＦＣＣ所标定的频谱,需要对数字视频像素数据进行压缩。与一般数字化ＮＴＳＣ格式电视信号相比;ＨＤＴＶ像素取样率和图像密度…     

FPGA上的DSP

数字信号处理（ＤＳＰ）,如ＦＩＲ、ＩＩＲ、ＦＦＴ、ＩＦＦＴ,主要由ＭＡＣ（乘加）操作构成,而实现ＭＡＣ操作需要消耗大量的ＦＰＧＡ逻辑资源。通过在ＦＰＧＡ硅片上预先构造出大量的可编程的ＥＣＵ（嵌入式计算单元）、ＤＰＲＡＭ（双口随机存储器）,Ｑｕｉｃｋｌｏｇｉｃ公司提供一种可用于高速、并行、复杂ＤＳＰ算法的ＦＰＧＡ。算法和计算系数可装入ＤｐＲＡＭ,用以操作功能强大的ＥＣＵ,以实现单时钟周期计算。本文将根据此芯片的功能,讨论如何高效地实现并行复杂ＤＳＰ算法。背景从事图像处理。通信、海量储存技术的工程师…     

带偏差约束的时钟线网的拓扑构造和优化

提出了一种新的拓扑构造和优化方法,综合考虑了几种拓扑构造方法的优点,总体考虑偏差约束,局部进行线长优化.实验结果表明,它可以有效控制节点之间的偏差,同时保证减小时钟布线树的整体线长.     

时钟延时及偏差最小化的缓冲器插入新算法

本文提出了以最小时钟延时和时钟偏差为目标的缓冲器插入新算法.基于Elmore延时模型,我们得到相邻缓冲器间的延时是缓冲器在时钟树中位置的凸函数.当缓冲器布局使所有缓冲器间延时函数具有相同导数值时,时钟延时达到最小;当所有源到各接收端点路径的延时函数值相等时,时钟偏差达到最小.对一棵给定的时钟树,我们在所有从源点到各接收端点路径上插入相同层数的缓冲器,通过优化缓冲器的位置实现时钟延时最小;通过调整缓冲器尺寸和增加缓冲器层数,实现时钟偏差最小.     

Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration

As IC fabrication technologies get into nanometer era, clock routing gradually dominates chip performance indicated by delay, cost, and power consumption. X-architecture can be applied for routing metal wires in diagonal and rectilinear directions to overcome the above challenges due to wirelength reduction. In this paper, we present a clock routing algorithm, called PMXF, to construct an X-architecture zero-skew clock tree with minimum delay. An X-pattern library is defined for simplifying the merging procedure of the DME approach, an X-Flip technique is proposed for reducing the wirelength between the paired points, and a wire sizing technique is applied for achieving zero skew. In terms of clock delay, wirelength, power consumption, and via count listed in the experimental results on benchmarks, the proposed PMXF algorithm can respectively achieve more reductions compared with other previous X-architecture clock routing algorithms.     

A buffer distribution algorithm for high-performance clock netoptimization

We propose a new approach for optimizing clock trees, especially for high-speed circuits. Our approach provides a useful guideline to a designer, by user-specified parameters, and three of these tradeoffs are provided in this paper. (1) First, to provide a “good” tradeoff between skew and wire length, a new clock tree routing scheme is proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and minimum rectilinear Steiner tree. Our experiments complement the theoretical results. (2) For high-speed clock distribution in the transmission line mode (e.g., multichip modules) where interconnection delay dominates the clock delay, buffer congestion might exist in a layout. Using many buffers in a small wiring area results in substantial interline crosstalks as well as wirability, when the elongation of the imbalanced subtrees is necessary. Placing buffers evenly (locally or globally) over the plane at the minimum impact on wire length increase helps avoid buffer congestion and results in less crosstalk between clock wires. Thus, an effective technique for buffer distribution is proposed. Experimental results verify the effectiveness of the proposed algorithms. (3) Finally, a postprocessing step constraining on phase-delay is also proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and bounded radius minimum spanning tree. The proposed algorithm has an important application in MCM clock net synthesis as well as VLSI clock net synthesis     

Legitimate Skew Clock Routing with Buffer Insertion

In this paper, we propose a new quick and effective legitimate skew clock routing with buffer insertion algorithm. We analyze the optimal buffer position in the clock path, and conclude the sufficient condition and heuristic condition for buffer insertion in clock net. During the routing process, this algorithm integrates buffer insertion and node merging together, and performs them in parallel. Compared with the method of buffer insertion after zero skew clock routing, our method improves the maximal clock delay by at least 48%. Compared with legitimate skew clock routing algorithm with no buffer, this algorithm further decreases the total wire length and gets reductions from 42 to 82% in maximal clock delay. The experimental results show that our algorithm is quick and effective. Xinjie Wei received his B.Sc. degree in Computer Science from the PLA Nanjing Institute of Communications Engineering in 1993, and got M.S. degree in Computer Science from Xidian University in 1998. He is currently pursuing the Ph.D. degree at Tsinghua University. His research interests include computer network security, neural network and design automation for VLSI circuits and systems. And the major research attention is focused on VLSI physical design. Yici Cai received BSc degree in Electronic Engineering from Tsinghua University in 1983 and received in and MS degree in Computer Science & Technology from Tsinghua University in 1986, She has been an associate professor in the Department of Computer Science & Technology, Tsinghua University. Beijing, China. Her research interests include VLSI layout theory and algorithms. Meng Zhao has been an researcher in Semiconductor Industry Association of Beijing. She received her Bachelor of Engineering degree in Electronical Engineering from Tsinghua University, China, in 2000. She received her Master of Science degree in Computer Science from Tsinghua University, China, in 2003. Her research interests include VLSI design and CAD, Electronical material and device, VLSI verification and so on. Xianlong Hong graduated from Tsinghua University, Beijing, China in 1964. Since 1988, he has been a professor in the Department of Computer Science Technology, Tsinghua University. His research interests include VLSI layout algorithms and DA systems. He is the fellow of IEEE and the Senior Member of Chinese Institute of Electronics.     

Useful-Skew Clock Routing with Gate Sizing for Low Power Design

This paper presents a new problem formulation and algorithm of clock routing combined with gate sizing for minimizing total logic and clock power. Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that only positive skew should be minimized while negative skew is useful in that it allows a timing budget larger than the clock period for gate sizing. We construct an useful-skew tree (UST) such that the total clock and logic power (measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes together form the feasible solution space of our problem. Inspired by the Deferred-Merge Embedding (DME) approach, we devise a merging segment perturbation procedure to explore various tree configurations which result in correct clock operation under the required period. Because of the large number of feasible configurations, we adopt a simulated annealing approach to avoid being trapped in a local optimal configuration. This is complemented by a bi-partitioning heuristic to generate an appropriate connection topology to take advantage of useful skews. Experimental results of our method have shown 12% to 20% total power reduction over previous methods of clock routing with zero-skew or a single fixed skew bound and separately sizing logic gates. This is achieved at no sacrifice of clock frequency.     

合理偏差驱动的时钟线网构造及优化

提出了一种新的时钟布线算法 ,它综合了 top- down和 bottom- up两种时钟树拓扑产生方法 ,以最小时钟延时和总线长为目标 ,并把合理偏差应用到时钟树的构造中 .电路测试结果证明 ,与零偏差算法比较 ,该算法有效地减小了时钟树的总体线长 ,并且优化了时钟树的性能     

Design Method Based on Routing Tree for Topology Update in Ad Hoc Network

Ad hoc network is a kind of infrastructureless and self-organized mobile network. The wireless communication range of mobile nodes is limited in ad hoc network. The nodes can’t communicate with each other directly, but resort to the other adjacent nodes to forward their packets and exchange information of nodes. Every node not only serves as the mobile terminal, but also is able to store and forward packets[1]. Therefore, the node can be regarded as a router in ad hoc network. It finds the p…     

NOC基于2D MESH的路由算法的比较

NOC设计的目的就是从体系结构上解决片上通信的瓶颈问题和时钟问题,片上网络的每条传输路径都包含若干路由器,经过每个路由器都要消耗数个时钟周期,当网络拥塞时,包传输会产生更大的延时,因此采用合适的路由算法来达到延时、吞吐率等的平衡是关键。本文使用NIRGAM仿真器对XY和OE两种算法在4×4的MESH拓扑上进行算法研究,结果显示OE算法的吞吐率和包延时的比值是2.5358,比XY路由算法的比值2.1126大,因此OE路由算法更适用于Mesh拓扑。