硅的横向刻蚀技术研究

研究了SF6等离子体横向刻蚀硅的速率和对SiO2的选择性,主要通过改变SF6气体流量和加入O2,提高硅的横向刻蚀速率和对SiO2选择性。实验发现,加入O2能提高SF6等离子对Si的横向刻蚀速率和Si/SiO2的刻蚀速率比。Si的横向刻蚀速率最高可达0．45μm/min,Si/SiO2的刻蚀比可达50：1。最后提出,在一定刻蚀条件下,可增加SiO2掩膜厚度,或用金属铝作掩膜来加大Si的横向刻蚀量。     

GaN/SiO_2刻蚀选择比的研究

在干法刻蚀GaN时使用SiO2作为掩蔽物,为了在较快的GaN刻蚀速率下获得良好的GaN/SiO2刻蚀选择比,使用电感耦合等离子刻蚀机(ICP),运用Cl2和Ar作为刻蚀气体,改变ICP功率、直流自偏压、气体总流量、气体组分等工艺条件,并讨论了这些因素对GaN/SiO2刻蚀选择比以及对GaN刻蚀速率的影响。实验结果获得了GaN在刻蚀速率为165nm/min时的GaN/SiO2选择比为8∶1。设备验收时GaN刻蚀速率为70nm/min,GaN/SiO2选择比为3.5∶1,可以应用于实际生产。     

外加电压对激光电化学刻蚀硅的影响研究

激光电化学刻蚀是将激光加工技术和电化学加工技术有机结合起来而形成的一种复合型刻蚀工艺。为了研究外加电压对激光电化学刻蚀硅的影响,本文采用248nm KrF准分子激光作为光源聚焦照射浸在KOH溶液中的阳极半导体n—Si上,实现激光诱导电化学刻蚀。在实验的基础上,详细分析外加电压对刻蚀工艺的影响,并对其产生的原因进行了分析。试验结果表明其影响主要有两个方面：（1）正的外加电压保证了SiO2钝化膜生成,从而实现了选择性刻蚀;（2）外加电压的增大,刻蚀速率会相应减小。因而外加电压也是调节刻蚀速率的一个重要的手段。     

硅各向异性浅槽腐蚀实验研究

通过实验分析,对比了异丙醇(IPA)和超声波对Si(100)面在KOH溶液和四甲基氢氧化氨(TMAH)溶液中的浅槽腐蚀速率及其表面形态的影响。实验结果表明,IPA能降低TMAH溶液的腐蚀速率,但IPA在KOH溶液中腐蚀速率降低不明显;IPA加入到较高浓度的KOH溶液中,会在Si表面产生较大小丘,恶化了Si腐蚀表面的质量,但在TMAH溶液中加入一定量的IPA会改善腐蚀表面的质量;超声波能加快腐蚀速率并能改善Si腐蚀表面质量,但对于加入IPA的较高浓度KOH溶液,超声波未能消除Si腐蚀表面的小丘,另外,超声波还能减弱腐蚀过程中微尺寸沟槽的尺寸效应;在腐蚀条件和配比一定情况下,TMAH溶液的腐蚀质量比KOH溶液好。     

一种控制硅深刻蚀损伤方法的研究

提出了提高硅深反应离子刻蚀的新方法.该方法在硅的侧壁PECVD淀积SiO2,硅的底部采用热氧化的方法形成SiO2.由于在刻蚀中硅与SiO2的刻蚀选择比为120:1～125:1,因此SiO2层可以抑制在硅-玻璃结构的刻蚀中出现的lag和footing效应,扫描电镜结果也证明,采用改进工艺后的硅结构在经过长时间的过刻蚀后仍然保持了完整性.硅陀螺测试结果也证明了改进工艺的正确性.     

硅基微结构制作及其在微分析芯片上的应用

基于一种新的湿法刻蚀条件和新型的凸角补偿结构,以KOH溶液为腐蚀液,对单晶(100)Si材料进行了湿法刻蚀,获得了表面平整和凸角完整的刻蚀结果,制作了用于微模塑工艺的硅基阳模,并成功地用于聚甲基乙烯基硅氧烷微分析芯片的制作上.     

IGZO-TFT钝化层三元复合结构过孔刻蚀

IGZO-TFT钝化层设计三元复合过孔结构,出现了20%过孔相关不良。本文以CF4/O2为反应气体,采用控制变量法,从功率、气体成分和比例、压力等方面对氧化物TFT钝化层的电感耦合等离子体刻蚀机理进行研究。当钝化层为SiO2或SiNx单组分时,氧气可以促进刻蚀反应;随着CF4/O2比例增加,刻蚀速率先增大后趋于稳定,并且当CF4/O2=15/8时,刻蚀速率和均一性达到最优;与源功率相比,提高偏压功率在提升刻蚀速率中起主导作用,同时均一性控制在15%以内;当压力在4Pa以内时,刻蚀速率随着压力的降低而增加。据此分析,对复合结构SiNx/SiO2、SiO2/SiNx、SiNx/SiO2/SiNx的刻蚀过程进行优化,得到了形貌规整、无残留物的过孔,过孔相关不良得到100%改善。     

PECVD技术在微结构表面沉积薄膜的复形性北大核心CSCD

采用光刻技术、刻蚀技术和等离子体增强化学气相沉积(PECVD)技术,在线阵掩模微结构表面沉积了SiO2和Si3N4薄膜,研究了线阵掩模的宽度和厚度,以及薄膜的厚度和沉积速率对SiO2和Si3N4薄膜复形性的影响,制备得到了具有良好微结构形貌的微结构滤光片阵列。结果表明,薄膜沉积速率越大,薄膜的复形性越好;掩模厚度和薄膜沉积厚度的增加会导致薄膜的复形性变差;SiO2薄膜的复形性优于Si3N4薄膜的。     

Ar/CHF_3反应离子束刻蚀SiO_2的研究

介绍了Ar/CHF3反应离子束刻蚀和离子束入射角对图形侧壁陡直度及刻蚀选择比的影响。使用紫外曝光技术在SiO2基片上获得光刻胶掩模图形,采用Ar CHF3来刻蚀石英基片,调节二者的流量配比,混合后通入离子源。在Ar和CHF3的流量比为1∶2,总压强为2×10-2Pa,离子束流能量为450 eV,束流为80 mA,加速电压220 V~240 V,离子束入射角15°并旋转样品台的情况下,刻蚀20 min后,得到光栅剖面倾角陡直度为80°~90°。同时发现,添加CHF3后,提高了SiO2的刻蚀速率和刻蚀SiO2与光刻胶的选择比,最高可达7∶1。     

一种控制硅深刻蚀损伤方法的研究

提出了提高硅深反应离子刻蚀的新方法。该方法在硅的侧壁PECVD淀积SiO2,硅的底部采用热氧化的方法形成SiO2。由于在刻蚀中硅与SiO2的刻蚀选择比为120∶1~125∶1,因此SiO2层可以抑制在硅-玻璃结构的刻蚀中出现的lag和footing效应,扫描电镜结果也证明,采用改进工艺后的硅结构在经过长时间的过刻蚀后仍然保持了完整性。硅陀螺测试结果也证明了改进工艺的正确性。     

碳氟等离子体中CF2对SiO2，Si3N4和Si刻蚀的作用

The CF2 density and etch rate of SiO2, Si3N4 and Si are investigated as a function of gas pressure and O2 flow rate in fluorocarbon plasma. As the pressure increases, the self-bias voltage decreases whereas the SiO2 etch rate increases. Previous study has shown that SiO2 etch rate is proportional to the self-bias voltage. This result indicates that other etching parameters contribute to the SiO2 etching. Generally, the CF2 radical is considered as a precursor for fluorocarbon layer formation. At a given power, defluorination of fluorocarbon under high-energy ion bombardment is a main source of fluorine for SiO2 etching. When more CF2 radical in plasma, SiO2 etch rate is increased because more fluorine can be provided. In this case, CF2 is considered as a reactant for SiO2 etching. The etch rate of Si3N4 and Si is mainly determined by the polymer thickness formed on its surface which is dominated by the CF2 density in plasma. Etching results obtained by varying O2 flow rate also support the proposition.     

Role of CF2 in the etching of SiO2, Si3N4 and Si in fluorocarbon plasma

The CF2 density and etch rate of SiO2, Si3N4 and Si are investigated as a function of gas pressure and 02 flow rate in fluorocarbon plasma. As the pressure increases, the self-bias voltage decreases whereas the SiO2 etch rate increases. Previous study has shown that SiO2 etch rate is proportional to the self-bias voltage. This result indicates that other etching parameters contribute to the SiO2 etching. Generally, the CF2 radical is considered as a precursor for fluorocarbon layer formation. At a given power, defluorination of fluorocarbon under high-energy ion bombardment is a main source of fluorine for SiO2 etching. When more CF2 radical in plasma, SiO2 etch rate is increased because more fluorine can be provided. In this case, CF2 is considered as a reactant for SiO2 etching. The etch rate of Si3N4 and Si is mainly determined by the polymer thickness formed on its surface which is dominated by the CF2 density in plasma. Etching results obtained by varying O2 flow rate also support the proposition.     

含添加剂的各向异性腐蚀液中实现小掩膜下高硅尖的腐蚀

各向异性KOH溶液腐蚀硅尖具有简单、易于实现、成本低廉、(100)晶面腐蚀速率均匀等优点.然而在40%KOH溶液中削角速率和(100)晶面的腐蚀速率之比约为1.6~1.9,并且该比值随着KOH浓度的减小而增大.如此高的削角速率会给AFM探针的制作带来技术上的困难.而对腐蚀场发射器件和隧道式传感器的硅尖阵列来说,高的削角速率会减少单位面积内的硅尖数量.本文通过在氢氧化钾(KOH)或者四甲基氢氧化胺(TMAH)溶液中添加适当的添加剂(如异丙醇(IPA)、1,5戊二醇或碘)降低了削角速率,在较小直径的掩膜下腐蚀出高硅尖.实验结果还表明:在TMAH基腐蚀液中每个硅尖的八个快腐蚀面的削角速率几乎相等,硅尖直径偏差较KOH溶液中腐蚀的硅尖直径偏差更小,因此成品率得到了提高.     

10%TMAH硅湿法腐蚀技术的研究

研究了浓度为10%的四甲基氢氧化铵(TMAH)溶液,在不同量的Si粉掺杂下,对铝膜及硅衬底的腐蚀及其pH值的变化。测试了在满足铝膜极低的腐蚀速率(<1nm/min)时,不同温度下该腐蚀液对硅(100)、(111)和(110)晶面及SiO2介质膜的腐蚀速率。还介绍了添加剂—过硫酸铵(APODS)和吡嗪的加入对腐蚀表面形貌及腐蚀速率的影响。研究结果表明,存在着一个临界的硅粉添加量,超过此量后铝膜的腐蚀速率急剧降低。90℃时,在10%TMAH溶液中加入1 5mol/L硅粉、3 0g/LAPODS和2g/L吡嗪可以实现铝膜不被腐蚀,同时硅(100)面约有1μm/min的腐蚀速率,腐蚀表面平整。腐蚀后的铝膜表面同硅铝丝键合良好,实现了腐蚀工艺同CMOS工艺的完全兼容。     

Back-etch method for plan view transmission electron microscopy sample preparation of optically opaque films

Back-etch methods have been widely used to prepare plan view transmission electron microscopy (TEM) samples of thin films on membranes by removal of the Si substrate below the membrane by backside etching. The conventional means to determine when to stop the etch process is to observe the color of the light transmitted through the sample, which is sensitive to the remaining Si thickness. However, most metallic films thicker than 75 nm are opaque, and there is no detectable color change prior to film perforation. In this paper, a back-etch method based on the observation of an abrupt change of optical reflection contrast is introduced as a means to determine the etch endpoint to prepare TEM samples for these films. As the acid etchant removes the Si substrate material a rough interface is generated. This interface becomes a relatively smooth and featureless region when the etchant reaches the membrane (film/SiO2). This featureless region is caused by the mirror reflection of the film plane (film/SiO2 interface) through the optically transparent SiO2 layer. The lower etch rate of SiO2 (compared with Si) gives the operator enough time to stop the etching without perforating the film. A clear view of the morphology and control of Si roughness during etching are critical to this method, which are discussed in detail. The procedures of mounting wax removal and sample rinsing are also described in detail, as during these steps damage to the membrane may easily occur without appropriate consideration. As examples, the preparation of 100-nm-thick Fe-based amorphous alloy thin film and 160-nm-thick Cu-thin film samples for TEM imaging is described.     

抛光工艺对硅基Pb_(1-x)Ge_xTe薄膜性能的影响

研究了不同的抛光方法(机械抛光、化学腐蚀及化学机械抛光)对硅基板上沉积的Pb_(1-x)Ge_xTe薄膜性能的影响.研究表明,经化学机械抛光(SiO_2胶体或Cr~+)的硅基板上所沉积的Pb_(1-x)Ge_xTe薄膜具有致密的结构及平直的界面,其沉积速率也比在化学腐蚀抛光表面的沉积速率大7%或18%(分别对应<111>和<100>晶向);薄膜具有明显高于化学腐蚀抛光基板沉积薄膜的折射率,且折射率随温度的降低而增加,而低温下折射率随波长的增加而增加;化学腐蚀抛光基板沉积薄膜的折射率的增加量明显大于化学机械抛光基板沉积薄膜的增加量;薄膜层经机械抛光后,其膜层结构、组分及其深度分布均未改变,但透射率增加,消光系数有所改善,折射率有所降低.     

用于高灵敏度红外探测器的超薄硅膜的研制

超薄、平整的硅膜对于制作高灵敏度红外探测器是非常重要的。这种超薄硅膜的各向异性腐蚀技术，包括有机溶液EPW和无机溶液KoH及KoH IPA(异丙醇)。从腐蚀速率、腐蚀表面质量、腐蚀停特性、腐蚀边缘形貌及腐蚀工艺的角度分析比较了两种腐蚀系统，分别制作出了约1μm厚的平整超薄硅膜，并研究了不同掩膜材料在腐蚀液中的抗蚀性，为高灵敏度红外探测器的制作奠定了工艺基础。     

1-/spl mu/m MOS Process Using Anisotropic Dry Etching

Anisotropic and selective etching of silicon has been obtained using a planar-reactive sputter-etching system and CC1/sub 3/F gas. The Si to SiO/sub 2/ etch-rate ratio was 5:1. This etch process in CC1/sub 3/F was interpreted as mainly involving physical reaction as opposed to etching in SF/sub 6/. The influence of reactive sputter etching on junction leakage and threshold voltage shift, in comparison with a conventional wet-etch process, could not be observed in the electrical characteristics of polysilicon gate MOS devices. An all dry-etched MOS process, consisting of an anisotropic etching for Si/sub 3/N/sub 4/, polysilicon, SiO/sub 2/, and aluminum, was applied to, the fabrication of a 1-kbit static RAM with 1-/spl mu/m minimum geometry. It was confirmed that this anisotropic etching technology was useful for very fine-geometry patterning and could be applied to a 1-/spl mu/m MOSLSI manufacturing process.     

三维掩膜硅各向异性腐蚀工艺释放微悬空结构

提出了一种新颖的基于三维掩膜的硅各向异性腐蚀工艺,即利用深反应离子刻蚀、湿法腐蚀等常规体硅刻蚀工艺和氧化、化学气相沉积(CVD)等薄膜工艺制作出具有三维结构的氧化硅(SiO2)或氮化硅(Si3N4)薄膜,以该三维薄膜作为掩膜进行各向异性腐蚀,该工艺可以应用于MEMS微悬空结构的制作。利用该工艺成功地在单片n-Si(100)衬底上完成了一种十字梁结构的释放,并对腐蚀的过程和工艺参数进行了研究。