A two-temperature technique for PECVD deposition of silicon dioxide

A new technique has been developed and analyzed for plasma-enhanced chemical vapor deposition (PECVD) silicon dioxide films, First, a thin cap layer is deposited at a low temperature and the film is subjected to an in-situ hydrogen plasma treatment. Then, the temperature is raised to the final value and the deposition continued to the desired thickness. It is shown that interrupting the deposition for in-situ sample treatment can be used to lower the interface trap density. Several variations are examined, and it is seen that a thin cap layer is best, along with a higher initial temperature. A variety of hydrogen treatments are shown to effectively reduce the trap density from that of a standard one-temperature deposition. The midgap trap densities obtained are among the best achieved with a direct PECVD system     

A current conduction mechanism in laser recrystallized silicon metal-oxide-semiconductor transistors

Laser recrystallization is a method used for improving the quality of deposited silicon films by enlarging the grain sizes and reducing the density of defect states in the films. N-channel MOS transistors were fabricated on silicon films that had been recrystallized by an argon ion laser at different power levels. These transistors showed electrical characteristics similar, but somewhat inferior to those devices fabricated on single crystal silicon substrates. These differences are attributed to the presence of trapping states at the grain boundaries of the crystallites in the recrystallized silicon. A coulombic scattering model is presented to explain these differences. In the case of films annealed at low laser power, an additional factor of nonuniform trap state distribution is invoked to explain device characteristics. This model provides an adequate explanation for the observed transport properties of transistors fabricated from recrystallized silicon films.     

Temperature and electric field characteristics of time-dependentdielectric breakdown for silicon dioxide and reoxidized-nitrided oxides

TDDB characteristics of 150 Å reoxidized nitrided oxide (ONO) gate dielectrics were examined at temperatures from 77 K to 400 K. These ONO films were processed with different conditions of rapid thermal nitridation (RTN) and rapid thermal re-oxidation (RTO). Optimized ONO films show better Q_bd performance while maintaining a similar temperature and electric field dependence compared to SiO₂. The low temperature activation energy for ONO and SiO₂ is found to be strongly temperature dependent, and the charge to breakdown, Q_bd, is closely related to the electron trap generation/trapping rate rather than the amount of hole trapping for high field stress. To further verify the effect of hole trapping on TDDB, X-ray irradiation was applied to wafers at different process steps. The results clearly show that the amount of hole trapping does not correlate with the charge to breakdown     

A new computer-aided simulation model for polycrystalline silicon film resistors

A general transport theory for the I–V characteristics of a polycrystalline film resistor has been derived by including the effects of carrier degeneracy, majority-carrier thermionic-diffusion across the space charge regions produced by carrier trapping in the grain boundaries, and quantum mechanical tunneling through the grain boundaries. Based on the derived transport theory, a new conduction model for the electrical resistivity of polycrystalline film resitors has been developed by incorporating the effects of carrier trapping and dopant segregation in the grain boundaries. Moreover, an empirical formula for the coefficient of the dopant-segregation effects has been proposed, which enables us to predict the dependence of the electrical resistivity of phosphorus-and arsenic-doped polycrystalline silicon films on thermal annealing temperature.Phosphorus-doped polycrystalline silicon resistors have been fabricated by using ion-implantation with doses ranged from 1.6 × 10¹¹ to 5 × 10¹⁵/cm². The dependence of the electrical resistivity on doping concentration and temperature have been measured and shown to be in good agreement with the results of computer simulations. In addition, computer simulations for boron-and arsenic-doped polycrystalline silicon resistors have also been performed and shown to be consistent with the experimental results published by previous authors.     

The Impact of Nitrogen Engineering in Silicon Oxynitride Gate Dielectric on Negative-Bias Temperature Instability of p-MOSFETs: A Study by Ultrafast On-The-Fly $I_{rm DLIN}$ Technique

Degradation of p-MOSFET parameters during negative-bias temperature instability (NBTI) stress is studied for different nitridation conditions of the silicon oxynitride (SiON) gate dielectric, using a recently developed ultrafast on-the-fly I_DLIN technique having 1-mus resolution. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is governed by nitrogen (N) density at the Si/SiON interface. The relative contribution of interface trap generation and hole trapping to overall degradation as varying interfacial N density is qualitatively discussed. Plasma oxynitride films having low interfacial N density show interface trap dominated degradation, whereas relative hole trapping contribution increases for thermal oxynitride films having high N density at the Si/SiON interface.     

Electrical properties of silicon dioxide films fabricated at 700°C. II: Low pressure hydride deposition

We have investigated the effects of different annealing treatments on silicon dioxide films produced from the reaction of dichlorosilane and nitrous oxide at 700° C. The electrical quality of these LPCVD films was evaluated by measuring oxide charge and interface trap densities on metal oxide semiconductor (MOS) capacitors. These densities were measured before and after avalanche injection of electron currents into the oxide films. The results of these studies were as follows. (1) The LPCVD oxide films required a post deposition anneal at 1000° C to produce as-grown charge densities similar to those of a standarddry thermal oxide grown and annealed at 1000° C. (2) Post-injection charge densities of LPCVD films given a post deposition anneal at 1000°C were an order of magnitude greater than those of the standard dry thermal oxide. (3) Different annealing treatments produced a series of dominant electron trapping centers in the oxide bulk₁₇ with capture cross sections ranging from 10⁻¹⁴ cm² to 10⁻¹⁷ cm². (4) The electron traps in the LPCVD oxides films were similar to those previously observed in standardwet thermal oxides grown and annealed above 1000° C.     

Degradation of silicon dioxide during selective silicon epitaxy in a dichlorosilane environment

The electrical degradation of dry thermal SiO₂ upon exposure to selective silicon epitaxy using dichlorosilane has been investigated. Capacitors were fabricated with thermal gate oxides (120 to 440A thick) grown on p-type silicon (100) substrates. Prior to the gate electrode formation, the oxides were exposed to hydrogen and dichlorosilane + hydrogen anneals. Leakage current and electric field breakdowns were measured to evaluate the effects of these anneals on the SiO₂ degradation. The SiO₂ degradation occurring because of dichlorosilane exposure was studied as a function of the temperature and time. While dichlorosilane exposure at temperatures above 850°C was found to cause high leakage current and breakdowns at low electric fields for silicon dioxide films thinner than 440Å, little effect was observed as a result of hydrogen and chlorine exposures. The degradation mechanism was attributed to pinhole etching via volatile SiO formation along defects present in the as-grown SiO₂.     

Rapid thermal oxidation of porous silicon for surface passivation

Rapid thermal oxidation with dry oxygen has been carried out on porous silicon (PS) films formed by electrochemical etching. The purpose of the paper was to investigate the surface passivation capability of the oxidized PS layers and to understand the oxidation mechanism. Rutherford back scattering (RBS) and X-ray photoemission spectroscopy (XPS) analyses confirmed the formation of a stoichiometric quasi-silicon dioxide. Besides, elastic recoil diffusion analysis (ERDA) demonstrated that a high concentration of hydrogen is still present in the PS film even after oxidation. RTO resulted in a good surface passivation effect at high temperature (>1000°C) as seen by internal quantum efficiency analysis. However, lifetime in bulk silicon is affected by the RTO process.     

Effect of deposition methods on dielectric breakdown strength of PECVD low-k carbon doped silicon dioxide dielectric thin films

The effect of deposition methods on dielectric breakdown strength of PECVD low-k dielectric carbon doped silicon dioxide films is investigated. I-V measurements were performed using metal-insulator semiconductor structures for carbon doped silicon dioxide thin films with various thicknesses by single deposition station and six sequential deposition systems. I-t measurements are also performed for films with the thickness of 32 nm prepared using both deposition methods. Comparison studies have been carried out for the thickness dependence, temperature dependence, conduction mechanism and time dependence of dielectric breakdown for carbon doped silicon dioxide with single layer and six sub-layers. Results demonstrated that both films follow the newly obtained relationship between dielectric strength E_B and thickness d, i.e. E_B∝(d−d_c)⁻ⁿ, but with a lower exponential factor n and a larger thickness limit d_c for films with six sub-layers. It is also demonstrated that films with six sub-layers have a higher dielectric strength in all the thickness and temperature ranges, a thickness independent thermal behavior and a longer lifetime under constant voltage stressing. This indicates that by tuning the deposition methods smaller thickness with desired dielectric properties can be achieved.     

TEOS-based PECVD of silicon dioxide for VLSI applications

Silicon dioxide films deposited from tetraethylorthosilicate (TEOS) using plasma-enhanced chemical vapour deposition (PECVD) are reviewed. The effect of the presence of oxygen on the film deposition rate and mechanism and the physical properties of the films, particularly the step coverage properties (conformality), are discussed in detail. Structural characterisation of the films has been carried out via etch rate measurements, infrared transmission spectroscopy, X-ray photoelectron spectroscopy (XPS) and Auger and secondary ion mass spectroscopy (SIMS) analysis. Electrical properties, i.e. resistivity, breakdown strength, fixed oxide charge density, interface state density and trapping behaviour, have been evaluated using metal-oxide-semiconductor (MOS) structures fabricated using the deposited oxides. Films deposited by microwave plasma-enhanced decomposition of TEOS in the presence of oxygen have been found to be comparable with standard silane-based low-pressure chemical vapour deposition (LPCVD) and PECVD oxides. It has been shown that films deposited on thin native oxides grown by either in situ plasma oxidation or low-temperature thermal oxidation exhibit excellent electrical properties.     

Two new efficient crystalline silicon light‐trapping textures

As a solar cell material, silicon has the disadvantage of an indirect bandgap, requiring both a photon and a phonon to be involved in near‐bandgap absorption processes. This disadvantage can be largely offset by schemes designed to trap incoming light within the body of the cell. Improved light‐trapping schemes have been a significant contributor to the increase in silicon solar cell performance from 21% efficiency to close to 25% over the last decade. Two new light‐trapping schemes are described, both with superior properties to those previously reported. Copyright © 1999 John Wiley & Sons, Ltd.     

a-SiH 热处理过程中纳米硅粒尺寸的控制(英文)

报道了控制热处理过程中含氢非晶硅中纳米硅颗粒大小的一种新方法。用喇曼散射、X射线衍射和计算机模拟,发现在非晶硅中所形成的纳米硅颗粒的大小,随着热退火过程中升温速率的变化而变化。在退火过程中,若非晶硅薄膜升温速率较高(～100℃/s),则所形成纳米硅粒的大小在1.6～15nm;若非晶硅薄膜升温速率较低(～1℃/s),则纳米硅粒大小在23～46nm。根据晶体生长理论,讨论了升温速率的高低与所形成的纳米硅颗粒大小的关系。     

Some observations on charge buildup and release in silicon dioxide irradiated with low energy electrons

The positive charge buildup produced in silicon dioxide by low energy electrons (0 to 30 keV) has been investigated as a function of beam energy and oxide thickness. The induced charge, as evidenced by displacement of capacitance versus voltage plots, was found to be a function of the beam energy dissipated within the oxide in the vicinity of the oxide-silicon interface. The charge induced at a particular fluence level in an oxide of given thickness increases with energy up to some level Emaxbeyond which the charge buildup rate falls off as the energy is increased further. Continued falloff in the buildup rate was observed in several samples irradiated at energies of 200 keV and 1 MeV. Emaxhas been found to correspond to the beam energy which, according to predicted range-energy data, produces maximum energy dissipation per unit path length in the oxide near the silicon interface. Constant temperature annealing of irradiated MOS samples has indicated that the annealed charge is linearly dependent on the logarithm of elapsed time over a finite time interval. This is particularly evident at room temperature where a linear dependence on In (t) has been observed out to 10⁵seconds. Such a time dependence of released charge can result either from thermal activation of trapped carriers from a uniform trap distribution or from thermal emission of recombination electrons over a Schottky barrier from the silicon into the oxide; however, both of these models predict the released charge to be a linear function of absolute temperature. A much stronger temperature dependence has been observed during these experiments.     

Weak light effect in multicrystalline silicon solar cells

Minority carrier trapping centers frequently exist in solar grade multicrystalline silicon, such trapping centers cause a drastic increase in photoconductance at carrier injection levels equal to and below the trap density, this phenomenon leads to higher open circuit voltage for multicrystalline silicon solar cells at illumination levels below about 0.2 suns compared to high performance crystalline silicon solar cells. In this paper, the open circuit voltage of multicrystalline silicon solar cells are investigated at low illumination levels, the experiments prove that some multicrystalline silicon solar cells which have higher trap density have higher open circuit voltage at weak illumination levels, and have lower efficiency, so a new method is presented to analyze quality of multicrystalline silicon by measuring open circuit voltage at weak illumination levels in-line, this makes cells manufacturers gain insight into the quality of multicrystalline silicon wafer from different multicrystalline silicon manufacturers easily with the same cell process before screenprinting and firing.     

Monolithic 3-D silicon photonics

A monolithic CMOS compatible process has been developed to realize vertically integrated devices in silicon. The method involves the implantation of an oxygen into a patterned silicon substrate to form buried guiding structures. These buried devices are separated from a surface silicon layer by an intervening layer of silicon dioxide formed through the implantation process. Photolithography and etching is used to define devices on the surface silicon layer. The method has been utilized to realize the vertically coupled microdisk resonators and a variety of microresonator-based integrated optical elements. A new method for extraction of the unloaded Q of a cavity from its measured spectrum is also described.     

Impact of the trapping of anode hot holes on silicon dioxide breakdown

Hot holes are injected from the anode and trapped in thin silicon dioxide using constant voltage stress at large gate voltage. By comparing oxides having trapped holes with oxides in which the holes were detrapped, it is shown that the presence of trapped holes does not affect the breakdown of the oxide. Furthermore, as the temperature during stress is increased, less hole trapping is observed whereas the charge-to-breakdown of the oxide is decreased. The results show that although the trapping of hot holes injected using anode hole injection (AHI) may be partly responsible for defect generation in silicon dioxide, breakdown cannot be limited by the number of holes trapped in the oxide.     

Annealing-temperature dependence of the thermal conductivity ofLPCVD silicon-dioxide layers

The authors point out that the reliability and performance of electronic circuits are influenced by heat conduction in low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide layers. Here, the effective thermal conductivity k_eff for conduction normal to films of LPCVD silicon dioxide layers as a function of annealing temperature, as well as for films of thermal and SIMOX oxides, is measured. The LPCVD oxide thermal conductivity increases by 23% due to annealing at 1150°C. The conductivities k_eff of LPCVD layers of thicknesses between 0.03 and 0.7 μm are higher than those reported previously for CVD layers, and vary between 50% and 90% of the conductivities of bulk fused silicon dioxide. The values of SIMOX and thermal oxide layers are within the experimental error of the values for bulk fused silicon dioxide     

Characteristics of thermally nitrided silicon dioxide film and plasma enhancement

After reviewing characteristics of thermally nitrided silicon dioxide films, plasma enhanced nitridation is described. The plasma technique makes possible reduction of the nitridation temperature by activating reaction species. Silicon dioxide films of about 10 nm thickness were nitrided in ammonia gas plasma, for example, at 1000‡C and at a pressure of 40 Pa. From the results of the AES depth profiles and the N_ss distribution, good dielectric and interfacial properties have been obtained via plasma nitridation. The plasma nitroxide films are useful for gate insulators of small MOSFETs in future VLSI.     

A silicon quantum wire transistor with one-dimensional subband effects

A silicon quantum wire transistor, in which electrons are transported through a very narrow wire, has been fabricated using silicon-on-insulator technology, electron beam lithography, anisotropic dry etching, and thermal oxidation. We have obtained the quantum wire with a width of 65 nm, which is fully embedded in silicon dioxide. This narrow dimension of the wire and large potential barrier between silicon and silicon dioxide make the electrons moving through the wire experience one-dimensional confinement. The step-like structure in the conductance versus gate voltage curve, which is a typical evidence of one-dimensional conductance, has been observed at temperatures below 4.2 K. A period of step appearance and a step size have been analyzed to compare experimental characteristics with theoretical calculation.     

Dielectric integrity of thin thermal oxides on silicon

The role of silicon dioxide layers in microelectronics and the importance of their integrity are undisputable. From passivating coatings and masking layers for diffusion to ultra-thin tunneling films — all the silicon technology could not exist without silicon dioxide. This review deals with some aspects of the integrity of thin silicon dioxide films for VLSI applications. The problems of dielectric strength and wear-out are considered from the point of view of their mechanisms, models, oxide processing dependence, testing, and measuring. A brief presentation of statistical approaches commonly applied to reliability topics is also included.