基于循环平稳特性的欠采样宽带数字预失真研究

为了解决行波管(TWT)宽带数字预失真(DPD)中反馈回路ADC采样率过高的问题，该文利用信号的循环平稳特性证实可通过欠采样下的输出信号估计功放的非线性模型参数，然后由功放非线性模型参数和输入信号可恢复出与高采样率下效果相似的功放输出信号，最后通过传统的间接学习结构对功放进行数字预失真以实现行波管的线性化。为了验证该方法，利用20 MHz LTE信号驱动一只55 W的X波段行波管放大器(TWTA)。数字预失真反馈回路的ADC采样率从61.44 Msps降低至6.144 Msps和3.072 Msps，但线性化效果变化不大，表明欠采样方法是有效的。     

基于Landweber迭代算法的欠采样恢复数字预失真技术

传统宽带数字预失真(DPD)为了更好地矫正功率放大器(PA)非线性特性,通常要求反馈通道带宽达到发送信号带宽的5倍,相应地要求更高采样率的模数转换器(ADC),这将导致数字预失真系统面临着硬件成本和能耗问题。针对这一问题,该文提出一种基于Landweber迭代算法的欠采样恢复(USR)数字预失真(Landweber-USR DPD)技术。这种以内外循环的方式进行处理,可将反馈通道带宽从理论要求的5倍降低至2倍,以良好的质量从欠采样的功放输出信号中恢复全频带的输出信号,使还原出的数据更接近真实的功放输出信号,以实现更好的预失真效果。实验选用基于单管氮化镓(GaN)器件的宽带F类功率放大器,在1.8 GHz工作频点下用5 MHz的长期演进(LTE)信号激励,反馈ADC速率分别设置为全采样速率(40 Msps)和欠采样速率(10 Msps)。实验结果充分证明了Landweber迭代算法恢复功放数据的可靠性以及Landweber-USR DPD技术的有效性,为宽带通信系统中数字预失真技术的工程实现提供了有效降低ADC采样率的思路和方法。     

一种基于维度加权盲K近邻算法的数字预失真技术

传统的数字预失真(DPD)模型通常在所有的输入信号功率上采用单一多项式模型和单一记忆深度对功率放大器(PA)进行线性化矫正。然而,功率放大器在不同的功率水平下会呈现出不同的非线性特性,并产生不同的记忆效应。针对这一问题,该文提出一种基于维度加权盲K近邻(KNN)算法的数字预失真模型,所提模型根据功放当前输入信号以及记忆输入信号的幅度进行维度加权的KNN分类,组成维度加权盲KNN记忆多项式(WKMP)模型,并为每一类输入信号序列建立子模型。所提方法用Doherty功率放大器进行实验验证,使用带宽为30 MHz、频点为2.2 GHz的3载波长期演进(LTE)信号作为输入,反馈端使用122.88 MHz的采样率进行采样。实验结果表明,所提维度加权盲KNN分类方法与记忆多项式(MP)模型结合时,功放正向建模效果和数字预失真效果均超过了广义记忆多项式(GMP)模型,并远超记忆多项式模型的效果,实验结果验证了所提模型的优良性能。     

基于数/模混合预失真技术的功放线性化北大核心CSCD

随着移动通信信号带宽的增加,传统功率放大器数字预失真线性化技术越来越受到采样率的限制。为了使线性化效果更好,文中提出了一种数字预失真和模拟预失真相结合的混合预失真器,利用模拟预失真宽带宽的特点和数字预失真线性化能力强的优势,把模拟预失真和数字预失真融合在一起,共同补偿功放的非线性。由于受实验设备采样率的限制,文中采用了带宽为60 MHz的5 G NR信号对一个中心频率为3.5 GHz的射频功放进行实验验证。实验结果表明:提出的混合预失真器不仅优于单独的数字预失真器和模拟预失真器的非线性矫正性能,而且还能改善数字预失真因采样率限制无法改善的带外互调失真。     

Complexity-reduced Volterra series model for power amplifier digital predistortion

This paper expounds a complexity-reduced Volterra series model for radio frequency power amplifier (PA) behavioral modeling and digital predistortion (DPD). An analysis was conducted, which took into account the memory effect mechanisms of the PA. This led to a closed-form expression that relates the memoryless behavior of the PA to the finite impulse response feedback filter, which approximates the memory effects’ behavior. The analysis resulted in a complexity-reduced Volterra series model which allows for a substantial reduction in the requirements for digital signal processors and the time needed to construct and implement the DPD in a real-time environment. The proposed model was validated as a behavioral model and a DPD using two different PA architectures, employing two different transistor technologies, driven by both 20 MHz 1001 wideband code division multiple access and long term evolution signals. The results obtained demonstrate the excellent modeling and linearization capability of the complexity-reduced Volterra series model.     

A Method to Reduce Sampling Rate of the ADC in Feedback Channel for Wideband Digital Predistortion

This paper presents a new digital predistortion (DPD) solution for wideband signals with low feedback sampling rate. To reduce the minimum sampling rate of the analog-to-digital converter (ADC) for wideband digital predistortion, the proposed method uses a bandpass filter to form a narrowband signal before the ADC. Then, a deconvolution operation is performed to recover the original wideband signal from the ADC samples. The proposed method is evaluated with an international mobile telecommunication-advanced signal with 100 MHz bandwidth. The simulation results show that the recovered signal of the proposed method closely approximates to the original signal in the passband of the filter, and the mean square error of the deconvolution decreases as the signal-to-noise ratio increases. The proposed algorithm can reduce the sampling rate of the ADC from 1105.92 million samples per second (MSPS) to 368.64 MSPS, and improve the adjacent channel power ratio more than 20 dB, which is merely 5.6 dB less than the conventional DPD with 1105.92 MSPS sampling rate.     

调整峰值功放电流响应提高效率的LTE-A Doherty 功放*

介绍了一种利用宽带输入匹配网络调整峰值功放输出电流,改善Doherty 功放负载调制效果和带内 效率的设计方法。理论分析表明,Doherty功放中峰值功放C 类偏置情况下带来的带内不一致开启特性会影响输出 电流和负载调制效果。通过引入宽带输入匹配网络,能有效改善它的开启不一致性。为验证分析结果设计了具有 宽带(采用简易实频技术)和窄带两种不同输入匹配网络,用于2.15GHz 频段LTE-A 的Doherty功放。仿真和测试 结果表明,功放的输出功率超过49dBm,在7dB 回退功率处,宽带输入匹配Doherty 功放的带内效率达到42% 以上, 效率波动由10%降低到2%。使用100MHz 宽带LTE-A 信号经过线性化改善后,在40dBm 输出时,宽带输入匹配网 络的Doherty功放上下边带ACLR(adjacent channel leakage ratio)指标为-45.1/-44.9dBc,效率为40.5%,均优于窄带输入匹配网络的Doherty功放。     

非均匀采样率并发双频数字预失真技术

5G通信的高速发展对发射机支持多模式多频带并发有了新的需求.考虑非均匀采样率并发双频场景下发射机的线性化方案,针对低采样率频段失真频谱超过采样带宽,从而恶化建模精度这一问题,提出一种混叠消除的并发双频数字预失真(DPD)方案.该方案通过在高采样率下构造模型基函数,然后通过低通滤波器来滤除超出采样带宽的频谱分量,再降采样...     

Adaptive Digital Feedback Predistortion Technique for Linearizing Power Amplifiers

We have developed a new adaptive digital predistortion (DPD) linearization technique based on analog feedback predistortion (FBPD). The lookup-table-based feedback input can remove the bandwidth limitation of the feedback circuit related to the loop delay, and suppress feedback oscillation by accurate digital control of the feedback signal. Moreover, the predistortion (PD) signal can be extracted very efficiently. By combining the feedback linearization and DPD linearization techniques, the performance of the predistorter is enhanced significantly compared to the conventional DPD. To clearly visualize the characteristics of digital FBPD (DFBPD), we have compared it to the conventional DPD based on the recursive least square algorithm using Matlab simulation. The results clearly show that the new method is a good linearization algorithm, better than a conventional DPD. For the demonstration, a Doherty power amplifier with 180-W peak envelope power is linearized using the proposed DFBPD. For a 2.14-GHz forward-link wideband code-division multiple-access signal, the adjacent channel leakage ratio at 2.5-MHz offset is -58 dBc, which is improved by 15 dB at an average output power of 43 dBm     

包络跟踪的J类功率放大器设计

为了提高功率放大器的回退效率以更好地适应第五代移动通信系统的高峰均比信号的需求,文中提出了一种基于包络跟踪的J类功率放大器的设计方法,通过对电源调制器的设计来动态调制J类功率放大器的供电电压,以降低漏极直流功耗,实现提高功率放大器效率的目标.最终的测试结果表明在3.4～3.6GHz频率范围内,当采用带宽20MHz、峰均...     

A hybrid CT/DT double-sampled SMASH Σ? modulator for broadband applications in 90?nm CMOS technology

In this paper, a hybrid continuous-time (CT)/discrete-time (DT) multi-stage noise shaping (MASH) sigma?Cdelta (????) modulator architecture for broadband applications is presented. The double-sampling technique is employed in the DT second-stage modulator in order to reduce the power consumption of the overall modulator. Flat and unity signal transfer functions are used in the first- and second-stage modulators, respectively, to relax the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first-stage CT modulator. The proposed structure is insensitive to the amplifier limited dc gain of CT stage and avoids the need of compensation for finite gain-bandwidth induced error in CT loop filter. As a design example, the proposed MASH 2-2 modulator is designed in a 90?nm CMOS technology with 1?V power supply. Circuit level simulation results with HSPICE achieve the maximum SNDR of 74.8?dB and dynamic range of 76.5?dB in 12.5?MHz bandwidth with 17?mW power consumption while operating at 200?MHz sampling rate.     

Amplifier linearization using RF feedback and feedforwardtechniques

The performance of feedback as a distortion reduction technique is highly dependent on the integrity of the feedback path. Any error or noise generated in this path is directly reflected into the output of the amplifier. Linearized RF power amplifiers (PAs) using Cartesian feedback require a demodulator in the feedback loop, and this is a potential source of linear errors, nonlinear errors, and noise. RF feedback with Cartesian compensation is proposed as a technique for overcoming some of these problems. The scheme is most suited to systems requiring an RF input. In addition, the RF nature of the input, feedback, and error signals enables the addition of a feedforward loop to further improve the linearization capability while still maintaining good efficiency. Design equations and simulation results are given for such a system. Disadvantages include the limited bandwidth (estimated at 1 MHz) and the need for additional circuits to generate the RF input signal when included in an integrated transmitter     

Mixed Cartesian feedback for Zero-IF WCDMA transmitter

In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a classic WCDMA zero-intermediate frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB) loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feedback I/Q demodulator, and a digital stage adjusting the phase rotation around the loop. The whole system consumes 500 and 2.94 mW, respectively, for the analog and the digital part. System level simulation gave a maximum improvement of 35 dBc at 5 MHz from the carrier for the W-CDMA signal.     

基于压缩采样结构的盲多带信号预失真模型

针对在支撑集未知的情况下重构多频带信号的问题,本文提出了一种基于压缩采样结构的盲多带信号预失真模型,即将多频输出信号视为单个宽带信号,经下变频和低通滤波器处理后,送入A-MWC (Alternate Modulated Wideband Converter)结构进行盲压缩采样,而后通过基于随机支撑挑选的变步长稀疏度自适...     

基于调制域分析的功放线性化测量验证

针对目前功率放大器(Power Amplifier,PA)线性化测量验证方案需要较多的软硬件资源且测试效率低的问题,提出了一种适用于卫星通信领域的PA线性化测量与验证方法.该方法基于信号的调制域分析,首先信源端生成循环I/Q数据,然后经调制域分析仪进行信号采集后,由所提算法进行非线性特性提取,最后进行数字预失真(Digital Pre-distortion,DPD)算法验证.从仿真及测试结果来看,该测量验证方法对P A的非线性建模准确,最小二乘算法DP D效果明显.误差矢量幅度由11.17％降至5.49％,邻信道功率比由-31.75 dBc降低至-42.43 dBc,较好地补偿了PA的非线性特性.测量验证方案平台硬件资源简易,能够便捷获取高阶调制信号激励下的PA非线性测量以及有潜力验证各类DP D算法.     

Performance analysis of an all-digital BPSK direct-sequencespread-spectrum IF receiver architecture

A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel     

An 8 bit, 100 ms/s flash ADC

An 8-bit flash ADC capable of operation at a sampling rate higher than 100 MHz with only 1.2 W of power dissipation is described. This good performance is realized using: (1) a small transistor utilizing oxide isolation and a thick field oxide process with small parasitic capacitances; (2) an optimized design for speed, accuracy, and power; and (3) a simple comparator design with small component count. Analog input capacitance of 35 pF and full-scale bandwidth of higher than 40 MHz were obtained. An error under the beat frequency test was eliminated by decoupling the master and the slave latches of the comparator.     

A Design-Optimized Continuous-Time Delta–Sigma ADC for WLAN Applications

A third-order continuous-time delta-sigma (DeltaSigma) analog-to-digital converter (ADC) is presented for the conversion of an input signal bandwidth of 10 MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed low-power building blocks of the DeltaSigma modulator. From this point of view, it is shown that GmC integrators are preferred over RC integrators in the low-pass filter of the modulator because they show a better tradeoff between power, speed, and accuracy. A new single-bit quantizer topology is presented that incorporates a local feedback path that improves stability using a switched-voltage technique. Finally, a design methodology for the single-bit digital-to-analog converter (DAC) in the feedback loop is proposed, focusing on the impact of high sampling rates on the stability of the converter. The presented continuous-time ADC achieves a simulated dynamic range of 72 dB and a signal-to-noise-and-distortion-ratio of 66 dB in a 10-MHz signal bandwidth. Therefore, it can be applied for WLAN broadband communication. The power consumption of the DeltaSigma modulator is limited to 7.5 mW. The chip is designed in a 0.18-mum triple-well CMOS technology     

5G 功放DPD 的FPGA 宽带实现及自动优化

5G 宽带功放数字预失真器(DPD)的FPGA 实现过程中,常遇到数字处理带宽不够和资源有限问题,对 此,文中提出一种基于双路并行数据流的数字预失真带宽扩展方法和基于Zynq Ultrascale+ MPSoC 的自动化模型优化 验证方法,可快速实现对5G 宽带功放线性化方案的优化。使用该并行处理结构的数字预失真器,克服了数字电路最 大时钟频率造成的对FPGA 线性化带宽的限制,使得数字预失真电路在每个时钟周期内可以处理更多的数据,不仅有 效地增加了数字处理带宽,而且降低了DPD 的功耗。然而,这种带宽增加以消耗更多硬件资源为代价,对此,文中同时 提出了对预失真非线性模型的在线自动优化方法,以简化非线性模型、降低DPD 的硬件资源开销。最后,在Zynq Ultrascale+ FPGA 实验平台上实现了具有两路并行数据处理的I-MSA 自优化数字预失真电路,采用100 MHz 的5G 新无 线电(NR)信号在2. 6 GHz 功率放大器上进行线性化实验验证,获得了满意的预失真性能,验证了所提方法的有效性。     

宽带Chrip信号激励下功放数字预失真补偿

功率放大器(power amplifiers, PAs)会对输入的宽带线性调频信号(linear frequency modulated, LFM)引入幅度失真和相位失真,这将导致接收机脉冲压缩处理后的输出信号主瓣展宽,旁瓣电平抬高,从而恶化雷达距离分辨率甚至产生虚假目标。文中提出采用有限冲击响应滤波器(finite impulse response, FIR)模型对宽带LFM信号激励下的功放进行行为建模和数字预失真(digital predistortion, DPD)补偿。利用宽带测试平台对500 MHz 瞬时带宽LFM信号激励下峰值功率15 W 的S波段功放进行验证。实验结果表明,浅饱和和深饱和情况下FIR模型都能准确建模功放的失真特性,浅饱和情况下DPD能够补偿幅度失真和相位失真,而深饱和情况下只能补偿相位失真,经过DPD补偿脉冲压缩后的峰值旁瓣电平都明显降低。