Effects of spacer thickness on noise performance of bipolar transistors

The effects of spacer thickness on noise performance of a bipolar junction transistor with different emitter widths and operation frequencies are examined. The minimum noise figure (NF/sub min/) derived from the Y-parameters as well as the base (r/sub B/) and emitter resistance (r/sub E/) obtained from the device simulation is used as a measure of noise characteristics. Furthermore, the noise resistance (R/sub n/), optimum source admittance (Y/sub sop/), and the associated gain (G/sub A,assc/) are also given in this brief. To achieve the minimum value of NF/sub min/, the spacer thickness should be targeted to an optimal value, and its value is frequency and geometry dependent.     

4 kV 4H-SiC epitaxial emitter bipolar junction transistors

In this paper, we present 4H-SiC bipolar junction transistors (BJTs) with open-base blocking voltage (BV/sub CEO/) of 4000 V, specific on-resistance (R/sub on,sp/) of 56 m/spl Omega/-cm/sup 2/, and common-emitter current gain /spl beta//spl sim/9. These devices are designed with interdigitated base and emitter fingers with multiple emitter stripes. We assess the impact of design (emitter stripe width and contact spacing) on device performance and also examine the effect of emitter contact resistance on the device forward conduction characteristics.     

An analysis of small-signal source-body resistance effect on RF MOSFETs for low-cost system-on-chip (SoC) applications

In this paper, we demonstrate a comprehensive analysis of small-signal source-body resistance (R/sub sb/) effect on the RF performances of RF MOSFETs for low-cost system-on-chip (SoC) applications for the first time. Our results show that for RF MOSFETs, both the kink phenomena of S/sub 11/ and S/sub 22/ become more obscure as reverse body bias (V/sub B/) increases due to the decrease of transconductance (g/sub m/). In addition, an increase of source-body spacing enhances both the kink phenomena of S/sub 11/ and S/sub 22/, but deteriorates the current-gain cut-off frequency (f/sub T/), maximum oscillation frequency (f/sub MAX/), and RF noise and power performances due to the increase of R/sub sb/ of the devices. Analytical formulas are derived to explain the kink phenomena of S/sub 11/ and S/sub 22/, and to explain why increasing R/sub sb/ leads to a reduction of equivalent substrate resistance R/sub sub/, or worse f/sub T/, f/sub MAX/, and RF noise performances of the devices. The present analyzes enable RF engineers to understand the S-parameters, noise parameters, and power performances of RF MOSFETs more deeply, and hence are helpful for them to optimize the layout of MOSFETs and to create a fully scalable RF CMOS model for SoC applications.     

A comparison of low-frequency noise characteristics and noise sources in NPN and PNP InP-based heterojunction bipolar transistors

Low-frequency noise characteristics of NPN and PNP InP-based heterojunction bipolar transistors (HBTs) were investigated. NPN HBTs showed a lower base noise current level (3.85 /spl times/ 10/sup -17/ A/sup 2//Hz) than PNP HBTs (3.10 /spl times/ 10/sup -16/ A/sup 2//Hz), but higher collector noise current level (7.16 /spl times/ 10/sup -16/ A/sup 2//Hz) than PNP HBTs (1.48 /spl times/ 10/sup -16/ A/sup 2//Hz) at 10 Hz under I/sub C/=1 mA, V/sub C/=1 V. The NPN devices showed a weak dependence I/sub C//sup 0.77/ of the collector noise current, and a dependence I/sub B//sup 1.18/ of the base noise current, while the PNP devices showed dependences I/sub C//sup 1.92/ and I/sub B//sup 1.54/, respectively. The dominant noise sources and relative intrinsic noise strength were found in both NPN and PNP InP-based HBTs by comparing the noise spectral density with and without the emitter feedback resistor. Equivalent circuit models were employed and intrinsic noise sources were extracted. The high base noise current of PNP HBTs could be attributed to the exposed emitter periphery and higher electron surface recombination velocity in P-type InP materials, while the relatively high collector noise current of NPN HBTs may be due to the noise source originating from generation-recombination process in the bulk material between the emitter and the collector.     

Low-voltage high performance compact all cascode CMOS current mirror

A high performance and compact current mirror with extremely low input and high output resistances (R/sub in//spl sim/0.01/spl Omega/, R/sub out//spl sim/10 G/spl Omega/), high copying accuracy, very low input and output voltage requirements (V/sub in/, V/sub out//spl ges/V/sub DSsat/), high bandwidth (200 MHz using a 0.5 /spl mu/m CMOS technology) and low settling time (25 ns) is proposed. Simulations and experimental results are shown that validate the circuit.     

Ultra high-speed InP-InGaAs SHBTs with f/sub max/ of 478 GHz

InP-based single heterojunction bipolar transistors (SHBTs) for high-speed circuit applications were developed. Typical common emitter DC current gain (/spl beta/) and BV/sub CEO/ were about 17 and 10 V, respectively. Maximum extrapolated f/sub max/ of 478 GHz with f/sub T/ of 154 GHz was achieved for 0.5 /spl times/ 10 /spl mu/m/sup 2/ emitter size devices at 300 kA/cm/sup 2/ collector current density and 1.5 V collector bias. This is the highest f/sub max/ ever reported for any nontransferred substrate HBTs, as far as the authors know. This paper highlights the optimized conventional process, and the authors have great hopes for the process that offers inherent advantages for the direct implementation to high-speed electronic circuit fabrication.     

Location of 1/f noise sources in BJT's and HBJT's—I. theory

The most general case of1/fnoise in transistors can be described by three independent noise current generators: ibebetween base and emitter, ibcbetween base and collector, and iecbetween emitter and collector. By short-circuiting the base and the collector to ground and comparing the base and collector noise spectraS_{IB}(f)andS_{IC}(f)for the case of zero feedback from the emitter with the base and collector noise spectraS'_{IB}(f)andS'_{IC}(f)for the case of strong feedback from the emitter, one can evaluate the relative strength of the three noise sources. By measuring the current dependence ofS_{IB}(f),S_{IC}(f),S'_{IB}(f), andS'_{IC}(f), one can assign physical processes to the current generators ibc, ibe, and iec. It is the aim of this paper to demonstrate theoretically a simple method for locating1/fnoise sources in BJT's and HBJT's by comparing the base and collector1/fnoise for the cases without and with strong emitter feedback. In later papers we shall demonstrate experimentally how this method is applied to practical situations.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

A submicrometer 252 GHz f/sub T/ and 283 GHz f/sub MAX/ InP DHBT with reduced C/sub BC/ using selectively implanted buried subcollector (SIBS)

The selectively implanted buried subcollector (SIBS) is a method to decouple the intrinsic and extrinsic C/sub BC/ of InP-based double-heterojunction bipolar transistors (DHBTs). Similar to the selectively implanted collector (SIC) used in Si-based bipolar junction transistors (BJTs) and HBTs, ion implantation is used to create a N+ region in the collector directly under the emitter. By moving the subcollector boundary closer to the BC junction, SIBS allows the intrinsic collector to be thin, reducing /spl tau//sub C/, while simultaneously allowing the extrinsic collector to be thick, reducing C/sub BC/. For a 0.35 /spl times/ 6 /spl mu/m/sup 2/ emitter InP-based DHBT with a SIBS, 6 fF total C/sub BC/ and >6 V BV/sub CBO/ were obtained with a 110-nm intrinsic collector thickness. A maximum f/sub T/ of 252 GHz and f/sub MAX/ of 283 GHz were obtained at a V/sub CE/ of 1.6 V and I/sub C/ of 7.52 mA. Despite ion implantation and materials regrowth during device fabrication, a base and collector current ideality factor of /spl sim/2.0 and /spl sim/1.4, respectively, at an I/sub C/ of 100 /spl mu/A, and a peak dc /spl beta/ of 36 were measured.     

Microwave noise characteristics of AlGaN/GaN HEMTs on SiC substrates for broad-band low-noise amplifiers

This letter reports high-performance passivated AlGaN/GaN high electron-mobility transistors (HEMTs) with 0.25-/spl mu/m gate-length for low noise applications. The devices exhibited a minimum noise figure (NF/sub min/) of 0.98 dB and an associated gain (G/sub a/) of 8.97 dB at 18 GHz. The noise resistance (R/sub n/), the measure of noise sensitivity to source mismatch, is 31/spl Omega/ at 18 GHz, which is relatively low and suitable for broad-band low noise amplifiers. The noise modeling analysis shows that the minimum noise figure of the GaN HEMT can be reduced further by reducing noise contributions from parasitics. These results demonstrate the viability of AlGaN/GaN HEMTs for low-noise as well as high power amplifiers.     

Characterization of GaAs FET's in Terms of Noise, Gain, and Scattering Parameters through a Noise Parameter Test Set

A method for the complete characterization of GaAs FET's in terms of noise parameters (F/sub o/,Gamma/sub on/, R/sub n/), gain parameters (G/sub ao/, Gamma /sub og/, R/sub g/), and of those scattering parameters ( S/sub11/, S/sub22/|,S/sub12/| S/sub21|, /spl angle/S/sub 12/S/sub 21/ ) that are needed for low-noise microwave amplifier design is presented. The instrumentation employed, i.e., a noise-figure measuring system equipped with a vectorial reflectometer, as well as the time consumption, are the same required for the determination of noise parameters only through conventional methods. The measuring setup and the experimental procedure are described in detail. Considerations about the computer-aided data processing technique are also provided. As an experimental result, the characterization of a sample device versus frequency (4-12 GHz) and drain current is reported. A comparison between the scattering parameters provided by the method and those measured by means of a network analyzer is also included.     

InGaAs-InP metamorphic DHBTs grown on GaAs with lattice-matched device performance and f/sub /spl tau//, f/sub max/>268 GHz

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBTs) were grown on a GaAs substrate using a metamorphic buffer layer and then fabricated. The metamorphic buffer layer is InP - employed because of its high thermal conductivity to minimize device heating. An f/sub /spl tau// and f/sub max/ of 268 and 339 GHz were measured, respectively - both records for metamorphic DHBTs. A 70-nm SiO/sub 2/ dielectric sidewall was deposited on the emitter contact to permit a longer InP emitter wet etch for increased device yield and reduced base leakage current. The dc current gain /spl beta/ is /spl ap/35 and V/sub BR,CEO/=5.7 V. The collector leakage current I/sub cbo/ is 90 pA at V/sub cb/=0.3 V. These values of f/sub /spl tau//, f/sub max/, I/sub cbo/, and /spl beta/ are consistent with InP based DHBTs of the same layer structure grown on a lattice-matched InP substrate.     

Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs

The correlation between channel mobility gain (/spl Delta//spl mu/), linear drain-current gain (/spl Delta/I/sub dlin/), and saturation drain-current gain (/spl Delta/Idsat) of nanoscale strained CMOSFETs are reported. From the plots of /spl Delta/I/sub dlin/ versus /spl Delta/I/sub dsat/ and ballistic efficiency (Bsat,PSS), the ratio of source/drain parasitic resistance (R/sub SD,PSS/) to channel resistance (R/sub CH,PSS/) of strained CMOSFETs can be extracted. By plotting /spl Delta//spl mu/ versus /spl Delta/I/sub dlin/, the efficiency of /spl Delta//spl mu/ translated to /spl Delta/I/sub dlin/ is higher for strained pMOSFETs than strained nMOSFETs due to smaller RSD,PSS-to-RCH,PSS ratio of strained pMOSFETs. It suggests that to exploit strain benefits fully, the RSD,PSS reduction for strained nMOSFETs is vital, while for strained pMOSFETs the /spl Delta/I/sub dlin/-to-/spl Delta//spl mu/ sensitivity is maintained until R/sub SD,PSS/ becomes comparable to/or higher than R/sub CH,PSS/.     

Temperature dependence of 1/f noise in polysilicon-emitter bipolar transistors

1/f noise was measured on polysilicon-emitter bipolar n-p-n and p-n-p transistors over a temperature range of 173K相似文献   

A novel InGaP/Al/sub x/Ga/sub 1-x/As/GaAs CEHBT

A new and interesting InGaP/Al/sub x/Ga/sub 1-x/As/GaAs composite-emitter heterojunction bipolar transistor (CEHBT) is fabricated and studied. Based on the insertion of a compositionally linear graded Al/sub x/Ga/sub 1-x/As layer, a near-continuous conduction band structure between the InGaP emitter and the GaAs base is developed. Simulation results reveal that a potential spike at the emitter/base heterointerface is completely eliminated. Experimental results show that the CEHBT exhibits good dc performances with dc current gain of 280 and greater than unity at collector current densities of J/sub C/=21kA/cm/sup 2/ and 2.70/spl times/10/sup -5/ A/cm/sup 2/, respectively. A small collector/emitter offset voltage /spl Delta/V/sub CE/ of 80 meV is also obtained. The studied CEHBT exhibits transistor action under an extremely low collector current density (2.7/spl times/10/sup -5/ A/cm/sup 2/) and useful current gains over nine decades of magnitude of collector current density. In microwave characteristics, the unity current gain cutoff frequency f/sub T/=43.2GHz and the maximum oscillation frequency f/sub max/=35.1GHz are achieved for a 3/spl times/20 /spl mu/m/sup 2/ device. Consequently, the studied device shows promise for low supply voltage and low-power circuit applications.     

Compression mappings on primitive sequences over Z/(p/sup e/)

Let Z/(p/sup e/) be the integer residue ring with odd prime p/spl ges/5 and integer e/spl ges/2. For a sequence a_ over Z/(p/sup e/), there is a unique p-adic expansion a_=a_/sub 0/+a_/spl middot/p+...+a_/sub e-1//spl middot/p/sup e-1/, where each a_/sub i/ is a sequence over {0,1,...,p-1}, and can be regarded as a sequence over the finite field GF(p) naturally. Let f(x) be a primitive polynomial over Z/(p/sup e/), and G'(f(x),p/sup e/) the set of all primitive sequences generated by f(x) over Z/(p/sup e/). Set /spl phi//sub e-1/ (x/sub 0/,...,x/sub e-1/) = x/sub e-1//sup k/ + /spl eta//sub e-2,1/(x/sub 0/, x/sub 1/,...,x/sub e-2/) /spl psi//sub e-1/(x/sub 0/,...,x/sub e-1/) = x/sub e-1//sup k/ + /spl eta//sub e-2,2/(x/sub 0/,x/sub 1/,...,x/sub e-2/) where /spl eta//sub e-2,1/ and /spl eta//sub e-2,2/ are arbitrary functions of e-1 variables over GF(p) and 2/spl les/k/spl les/p-1. Then the compression mapping /spl phi//sub e-1/:{G'(f(x),p/sup e/) /spl rarr/ GF(p)/sup /spl infin// a_ /spl rarr/ /spl phi//sub e-1/(a_/sub 0/,...,a_/sub e-1/) is injective, that is, a_ = b_ if and only if /spl phi//sub e-1/(a_/sub 0/,...,a_/sub e-1/) = /spl phi//sub e-1/(b_/sub 0/,...,b_/sub e-1/) for a_,b_ /spl isin/ G'(f(x),p/sup e/). Furthermore, if f(x) is a strongly primitive polynomial over Z/(p/sup e/), then /spl phi//sub e-1/(a_/sub 0/,...,a_/sub e-1/) = /spl psi//sub e-1/(b_/sub 0/,...,b_/sub e-1/) if and only if a_ = b_ and /spl phi//sub e-1/(x/sub 0/,...,x/sub e-1/) = /spl psi//sub e-1/(x/sub 0/,...,x/sub e-1/) for a_,b_ /spl isin/ G'(f(x),p/sup e/).     

15-nm base type-II InP/GaAsSb/InP DHBTs with F/sub T/=384 GHz and a 6-V BV/sub CEO/

Type-II InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a 15-nm base were fabricated by contact lithography: 0.73/spl times/11 /spl mu/m/sup 2/ emitter devices feature f/sub T/=384GHz (f/sub MAX/=262GHz) and BV/sub CEO/=6V. This is the highest f/sub T/ ever reported for InP/GaAsSb DHBTs, and an "all-technology" record f/sub T//spl times/BV/sub CEO/ product of 2304 GHz/spl middot/V. This result is credited to the favorable scaling of InP/GaAsSb/InP DHBT breakdown voltages (BV/sub CEO/) in thin collector structures.     

Temperature and substrate-impedance dependence of noise figure of monolithic RF inductors on silicon

In this letter, we analyze the effects of temperature (from -50/spl deg/C to 200/spl deg/C) and substrate impedance on the noise figure (NF) and quality factor (Q-factor) performances of monolithic RF inductors on silicon. The results show a 0.75 dB (from 0.98 to 0.23 dB) reduction in minimum NF (NF/sub min/) at 8 GHz, an 86.1% (from 15.1 to 28.1) increase in maximum Q-factor (Q/sub max/), and a 4.8% (from 16.5 to 17.3 GHz) improvement in self-resonant frequency (f/sub SR/) were obtained if post-process of proton implantation had been done. This means the post-process of proton implantation is effective in improving the NF and Q-factor performances of inductors on silicon mainly due to the reduction of eddy current loss in the silicon substrate. In addition, it was found that NF increases with increasing temperature but show a reverse behavior within a higher frequency range. This phenomenon can be explained by the positive temperature coefficients of the series metal resistance (R/sub s/), the parallel substrate resistances (R/sub sub1/ and R/sub sub2/), and the resistance R/sub s1/ of the substrate transformer loop. The present analyzes are helpful for RF designers to design less temperature-sensitive high-performance fully on-chip low-noise-amplifiers (LNAs) and voltage-controlled-oscillators (VCOs) for single-chip receiver front-end applications.     

Wideband DHBTs using a graded carbon-doped InGaAs base

We report an InP/InGaAs/InP double heterojunction bipolar transistor (DHBT), fabricated using a mesa structure, exhibiting 282 GHz f/sub /spl tau// and 400 GHz f/sub max/. The DHBT employs a 30 nm InGaAs base with carbon doping graded from 8/spl middot/10/sup 19//cm/sup 3/ to 5/spl middot/10/sup 19//cm/sup 3/, an InP collector, and an InGaAs/InAlAs base-collector superlattice grade, with a total 217 nm collector depletion layer thickness. The low base sheet (580 /spl Omega/) and contact (<10 /spl Omega/-/spl mu/m/sup 2/) resistivities are in part responsible for the high f/sub max/ observed.