A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter

A 175 Ms/s A/D converter with a latency of one clock cycle is designed in a 0.7 μm digital CMOS technology. The resolution of the converter is 6 b while the power dissipation is only 160 mW. The A/D converter architecture is based on a continuous time analog preprocessing topology. A continuous time current interpolation circuit is implemented. The performance of the A/D converter is ruled by a tradeoff between speed, power, and accuracy     

An interpolative bandpass converter on a 1.2-μm BiCMOSanalog/digital array

The architecture and performance of an interpolative bandpass A/D converter (ADC) and digital quadrature demodulator dedicated for digital narrowband transmission systems, like the cellular radio mobile receiver, are presented. A prototype version has been implemented on a 1.2-μm/7-GHz BiCMOS analog/digital array. A bandpass signal centered at 6.5 MHz with 200-kHz bandwidth is demodulated and converted with a 55-dB signal-to-noise ratio giving 9-b performance     

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal-lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm~2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.     

A full Nyquist 15 MS/s 8-b differential switched-current A/Dconverter

This paper describes the architecture and circuit design of an experimental 8-b differential 15 MS/s CMOS A/D converter, implemented using the switched-current (SI) technique. Particular emphasis has been given to maintaining analog bandwidth and hence the effective number of bits right across the input Nyquist band. Individual cells have also been optimized for inherent accuracy to achieve good performance in a simple uncorrected conversion algorithm. The converter is fabricated in a standard 0.8 μm 5 V digital CMOS process and occupies 2.4 mm²      

Mixed digital/analog signal processing for a single-chip 2B1Q U-interface transceiver

Mixed analog-digital signal processing aspects of a 5-V single-chip U-interface 2B1Q transceiver are discussed. Analog signal processing preconditions the signal by reducing jitter-induced echo and nonlinear echo components, and by maximizing the dynamic range utilization of the 13-b analog-to-digital (A/D) converter. The digital signal processor performs the high-pass filtering, precursor equalization, linear echo cancellation, far-end signal equalization, and timing recovery functions. The analog signal preconditioning technique allows the entire digital signal processing (DSP) section to be designed without a single dedicated multiplier. The U-interface transceiver has been realized in a 1.5-μm double-metal CMOS process, resulting in a circuit area of 77 mm². Total power consumption is 300 mW. To comply with the ANSI-specified performance test procedures, a crosstalk noise generator and injection circuit were custom built along with a jitter generation system, all of which match the ANSI noise and jitter templates. Testing was performed over the 15 ANSI loops and countless other random configurations. Full compliance with the standard protocol and timing limits was achieved on all the loops     

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design andperformance evaluation

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f_t were developed for the integrators. The circuit is implemented in a 1.75-μm 5-V CMOS process. The analog circuitry occupies 2 mm² of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software     

Area-efficient multichannel oversampled PCM voice-band coder

The authors describe the design of a four-channel oversampled A/D (analog/digital) converter with transmit filter for voice-band application. The decimator filter is timeshared between the four channels and the architecture of the sigma-delta coder is selected on the basis of minimizing the chip area. The analog front-end loop is fully differential to minimize the channel-to-channel crosstalk. The key issues in designing a multichannel oversampled A/D converter for area efficiency are addressed. It is concluded that for the multichannel telephony voice-band application implemented in CMOS technology, a first-order loop is most area-efficient. The performance of the coder has been evaluated and it is shown to have a dynamic range of 79 dB, to occupy a total active area of 33000 mils² or 8250 mils² per channel, and to meet the D3 specifications for the transmit filter. It runs on a 5-V supply and consumes 50 mW per channel     

A 14-bit 10-μs subranging A/D converter with S/H

A microprocessor-compatible, 14-bit, 10-μs subranging analog-to-digital converter with a sample/hold amplifier (SHA) is described. The chip architecture is based on a five-cycle subranging flash technique using both analog and digital error correction. The conversion speed is enhanced by an analog correction method, whereby redundant bit currents allow digital/analog converter updates without changing bits determined in previous cycles. The residue signal path uses simple circuitry and is highly differential. Prototype performance has been demonstrated     

A 125-MHz mixed-signal echo canceller for Gigabit Ethernet oncopper wire

A discrete-time analog echo canceller is described that reduces the echo in the front end of Gigabit Ethernet twisted-pair interfaces. Echo cancellation in the analog domain by means of four taps reduces the complexity of the digital echo canceller and crosstalk cancellers. Designed in a 0.4-μm CMOS technology, the circuit employs an LMS algorithm to adapt to the cable length and impedance discontinuities, providing an echo suppression of 10 dB. The design operates at 125 MHz while consuming 43 mW from a 3-V supply     

一种单斜坡积分型A／D转换器

介绍了一种单斜坡积分型模／数转换器的设计原理及关键技术。提出了输入对管匹配和非匹配失调设计技术，从电路、版图和工艺上进行优化设计。采用铝栅工艺研制的ＳＡＤ４４４７六通道模／数转换器在５Ｖ、１０Ｖ、１５Ｖ三种电源下工作，转换线性度＜０．３％，电路在－５５～１２５°Ｃ环境温度下能可靠地工作     

基于微小井眼钻井技术的A/D转换器选型研究

微小井眼钻井技术是国外近年来发展起来一种前沿技术,具有成本低、安全环保和勘探开发效率高等特点.通过A/D、D/A转换器将井下模拟信号转换为数字信号,经处理后,将数字信号在转换成模拟信号去控制设备,实现井下的采集、通讯、控制任务.本文通过提出A/D转换器的选型原则,综合考虑性能参数、数字接口、原理结构、工作温度等各个方面,选择出适合随钻测量短节设计的A/D转换器,保证井下系统数据采集过程的稳定,对整个微小井眼钻井设备具有重要的作用.     

基于功率D/A转换的音频功率放大器

设计了一种基于A/D和D/A相互转换的音频功率放大器.A/D转换后的数字音频信号经电平匹配和隔离驱动后,控制功率D/A转换电路进行音频还原和功率放大.当转换位数足够时,能基本不失真地还原音频信号.对功率D/A转换输出的阶梯波进行逐级分析,得出开关器件工作频率、器件通态损耗和开关损耗的计算式.利用多级自举方法,减少了驱动电源数目.实验结果表明,这是一种效率较高的音频功率放大器.     

A 30-MHz mixed analog/digital signal processor

A multiplying encoder architecture that is implemented in the design of a mixed analog and digital signal processor is presented. The processor is suitable for performing both high-speed A/D conversion and digital filtering in a single chip. The device can resolve the input with 8 b at 30 Msample/s and perform 28 multiply and 28 add operations per sample under typical conditions. The processor is designed for a 28-tap programmable FIR (finite impulse response) filter with analog input signal which can be used for waveform shaping of the modem to obtain the desired transmission performance for business satellite communication and mobile communication. The chip is fabricated in a 1-μm double-polysilicon and double-metal CMOS technology. The chip size is 9.73×8.14 mm², and the chip operates with a single +5.0-V power supply. Typical power dissipation is 950 mW; 330 mW is dissipated in analog and 620 mW is in the digital block     

The Wheatstone bridge-based analog adaptive filter with application in echo cancellation

In this paper, a new analog adaptive filter is introduced with application in adaptive echo cancellation namely, the Wheatstone bridge-based analog adaptive filter (WAAF). It is proved the WAAF is a variable weight analog IIR filter. IIR filter weights vary with gate-source voltage control of a MOSFET transistor in triode region. The best balance point control of the WAAF is achieved using least mean square (LMS) algorithm. It is proved that analog LMS algorithm converges faster than digital LMS adaptive filter. The superiority of the proposed WAAF is observed in the designing process, computational cost, convergence speed and real time operation. Also, experimental results show ability of the proposed WAAF in the hybrid circuit of the telephone echo cancellation.     

WCDMA直放站回波对消方案设计

基于WCDMA标准提出了FPGA+DPS平台下实现在数字中频技术中抵消WCDMA直放站回波干扰信号的方案.首先发射与WCDMA信号不相关的伪随机序列CAZAC码作为训练序列进行信道初估计,然后将初估计得到的时延和幅度信息作为赋给LMS自适应滤波器的初值,生成逼近干扰信号的抵消信号,实现回波对消.使用MATLAB和SIMULINK联合仿真,证明该方法拥有良好的性能.     

1 V power supply, low-power consumption A/D conversion techniquewith swing-suppression noise shaping

A 1 V power supply and low-power consumption A/D conversion technique using swing-suppression noise shaping is proposed. This technique makes it possible to power the on chip A/D converter in digital LSI's directly by a one-cell battery, without a dc-dc converter. Experimental results indicated good performance for the RF-to-baseband analog interface of a digital cordless phone. The A/D converter, fabricated with a 0.5 μm CMOS process, operates on a 1 V power supply, has a 10 bit dynamic-range with a 384 ksps sampling speed and consumes only 1.56 mW     

一种∑-Δ模数转换器

∑-Δ模数转换器是一种高度集成化的新型模数转换器,采用过采样技术,无需采样保持电路.它内置了多路复用器、可编程放大器、调制器、数字滤波器、校准系统和串行接口.其转换率最高为150kHz,分辨率可达24位.本文对该系列∑-Δ模数转换器的原理结构及其操作进行简单介绍.     

A 12-bit sigma-delta analog-to-digital converter with a 15-MHz clock rate

A sigma-delta analog-to-digital converter that achieves 12-bit integral and differential linearity and nearly 13-bit resolution without trimming is described. The baseband width is 120 kHz with a first filter pole at 60 kHz, the clock frequency is 15 MHz, and only one 5-V power supply is needed. The circuit was realized in a p-well CMOS technology with 3-/spl mu/m minimum feature size. Compared with previous sigma-delta modulators, the input signal frequency and clock rate limit have been increased by one order of magnitude. To achieve this increase, a novel integrator concept was developed using bidirectional current sources. The circuit is fully self-contained, requiring only a 15-MHz crystal and one blocking capacitor as external elements. This converter was developed as the analog front end of a digital echo cancellation circuit for an integrated services digital network.     

A single-chip 2B1Q U-interface transceiver

A single-chip transceiver designed to meet the American National Standards Institute (ANSI) requirements for the U-interface in the integrated services digital network (ISDN) is described. The device utilizes linear, jitter-compensated, and nonlinear echo cancellation and the 2B1Q line code to achieve high performance in the presence of near-end crosstalk and other impairments. The 2-μm, single-metal, double-polysilicon, 5-V CMOS VLSI chip includes all the necessary analog and digital signal processing blocks for a network-termination of line-termination U-interface to be realized with the addition of a passive-line termination circuit and a transformer. Operation over 4.7 km of 0.4-mm cable or 7.5 km of 0.5-mm cable, with a bit error rate of 10^-7, is possible     

A digital signal processor for an ANSI standard ISDN transceiver

The digital signal processing chip of a two-chip ISDN (integrated services digital network) basic access transceiver based on the ANSI standard 2B1Q code is described. Nonlinear echo cancellation is used to improve the loop coverage. The chip features a multiprocessor architecture, where each processor is optimized for the algorithm used. Full observability of internal signals and adaptive filter coefficients is supported. The device is fabricated in a 1.25-μm double-level-metal CMOS process with an active area of 47 mm²