共查询到20条相似文献,搜索用时 31 毫秒
1.
Meghelli M. Rylyakov A.V. Zier S.J. Sorna M. Friedman D. 《Solid-State Circuits, IEEE Journal of》2003,38(12):2147-2154
A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120-GHz f/sub T/ and 100 GHz f/sub max/. The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10/sup -9/ is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a -3.6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a -3.6-V supply voltage. 相似文献
2.
Lao Z. Guinn K. Delaney M. Jensen J. Fields C. Thomas S. 《Microwave and Wireless Components Letters, IEEE》2005,15(7):469-471
A packaged D-type flip-flop (DFF) decision circuit for optical OC-768 systems and testing equipment is reported. The circuit uses 1 /spl mu/m InP SHBT technology featuring f/sub T//f/sub max/=150 GHz and has been operated up to 45 Gb/s with a clock phase margin about 180/spl deg/. Measured output eye diagrams from packaged devices exhibit 9/8 ps rise/fall with only 3ps peak-peak jitter. A single-ended AC-coupled clock input makes the application of this circuit very convenient. The IC dissipates 440 mW from a -4V supply voltage. 相似文献
3.
An ultra-high-speed selector IC has been developed for future optical transmission systems. The IC was fabricated with AlGaAs/GaAs HBT technology, for which the f/sub T/ is about 70 GHz. It operates at 28 Gbit/s with an output voltage swing of 1 V/sub p-p/. This is the fastest operating speed ever reported for a selector IC using any technology.<> 相似文献
4.
Krishnamurthy K. Chow J. Mensa D. Pullela R. 《Microwave and Wireless Components Letters, IEEE》2004,14(1):28-30
Packaged master-slave D-flip-flops designed in InP DHBT technology with 150 GHz f/sub t/ and 180 GHz f/sub max/ are presented. Measurement results using a 43.2 Gb/s nonreturn to zero (NRZ), pseudo random binary sequence (PRBS) data (generated from 4 channels of 10.8 Gb/s, 2/sup 31/-1, PRBS data) and a 43.2 GHz clock, show a clock phase margin of 190/spl deg/. 2:1 Static frequency dividers designed using the D-flip-flops have been tested up to 50 GHz and show normal operation. These circuits are key building blocks in numerous front-end circuits used for 40 Gb/s optical communication systems. 相似文献
5.
Ong A. Benyamin S. Cancio J. Condito V. Labrie T. Qinghung Lee Mattia J.P. Shaeffer D.K. Shahani A. Xiaomin Si Hai Tao Tarsia M. Wong W. Min Xu 《Solid-State Circuits, IEEE Journal of》2003,38(12):2155-2168
A fully integrated OC-768 clock and data recovery IC with SFI-5 1:16 demultiplexer is designed in a 120-GHz/100-GHz (f/sub T//f/sub MAX/) SiGe technology. The 16 2.5-Gb/s outputs and additional deskew channel are compliant with the Serdes Framer Implementation Agreement Level 5 specification. The measured bit-error rate is <10/sup -15/. The measured jitter tolerance exceeds the mask specified in G.8251. The IC operates with 1.8-V and -5.2-V supplies and dissipates 7.5 W. 相似文献
6.
Kishine K. Fujimoto K. Kusanagi S. Ichino H. 《Solid-State Circuits, IEEE Journal of》2004,39(5):740-750
A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the "limited pull-in range," and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm. 相似文献
7.
A static frequency divider designed in a 210-GHz f/sub T/, 0.13-/spl mu/m SiGe bipolar technology is reported. At a -5.5-V power supply, the circuit consumes 44 mA per latch (140 mA total for the chip, with input-output stages). With single-ended sine wave clock input, the divider is operational from 7.5 to 91.6 GHz. Differential clocking under the same conditions extends the frequency range to 96.6 GHz. At -5.0 V and 100 mA total current (28 mA per latch), the divider operates from 2 to 85.2 GHz (single-ended sine wave input). 相似文献
8.
Myung-Jun Choe Kwang-Hyun Baek Teshome M. 《Solid-State Circuits, IEEE Journal of》2005,40(12):2456-2468
A 12-bit 1.6-GS/s digital-to-analog converter (DAC) implemented with 4-/spl mu/m/sup 2/ GaAs HBT process is presented. Return-to-zero (RZ) current switches are added to current steering DAC for high-frequency wideband applications to achieve 800-MHz bandwidth at first and second Nyquist band without the need for a reverse sinc equalization filter in wideband transmitter application. The RZ circuit also improves spectral purity by screening the switching noise from the analog output during data transition. Measured performance shows two-tone third-order harmonic distortion of -70 dB at 1.5-GHz output frequency, clocked at 1.6 GHz. Reliable interface with CMOS logic IC is guaranteed with the inclusion of a four-clock-deep FIFO circuit. The DAC dissipates 1.2 W at -5 V when sampled with 1.6-GHz clock, with typical output voltage swing of 1.2 V/sub PP/. 相似文献
9.
SiGe BiCMOS technology for RF circuit applications 总被引:4,自引:0,他引:4
SiGe BiCMOS is reviewed with focus on today's production 0.18-/spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/, as well as lower power consumption, noise figure, and improved large-signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high-power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz). 相似文献
10.
Masuda T. Ohhata K. Shiramizu N. Ohue E. Oda K. Hayami R. Shimamoto H. Kondo M. Harada T. Washio K. 《Solid-State Circuits, IEEE Journal of》2005,40(3):791-795
A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction. 相似文献
11.
Yun Wei Scott D.W. Yingda Dong Gossard A.C. Rodwell M.J. 《Electron Device Letters, IEEE》2004,25(5):232-234
We report a 0.7/spl times/8 /spl mu/m/sup 2/ InAlAs-InGaAs-InP double heterojunction bipolar transistor, fabricated in a molecular-beam epitaxy (MBE) regrown-emitter technology, exhibiting 160 GHz f/sub T/ and 140 GHz f/sub MAX/. These initial results are the first known RF results for a nonselective regrown-emitter heterojunction bipolar transistor, and the fastest ever reported using a regrown base-emitter heterojunction. The maximum current density is J/sub E/=8/spl times/10/sup 5/ A/cm/sup 2/ and the collector breakdown voltage V/sub CEO/ is 6 V for a 1500-/spl Aring/ collector. In this technology, the dimension of base-emitter junction has been scaled to an area as low as 0.3/spl times/4 /spl mu/m/sup 2/ while a larger-area extrinsic emitter maintains lower emitter access resistance. Furthermore, the application of a refractory metal (Ti-W) base contact beneath the extrinsic emitter regrowth achieves a fully self-aligned device topology. 相似文献
12.
Betser Y. Scott D. Mensa D. Jaganathan S. Mathew T. Rodwell M.J. 《Electron Device Letters, IEEE》2001,22(2):56-58
We report the design, fabrication, and measurement of InAlAs/InGaAs heterostructure bipolar transistors (HBTs) designed for high speed digital circuits. At 0.96 V V/sub CE/ the current gain cutoff frequency, f/sub /spl tau//, is 300 GHz and the maximum frequency of oscillation, f/sub max/, is 235 GHz. This value of f/sub /spl tau//, is the highest reported for bipolar transistors. At a slightly higher V/sub CE/ bias, a high value of 295 GHz for f/sub /spl tau// and f/sub max/ were obtained simultaneously. 相似文献
13.
Charlon O. Locher M. Visser H.A. Duperray D. Chen J. Judson M. Landesman A.L. Hritz C. Kohlschuetter U. Yifeng Zhang Ramesh C. Daanen A. Minzhan Gao Haas S. Maheshwari V. Bury A. Nitsche G. Wrzyszcz A. Redman-White W. Bonakdar H. Rachid El Waffaoui Bracey M. 《Solid-State Circuits, IEEE Journal of》2006,41(7):1503-1512
This paper describes a high-performance WLAN 802.11a/b/g radio transceiver, optimized for low-power in mobile applications, and for co-existence with cellular and Bluetooth systems in the same terminal. The direct-conversion transceiver architecture is optimized in each mode for low-power operation without compromising the challenging RF performance targets. A key transceiver requirement is a sensitivity of -77 dBm (at the LNA input) in 54 Mb/s OFDM mode while in the presence of a GSM1900 transmitter interferer. The receiver chain achieves an overall noise figure of 2.8/3.2 dB, consuming 168/185 mW at 2.8 V for the 2.4/5GHz bands, respectively. Signal loopback and transmit power detection techniques are used in conjunction with the baseband modem processor to calibrate the transmitter LO leakage and the transceiver I/Q imbalances. Fabricated in a 70 GHz f/sub T/ 0.25-/spl mu/m SiGe BiCMOS technology for system-in-package (SiP) use, the dual-band, tri-mode transceiver occupies only 4.6 mm/sup 2/. 相似文献
14.
Gunnarsson S.E. Karnfelt C. Zirath H. Kozhuharov R. Kuylenstierna D. Alping A. Fager C. 《Solid-State Circuits, IEEE Journal of》2005,40(11):2174-2186
Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3). 相似文献
15.
AlGaN/GaN HEMTs on SiC with f/sub T/ of over 120 GHz 总被引:1,自引:0,他引:1
Kumar V. Lu W. Schwindt R. Kuliev A. Simin G. Yang J. Asif Khan M. Adesida I. 《Electron Device Letters, IEEE》2002,23(8):455-457
AlGaN/GaN high electron mobility transistors (HEMTs) grown on semi-insulating SiC substrates with a 0.12 /spl mu/m gate length have been fabricated. These 0.12-/spl mu/m gate-length devices exhibited maximum drain current density as high as 1.23 A/mm and peak extrinsic transconductance of 314 mS/mm. The threshold voltage was -5.2 V. A unity current gain cutoff frequency (f/sub T/) of 121 GHz and maximum frequency of oscillation (f/sub max/) of 162 GHz were measured on these devices. These f/sub T/ and f/sub max/ values are the highest ever reported values for GaN-based HEMTs. 相似文献
16.
Fujita S. Suzaki T. Matsuoka A. Miyazaki S. Torikai T. Nakata T. Shikada M. 《Electronics letters》1990,26(3):175-176
A 5 Gbit/s optical receiver module was developed by using a wideband transimpedance Si IC and a high gain-bandwidth product GaInAs APD. A 6 GHz bandwidth Si IC utilising a f/sub t/=20 GHz Si MMIC process, bare chip mounting of a Si IC and an APD to minimise parasitic capacitance, made it possible to realise high speed operation and high receiver sensitivity of -31.8 dBm.<> 相似文献
17.
Sato F. Hashimoto T. Tezuka H. Soda M. Suzaki T. Tatsumi T. Tashiro T. 《Electron Devices, IEEE Transactions on》1999,46(7):1332-1338
A 60-GHz cutoff frequency (fT) super self-aligned selectively grown SiGe-base (SSSB) bipolar technology is developed. It is applied to 20-Gb/s optical fiber transmitter ICs. Self-aligned bipolar transistors mutually isolated by using a BPSG-filled trench were fabricated on a bond-and-etchback silicon-on-insulator (SOI) substrate to reduce the collector-substrate capacitance CCS. The SiGe base was prepared by selective epitaxial growth (SEG) technology. A 0.4-μm wide emitter was used to reduce the junction capacitances. The maximum cutoff frequency fT and the maximum frequency of oscillation fmax were 60 and 51 GHz, respectively. By using this technology, Si-ICs for an optical transmitter system were made, such as a selector (a multiplexer without input and output retiming D-type flip-flops (D-F/Fs)), a multiplier, and a D-F/F. An internal high-speed clock buffer circuit achieves stable operation under a single clock input condition in the selector and the multiplier ICs. Their stable operation was confirmed up to 20 Gb/s. The selector IC for data multiplexing operates at over 30 Gb/s 相似文献
18.
Griffith Z. Dahlstrom M. Rodwell M.J.W. Fang X.-M. Lubyshev D. Wu Y. Fastenau J.M. Liu W.K. 《Electron Device Letters, IEEE》2005,26(1):11-13
InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBT) have been designed for use in high bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 391-GHz f/sub /spl tau// and 505-GHz f/sub max/, which is the highest f/sub /spl tau// reported for an InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The devices have been aggressively scaled laterally for reduced base-collector capacitance C/sub cb/. In addition, the base sheet resistance /spl rho//sub s/ along with the base and emitter contact resistivities /spl rho//sub c/ have been lowered. The dc current gain /spl beta/ is /spl ap/36 and V/sub BR,CEO/=5.1 V. The devices reported here employ a 30-nm highly doped InGaAs base, and a 150-nm collector containing an InGaAs-InAlAs superlattice grade at the base-collector junction. From this device design we also report a 142-GHz static frequency divider (a digital figure of merit for a device technology) fabricated on the same wafer. The divider operation is fully static, operating from f/sub clk/=3 to 142.0 GHz while dissipating /spl ap/800 mW of power in the circuit core. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies >100 GHz. 相似文献
19.
A 16:1 STS-768 multiplexer IC has been designed and fabricated using the Vitesse Semiconductor VIP-1 process. This IC is part of a complete chip-set solution for a 40-Gb/s STS-768 optical communication transceiver module. The multiplexer IC features a full-rate clock multiplication unit and a data retimer in the output stage to reduce duty-cycle distortion and jitter in the output data eye. Because of its strict timing requirements, this approach needs fast logic gates with a very low gate delay. The Vitesse VIP-1 process, with 150-GHz f/sub t/ and 150-GHz f/sub max/ heterojunction bipolar transistor, is an obvious choice to implement this IC. The multiplexer IC typically dissipates 3.6 W from -3.6-V and -5.2-V power supplies. This paper discusses the design and development of a 40-Gb/s 16:1 multiplexer IC including current-mode logic gate circuit design, divide-by-two, 40-GHz clock tree, voltage-controlled oscillator, clock multiplication unit, and output driver. Layout design and package design are also discussed due to their significant roles in the IC performance. 相似文献
20.
Type-II InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) with a 15-nm base were fabricated by contact lithography: 0.73/spl times/11 /spl mu/m/sup 2/ emitter devices feature f/sub T/=384GHz (f/sub MAX/=262GHz) and BV/sub CEO/=6V. This is the highest f/sub T/ ever reported for InP/GaAsSb DHBTs, and an "all-technology" record f/sub T//spl times/BV/sub CEO/ product of 2304 GHz/spl middot/V. This result is credited to the favorable scaling of InP/GaAsSb/InP DHBT breakdown voltages (BV/sub CEO/) in thin collector structures. 相似文献