A compact MOST model for design analysis

A dc model of the 4-terminal MOS transistor is described that eliminates the need for piecewise definition of the channel current while maintaining sufficient physical correspondence to accurately represent modern MOS devices used in arrays. The determination of model parameters is straightforward.     

Circuit analysis, logic simulation, and design verification for VLSI

In this paper, we consider computer-aided design techniques for VLSI. Specifically, the areas of circuit analysis, logic simulation and design verification are discussed with an emphasis on time domain techniques. Recently, researchers have concentrated on two general problem areas. One important problem discussed is the efficient, exact-time analysis of large-scale circuits. The other area is the unification of these techniques with logic simulation and design verification technique in so called multimode or multilevel systems.     

A compact thermal noise model for the investigation of soft errorrates in MOS VLSI digital circuits

A compact VLSI MOSFET model that includes an integrated thermal noise model and a methodology for the analysis of the effects of thermal noise on the performance and error rates of digital integrated circuits is presented. The usefulness of the model and methodology is demonstrated by comparing simulation results for signal-to-noise ratio to analytic results for the balanced bit-line architecture of the single-device DRAM and the associated cross-coupled pair sense amplifier. The design options and tradeoffs related to thermal noise are introduced for both the balanced bit lines and the sense amplifier are considered. The error rate as a function of signal-to-noise ratio is determined, and possible limits to DRAM construction due to inherent thermal noise are highlighted     

A computationally efficient model of single electron transistor for analog IC simulation

A compact analytical single electron transistor (SET) model is proposed. This model is based on the “orthodox theory” of single electron tunneling, valid for unlimited range of drain to source voltage, valid for single or multi-gate, symmetric or asymmetric devices and takes the background charge effect into account. This model is computationally efficient in comparison with existing models. SET characteristics produced by the proposed model have been verified against Monte Carlo simulator SIMON and show good agreement. This model has been implemented in HSPICE simulator through its Verilog-A interface to enable simulation with conventional MOS devices and single electron inverter has been simulated and verified with SIMON results. At high operating temperature, the thermionic current is taken into account.     

Whole-chip ESD protection design with efficient VDD-to-VSS ESDclamp circuits for submicron CMOS VLSI

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-μm CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-μm CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV     

A simple and efficient measurement method for characterizingcapacitance matrix of multilayer interconnection in VLSI

A compact new test structure for direct extraction of components of the capacitance matrix for multilayer interconnections is presented. In this new method, each capacitive component in integrated structures is separately and directly obtained from measurement, and the total pads are kept to eight, independent of the size of the target matrix. As a result of evaluation of measurement errors caused by the asymmetry of structures, this new method can measure components of capacitance matrix with a precision of femto-farad order     

An efficient and reliable MRF-based methodology for designing low-power VLSI circuits

Noise-interference is one of the major concerns in low-power VLSI circuits. Due to power supply downscaling, these circuits have an extremely limited noise margin that is inadequate for dealing with intrinsic and extrinsic noise. The MRF-based design has been accepted as a highly effective method for designing noise-tolerant low-power circuits. However, the MRF-based circuits suffer from a complex structure and the methods which tried to simplify the structure always sacrificed the noise immunity for hardware simplicity. In this paper, we propose a novel MRF-based method for designing efficient and reliable low-power VLSI circuits. For the first time, an innovative reliability boosting mechanism based on maximum conditional correct probability is incorporated into an efficient MRF-based structure which leads to highly reliable circuits with considerably low cost, delay, and power consumption. The proposed method demonstrates the best performance among all of the previously reported methods. Moreover, the Monte Carlo simulations confirm that the proposed method can preserve its superior noise immunity even under serious process, voltage, and temperature variations.     

A graph based approach for reliability analysis of nano-scale VLSI logic circuits

Advances in nano-electronics VLSI manufacturing technology and the rapid downscaling of the size of logic circuits have made them more prone to errors. This has led to the need for fast circuit reliability evaluation of large logic circuits. In this paper a new method for reliability analysis of VLSI logic circuits based on a modified form of Mason’s rule is proposed. Utilizing matrix sparsity significantly increases the speed and reduces the required memory of the proposed approach. In addition, an approach is introduced to mitigate the effect of reconvergent paths. Simulation results indicate that the proposed method is scalable and runs 4× faster than previously proposed schemes.     

Analysis, design, and performance of micropower circuits for a capacitive pressure sensor IC

An integrated circuit has been designed, built, and testing as part of a capacitive pressure transducer. High-accuracy compact micropower circuits utilizing a standard bipolar IC process without any special components or trimming are used. The key circuits for achieving this performance are a Schmitt trigger oscillator and a bandgap voltage reference. The sensor circuits consume 200 /spl mu/W at 3.5 V, can resolve capacitance changes of 300 p.p.m., measure temperature to /spl plusmn/0.1/spl deg/C over a limited temperature range, and presently occupy 4 mm/SUP 2/ on a 2 mm/spl times/6 mm implantable monolithic silicon pressure sensor. Further scaling of the sensor is discussed showing that a reduction of area by a factor of 4 is achievable.     

Statistical analysis of subthreshold leakage current for VLSI circuits

We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.     

Stress analysis of 3-dimensional IC package as function of structural design parameters

Solid Liquid Inter-Diffusion (SLID) is a technology that has recently been utilized to fabricate 3D ICs. Since application of this technology is in its infancy stages, manufacturability and reliability of these bonds are still under heavy investigations. This study presents an elastic-plastic finite element and analytical analyses that were implemented to evaluate effect of package design parameters on thermo-mechanical reliability of the SLID bonds and copper interconnects. A numerical experiment is designed in which several design parameters; die thickness, bond size, underfill stiffness and substrate thickness, are varied in 3 levels. Stress in SLID bonds and in copper interconnects were evaluated using the 3-dimensional finite element analysis as well as an analytical approach. The results show that die and substrate thicknesses are the most influential factors among the selected parameters on stress at the interface and on copper interconnects. Main effect results for stress analysis in SLID bonds using finite element shows that die thickness and underfill stiffness are the most influential factors in defining stress at SLID bonds. Results of the analytical approach confirm the finite element analysis. It is shown that effect of interconnect size and pitch is very small compared to die thickness. In average increasing die thickness increases both shear and peeling stresses at the interfaces and copper interconnects.     

Gate oxide leakage current analysis and reduction for VLSI circuits

In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.     

A simple but efficient analog computer for simulation of high-speed integrated circuits

An analog computer is described which performs transient simulation of nonsaturated transistor circuits with little expense of time. The computer contains models of bipolar transistors and Schottky-barrier diodes as well as variable capacitors and resistors, all realized in plug-in technique. The parameters of the semiconductor devices are directly and continuously adjustable. Therefore, no special knowledge is required to operate the computer. For the display, a dual-trace oscilloscope with low bandwidth is sufficient because the analog time range lies above 0.1 ms. Compared with the digital computer simulation, this analog method has the advantages of lower costs and less simulation time, the latter allowing fast interaction between designer and computer. The good accuracy of the described simulation method is demonstrated by comparing the simulated and the directly measured transient response of an integrated subnanosecond E/SUP 2/CL gate. Also it is shown how the delay time of this gate depends on the transistor parameters.     

A compact model of MOSFET mismatch for circuit design

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 /spl mu/m technology confirm the accuracy of our mismatch model under various bias conditions.     

A Matlab-based modeling and simulation package for electric andhybrid electric vehicle design

This paper discusses a simulation and modeling package developed at Texas A&M University, V-Elph 2.01. V-Elph facilitates in-depth studies of electric vehicle (EV) and hybrid EV (HEV) configurations or energy management strategies through visual programming by creating components as hierarchical subsystems that can be used interchangeably as embedded systems. V-Elph is composed of detailed models of four major types of components: electric motors, internal combustion engines, batteries, and support components that can be integrated to model and simulate drive trains having all electric, series hybrid, and parallel hybrid configurations. V-Elph was written in the Matlab/Simulink graphical simulation language and is portable to most computer platforms. This paper also discusses the methodology for designing vehicle drive trains using the V-Elph package. An EV, a series HEV, a parallel HEV, and a conventional internal combustion engine (ICE) driven drive train have been designed using the simulation package. Simulation results such as fuel consumption, vehicle emissions, and complexity are compared and discussed for each vehicle     

毫米波相控阵封装天线电磁兼容仿真分析与设计

提出了一种毫米波相控阵封装天线的建模方法,通过商业仿真软件搭建了相控阵封装天线集数字、模拟和射频于一体的系统级仿真模型。基于此模型,分析了毫米波相控阵封装天线典型电磁兼容问题机理。此外,提出了相控阵封装天线电磁兼容设计的基本原则。原理样机试验和装机试飞验证了所提出的电磁兼容建模、仿真、分析和设计方法的有效性与正确性。     

A process simulation model for multilayer structures involving polycrystalline silicon

The increasing complexity of VLSI fabrication often requires the use of multilayer structures above the silicon substrate. Electrical and metallurgical properties of multilayer structures have an important effect on circuit performance and reliability. Although process simulation models are available and widely used for computer-aided process design, none of the existing process simulation programs have the capability for modeling multilayer structures. A new model with such capability has been developed and this paper presents the physics as well as the results of simulation supported by experimental data. The model can simulate many desirable properties of multilayer structures involving polycrystalline silicon, such as grain growth, resistivity and oxidation rate of the polysilicon layer, the impurity redistribution across multilayers after high-temperature thermal processing, impurity segregation both at grain boundaries and at interfaces, and the interdependent phenomena of dopant-dependent oxidation/diffusion.