( NH4) 2Sx 溶液改善GaAs MESFETs 击穿特性的机理研究

使用（NH4）2Sx溶液对GaAs MESFETs进行处理。处理后，器件各栅偏压下的源漏饱和电流降低了，栅漏击穿电压有了显著提高。我们认为负电荷表面态影响着栅边缘的电场，负电荷表面态密度的增大会提高器件的击穿电压，这就是（NH4）2Sx溶液处理可改善GaAs MESFET击穿电压的原因。     

Extremely low-noise MESFETs fabricated by metal-organic chemical vapour deposition

Quarter-micron gate low-noise GaAs MESFETs have been developed by delineating gate electrodes by an electron-beam lithography technique and by using high-purity epiwafers prepared by a metal-organic-chemical vapour deposition (MOCVD) technique. At 18 GHz, a noise figure of 1.75 dB with an associated gain of 8.5 dB and a maximum available gain of 11 dB were obtained at drain currents of 10 mA and 30 mA, respectively. This is the lowest noise figure yet reported for low-noise GaAs MESFETs.     

High temperature performance and operation of HFETs

The high temperature performance of Al_0.75Ga_0.25 As/In_0.25Ga_0.75As/GaAs Complementary Heterojunction FETs (CHFETs) is reported between 25 and 500°C. Both experimental and modeled devices have shown acceptable digital characteristics to 400°C. Digital logic circuits have also been shown to operate at temperatures of over 400°C. This strongly suggests that GaAs based devices are capable of satisfying high temperature electronics requirements in the 125-400°C range. Two dimensional physically based modeling has been used to understand the high temperature operation of the HFETs. This work has shown that the devices suffer from gate limited drain leakage currents at elevated ambient temperatures. This off-state leakage current is higher than anticipated. Simulation has shown that, although forward gate leakage currents are reduced with the heterostructure device design, the reverse current is not     

Enhanced CAD model for gate leakage current in heterostructurefield effect transistors

A simple and accurate circuit model for Heterostructure Field Effect Transistors (HFETs) is proposed to simulate both the gate and the drain current characteristics accounting for hot-electron effects on gate current and the effect of the gate current on the channel current. An analytical equation that describes the effective electron temperature is developed in a simple form. This equation is suitable for implementation in circuit simulators. The model describes both the drain and gate currents at high gate bias voltages. It has been implemented in our circuit simulator AIM-Spice, and good agreement between simulated and measured results is achieved for enhancement-mode HFETs fabricated in different laboratories. The proposed equivalent circuit and model equations are applicable to other compound semiconductor FETs, i.e., GaAs MESFETs     

High-breakdown-voltage MESFET with a low-temperature-grown GaAspassivation layer and overlapping gate structure

GaAs MESFETs were fabricated using a low-temperature-grown (LTG) high-resistivity GaAs layer to passivate the doped channel between the gate and source and between the gate and the drain. The gate was fabricated such that the source and drain edges of the metal gate overlapped the LTG GaAs passivation layer. The electric fields at the edges of the gate were reduced by this special combination of LTG GaAs passivation and gate geometry, resulting in a gate-drain breakdown voltage of 42 V. This value is over 60% higher than that of similar MESFETs fabricated without the gate overlap     

Self-aligned GaAs MISFET's with a low-temperature-grown GaAs gateinsulator

GaAs MISFET's with a low-temperature-grown (LTG) GaAs gate insulator and ion-implanted self-aligned source and drain n⁺ regions are demonstrated. The resistivity and breakdown field of the LTG GaAs insulator were not changed appreciably by implantation and 800°C activation annealing. The gate leakage current remained very low at a value of approximately 1 μA per μm² of gate area at 3 V forward gate bias. Because of the reduced source and drain resistance, the drain saturation current and the transconductance of self-aligned MISFET's increased more than twofold after ion implantation     

Light emission in AlGaAs/GaAs HEMTs and GaAs MESFETs induced by hotcarriers

Light emission in submicrometer gate AlGaAs/GaAs HEMTs and GaAs MESFETs has been observed at high drain bias values (>4.0 V). The spectral distribution of the emitted photons in the 1.7-2.9-eV range does not correspond to a simple Maxwellian distribution function of the electron energies in the channel. Light emission is observed in correspondence with nonnegligible gate and substrate hole currents, due to the collection of holes generated by impact ionization     

Reliability studies on GaAs MESFETs fabricated using spin-onplatinum source

GaAs MESFETs were fabricated using a spin-on platinum source as the gate material. They were subsequently aged at 200°C for up to 1000 h. DC electrical characterisation of the MESFETs was carried out during various stages of annealing. The aging behaviour of these MESFETs was compared with those fabricated using conventionally evaporated platinum sources. The results show that the performance of the MESFETs fabricated using a spin-on platinum source is comparable to those of MESFETs fabricated using a conventionally evaporated platinum source     

High-temperature stability of refractory-metal VLSI GaAs MESFETs

Commercially available, self-aligned VLSI GaAs MESFETs, with tungsten-based refractory-metal Schottky gates, nickel-based refractory-metal ohmic contacts, and aluminum interconnection metallization, have been thermally cycled and shown to be stable after 3 h at temperatures up to 500°C. Both partially processed and fully processed wafers were found to be stable with no significant change occurring in either Schottky gate or ohmic contact properties. An increase in the channel resistance component of the series resistance is believed to be responsible for I_DS and g_m degradation above 500°C. The fact that commercially available, gold-free VLSI GaAs MESFETs are able to withstand such thermal cycles has very important consequences for monolithic optoelectronic integrated circuit (OEIC) fabrication because it means that it may now be feasible to grow photonic device heterostructures epitaxially on MESFET VLSI wafers; process them into lasers, modulators, and/or detectors; and interconnect them with the electronics to produce VLSI-density OEICs     

Ion-implanted high microwave power indium phosphide transistors

Encapsulated rapid thermal annealing (RTA) has been used in the fabrication of indium phosphide (InP) power metal-insulator-semiconductor field-effect transistors (MISFETs) with ion-implanted source, drain, and active channel regions. The MISFETs had a gate length of 1.4 μm. Six to ten gate fingers per device, with individual gate finger widths of 100 or 125 μm, were used to make MISFETs with total gate widths of 0.75, 0.8, or 1 mm. The source and drain contact regions and the channel region of the MISFETs were fabricated using silicon implants in semi-insulating InP at energies from 60 to 360 keV with doses from 1×10¹² to 5.6×10¹⁴ cm^-2. The implants were activated using RTA at 700°C for 30 s in N₂ or H₂ ambients using a silicon nitride encapsulant. The high-power, high-efficiency MISFETs were characterized at 9.7 GHz, and the output microwave power density for the RTA conditions used was as high as 2.4 W/mm. For a 1-W input at 9.7 GHz gains up to 3.7 dB were observed, with an associated power-added efficiency of 29%. The output power density was 70% greater than that reported for GaAs MESFETs     

A mechanism of threshold voltage changes for WNx gate GaAs MESFETs in high temperature storage life tests

Reliability of 0.8 μm WN_x gate GaAs MESFETs with a self-aligned lightly doped drain structure has been investigated by means of high temperature storage life tests at 250, 275 and 300 °C. The observed reduction in threshold voltage followed by drain current increase was just reverse in contrast to those for ‘gate sinking’ effect reported on several Au-based gates. The correlation of the threshold voltage reduction with Shottky barrier height and other MESFET parameter changes during the tests suggested a model related to the short channel effect for the threshold voltage reduction, which was proved true by submitting samples of gate lengths 0.7, 1.0 and 1.5 μm to high temperature storage life tests. The dependence of threshold voltage changes on gate orientation relative to the crystal axis was also evaluated with 1.0 μm gate MESFETs to investigate the model in more detail. MESFETs parallel to [001] axis showed minimum absolute threshold voltage changes, while those parallel to piezoelectrically active [011] and [0 1] axes showed decreasing and increasing threshold voltage changes, respectively. From these results, the threshold voltage changes were tentatively ascribed to the relief of the stress caused by poly-imide die bonding process for packaging MESFET chips. In other words, WN_x gate GaAs MESFET chips themselves were concluded to show no appreciable degradation up to 1000 hr storage life tests at 250 and 275 °C, except for ohmic contact degradation at 300 °C.     

Enhanced microwave performance of ion-implanted MESFET with graded GaAs/AlGaAs heterojunctions

Ion-implanted MESFETs have been fabricated on an inverted GaAs/AlGaAs heterostructure. The aluminium concentration in the AlGaAs is graded from 0% at the substrate to 30% at the heterointerface. A maximum extrinsic transconductance of 410 mS/mm is achieved with 0.5 mu m gate devices. This heterojunction ion-implanted FET (HIFET) also exhibits enhanced microwave performance, especially at low drain current, when compared to conventional ion-implanted GaAs MESFETs. At 20% of I/sub dss/, the current gain cutoff frequency f/sub t/ is 40 GHz, which increases up to a maximum value of 47 GHz as the drain current rises. These characteristics of high f/sub t/ and high gain at low current are advantageous for low-noise applications.<>     

Carrier transit delays in nanometer-scale GaAs MESFET's

MESFETs with gate lengths in the range of 40 to 300 nm with GaAs and AlGaAs buffer layers were characterized by high-frequency transit-time measurements. The total carrier transit time is interpreted as being composed of an intrinsic part, a drain delay, and a channel charging delay. The drain field's effect on the geometry of the gate depletion region, and the injection of carriers into the buffer layer are used to describe the origin of these delays and their limiting effect on the high-frequency performance of sub-0.1-μm gate-length MESFETs     

Non-quasi-static transient and small-signal two-dimensionalmodeling of GaAs MESFET's with emphasis on distributed effects

The operation of micron and submicron GaAs MESFETs under high-speed transient and high-frequency small-signal conditions is analyzed using a two-dimensional model. The effects of displacement currents, dipole due to negative differential mobility or current continuity, and two-dimensional transport are emphasized. The origin of delay effects, such as the phase delay incorporated in small-signal models, is explored in order to relate it to the behavior under switching conditions. Broadband expressions for the extraction of a complete small-signal model are presented. Using the expressions derived, the variation of model elements with frequency and the effect of this on the unilateral gain of the device are studied     

Backside copper metallization of GaAs MESFETs using TaN as thediffusion barrier

Backside copper metallization of GaAs MESFETs using TaN as the diffusion barrier was studied. A thin TaN layer of 40 nm was sputtered on the GaAs substrate before copper film metallization, as judged from the data of X-ray diffraction (XRD), Auger electron spectroscopy (AES), and cross-sectional transmission electron microscopy (TEM), the Cu/TaN films with GaAs were very stable without interfacial interaction up to 550°C annealing; the copper metallized MESFETs were thermally stressed at 300°C. The devices showed very little change in the device characteristics (<3%) after thermal stress, and the changes of the electrical parameters and RF characteristics of the devices after thermal stress were of the same order as those devices without Cu metallization, these results show that TaN is a good diffusion barrier for Cu in GaAs devices and the Cu/TaN films can be used for the backside copper metallization of GaAs MESFETs     

High drain current-voltage product of submicrometer-gateion-implanted GaAs MESFET's for millimeter-wave operation

Ion-implanted GaAs MESFETs with gate lengths of 0.3 and 0.5 μm have been fabricated using optical lithography. The devices with 0.3- and 0.5-μm gate lengths exhibit extrinsic transconductances, at zero gate bias, of 200 and 180 mS/mm at drain currents of 400 and 420 mA/mm, respectively. The gate-to-drain diode characteristics of these two different gate-length devices show similar breakdown voltages of 13-15 V. From S-parameter measurements, current-gain cutoff frequencies, f _ts, of 56 and 30 GHz are obtained for 0.3- and 0.5-μm gate-length devices, respectively. The high drain current-voltage product and the microwave performance indicate that ion-implanted technology has the potential to be used to manufacture power devices for millimeter-wave applications     

Experimental and theoretical noise analysis of microwave HEMTs

Low-frequency noise power and high-frequency noise figures in HEMTs (high electron mobility transistors) were measured and compared with calculations based on a one-dimensional noise model to characterize their low-noise properties. It was found that the drain noise current parameter Q in HEMTS is lower than that in GaAs MESFETs. The strong correlation between drain- and induced-gate-noise currents in HEMTs is due to the asymmetric distribution of noise generation along a channel, and the drain noise current is nearly canceled by those induced-gate-noise current. The intrinsic thermal noise from source and gate resistances is about 25% of the total output noise in the 0.25-μm gate-length HEMT considered     

Numerical simulation of the hysteresis in the sidegating effect inGaAs MESFETs-the effect of Schottky contacts

Two-dimensional simulation of the sidegating effect in GaAs MESFETs has been performed. The result confirms that Schottky contacts on semi-insulating substrate cause serious high substrate leakage current and drain current reduction in GaAs MESFETs. The competition between the currents or biases of the contacts is found to be the cause of the S-type negative differential conductivity (S-NDC) or hysteresis observed when measuring the sidegating threshold     

Fabrication and characterization of 4H-SiC planar MESFETs

The planar 4H-SiC MESFETs were fabricated by employing an ion-implantation process instead of a recess gate etching process, which is commonly adapted in compound semiconductor MESFETs, to eliminate potential damage to the gate region during etching process. Excellent ohmic and Schottky contact properties were achieved by using the modified RCA cleaning of 4H-SiC surface and the sacrificial thermal oxide layer. The fabricated MESFETs was also free from drain current instability, which the most of SiC MESFETs have been reported to suffer for the charge trapping. The drain current recovery characteristics were also improved by passivating the surface with a thermal oxide layer and eliminating the charge trapping at the surface. The performance of fabricated MESFETs was characterized by analyzing the small-signal equivalent circuit parameters extracted from the measured parameters.     

An analytical threshold voltage and subthreshold current model forshort-channel MESFETs

Short-channel effects on the subthreshold behavior are modeled in self-aligned gate MESFETs with undoped substrates through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant potential solution, simple and accurate analytical expressions for short-channel threshold voltage, subthreshold swing, and subthreshold drain current are derived. These are then used to develop an expression for minimum acceptable channel length. A comparative study of the short-channel effects in MESFETs with doped and undoped substrates indicates that channel lengths will be limited to 0.15-0.2 μm by subthreshold conduction. Besides offering insight into the device physics of the short-channel effects in MESFETs, the model provides a useful basis for accurate analysis and simulation of small-geometry GaAs MESFET digital circuits