吸收边界条件下含时薛定谔方程的解

The performances of absorbing boundary conditions （ABCs） in four widely used finite difference time domain （FDTD） methods, i.e. explicit, implicit, explicit staggered-time, and Chebyshev methods, for solving the time-dependent Schrodinger equation are assessed and compared. The computation efficiency for each approach is also evaluated. A typical evolution problem of a single Gaussian wave packet is chosen to demonstrate the performances of the four methods combined with ABCs. It is found that ABCs perfectly eliminate reflection in implicit and explicit staggered-time methods. However, small reflection still exists in explicit and Chebyshev methods even though ABCs are applied.     

Flip-chip structure transient thermal model

This paper describes new approach to transient thermal characterization of widely used flip-chip structures. The thermal model is based on the formalization of conjugate problem of heat exchange in the die and the substrate. Accepted provision on linearity of the decision function along the z coordinate allowed building the method characterized by simple programming and temperature calculation in any construction point regardless of previous values and partitioning mesh. The utilization of the mathematical model is illustrated by the example of thermal simulation in the test structure and approved by comparison with the results obtained by thermal–electrical technique.     

Solution of the time-dependent Schr(o)dinger equation with absorbing boundary conditions

The performances of absorbing boundary conditions (ABCs) in four widely used finite difference time domain (FDTD) methods, I.e. Explicit, implicit, explicit staggered-time, and Chebyshev methods, for solving the time-dependent Schr(o)dinger equation are assessed and compared. The computation efficiency for each approach is also evaluated. A typical evolution problem of a single Gaussian wave packet is chosen to demonstrate the perfor-mances of the four methods combined with ABCs. It is found that ABCs perfectly eliminate reflection in implicit and explicit staggered-time methods. However, small reflection still exists in explicit and Chebyshev methods even though ABCs are applied.     

Investigation of smart power DMOS devices under repetitive stress conditions using transient thermal mapping and numerical simulation

Temperature distribution in diced and packaged DMOS devices subjected to repetitive stress is analyzed using transient interferometric mapping (TIM) technique combined with measurements on diode built-in temperature sensors. The effect of DMOS device position on dice, duty cycle and chip ambient temperature on thermal distribution is studied. The TIM experiments and transient temperature measurements are in good agreement with numerical 3D thermal simulations. Failure analysis data after long term pulse stress testing indicate electromigration degradation of the top metal.     

Electrothermal simulation of integrated circuits

This paper describes new techniques for simulating the DC and steady-state thermal characteristics of integrated circuits using the incomplete Choleski conjugate gradient (ICCG) method, and transient electrothermal performance using an efficient macromodeling method based on asymptotic waveform evaluation (AWE). Results on several benchmark circuits show orders of magnitude reductions in CPU time and memory with accuracy comparable to that of the traditional techniques     

Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits

An electrothermal diode model intended for implementation in a SPICE-like simulator is presented. The model is valid in the high current, forward-bias and reverse-breakdown regimes where diodes operate during ESD events. We also present a procedure for extracting the temperature of an SOI diode from an I–V measurement.     

Electrothermal simulation and design of integrated circuits

An accurate prediction of the electrothermal behavior of power integrated devices is required to design circuits in an efficient way. An electrothermal simulator (ETS) is a combination of SPICE with finite element code, in a relaxation procedure. It simulates the full electrothermal behavior of integrated circuits. Static and dynamic simulations of typical examples, reveal the value of ETS for high-power applications. Some specific design rules are derived. They are simple formulas, which estimate the temperature (gradients) on chip. They can be used before any CPU-time consuming simulation takes place which allows a more efficient design and prototype phase     

Static and transient latchup simulation of VLSI-CMOS with an improved physical design model

We are presenting an improved latchup design model for static and transient latchup simulation of VLSI CMOS devices. The model is based on a decomposition of the CMOS structure into a network of analytically described current elements for both majority and minority carriers. Average doping densities and geometrical parameters are the physically based input data. For the modeling of the 2-D majority-carrier flow, transmission-line elements are introduced, especially in the inhomogeneously doped transition region between the substrate and an epitaxial layer. For modeling the transient current behavior, diffusion and space-charge capacitances are used. The model yields very good agreement with measurements both for static and transient triggering modes. Due to the physically reasonable assumptions used in the model equations, the influence of design variations on latchup characteristics can be predicted adequately without new parameter fitting.     

Electrothermal simulation of an IGBT PWM inverter

An electrothermal network simulation methodology is used to analyze the behavior of a full-bridge, pulse-width-modulated (PWM), voltage-source inverter, which uses insulated gate bipolar transistors (IGBTs) as the switching devices. The electrothermal simulations are performed using the Saber circuit simulator and include control logic circuitry, IGBT gate drivers, the physics-based IGBT electrothermal model, and thermal network component models for the power-device silicon chips, packages, and heat sinks. It is shown that the thermal response of the silicon chip determines the IGBT temperature rise during the device switching cycle. The thermal response of the device TO247 package and silicon chip determines the device temperature rise during a single phase of the 60-Hz sinusoidal output. Also, the thermal response of the heat sink determines the device temperature rise during the system startup and after load-impedance changes. It is also shown that the full electrothermal analysis is required to accurately describe the power losses and circuit efficiency     

A lumped transient thermal model for self-heating in MOSFETs

Both static and dynamic effects related to self-heating in MOSFETs (metal-oxide-silicon field effect transistors) are studied in order to construct an adequate compact thermal model. An available 2D electrical device simulator in addition to a simple 2D finite difference code for the heat equation are used as analysis tools. These tools are used both to justify the proposed model topology as well as to extract model parameters. Both static and dynamic effects predicted by the model are compared with existing experimental results.     

Application of the TLM method to transient thermal simulation ofmicrowave power transistors

The transmission line matrix (TLM) explicit method of numerical simulation has been used to model the transient thermal properties of various microwave heterojunction bipolar transistor (HBT's) power structures, used in a pulsed mode. Control of the time step during the simulation is of paramount importance and the paper outlines some of the problems encountered using time step control methods currently published and describes an improved algorithm. This improved time step control method has been implemented in a general purpose 3D TLM transient thermal simulator. Some simulation results are described for a variety HBT transistor structures with very different thermal time constants     

Enhancing reliability with thermal transient testing

Thermal transient measurement, the method for the characterisation of IC packages is gaining increasing importance. The measurement of these transients requires dedicated equipment. The paper discusses the methodology of thermal transient measurements in details, including the compensation of second order effects as non-linearity, non-constant powering etc. In the following part the evaluation methods and algorithmic solutions are discussed. A typical example is presented. Reliability issues are discussed in the last section of the paper, including the problem of die attach testing. The contribution of the thermal transient measurements to the analysis of thermo-mechanical strain is demonstrated.     

Active control of boundary conditions for dynamic thermal characterization of electronic components

This paper presents a practical realization of the system for the active control of boundary conditions during the dynamic thermal characterization of electronic components. The control of boundary conditions is exercised by the dual cold plate cooling assembly equipped with Peltier thermo-electric modules and an appropriate control circuit. Additionally, a tensometer bridge is used to assure the parallel alignment of surfaces and to adjust the contact thermal resistance between particular layers. The operation of the entire control system is illustrated based on a practical example where Peltier module currents are adjusted in real time so as to impose isothermal or constant heat flux boundary conditions on a power diode package surface during measurements performed with time varying power dissipation in the device.     

A novel transient simulation for 3D multilevel interconnections oncomplex topography

An efficient method is presented to model the transient characteristics of distributed resistor-capacitor of ULSI multilevel interconnections on complex topography, in which the reformulation of the boundary-element method (BEM) and the Pade-via-Lanczos (PVL) algorithm associated with multilayer Green's function can avoid the redundant works on both volume mesh and transient analysis associated with the finite-difference method. An adaptive multilayer Green's function is adopted to investigate several cases that have revealed interesting physical mechanisms in charge transfer between conductors on multilayer topography. To improve the timing analysis efficiency of the finite-difference method, the dominant poles are obtained by introducing the PVL algorithm for model-order reduction. Hence, it is easy to calculate the transient characteristics of both parallel conductors and complicated configurations such as crossing lines, corners, contacts, multilayers, and their combinations     

Concise transient SPICE model for bipolar power transistor quasi-saturation simulation

A concise transient SPICE model is presented in this paper to predict both the static and the switching behaviour of power transistors, with emphasis placed on quasi-saturation effects. The model is proposed to simulate both ohmic and non-ohmic quasi-saturation phenomena by automatically adjusting the hole injection ratio term. The model incorporates the currently used Gummel-Poon (GP) model and an additional charge-control relation for the transistor's epitaxial collector. The turn-off charge removal phenomenon is not modelled specifically; however, the charge-control equation for the epitaxial collector region may partly simulate this effect where the quasi-saturation region is entered. The validity of the model is verified by comparison between the original SPICE bipolar junction transistor model and experimental data for both DC and turn-on conditions. Methods for determining the model parameters are described.