双频段接收机中的BiFET低噪声放大器

设计了一种采用BiFET结构的低噪声放大器（LNA）,这种结构通过BiCMOS工艺使低噪声放大电路集合了双极型晶体管的低噪声特性和CMOS晶体管的高线性度。应用优化的BiFET Cascode共源共栅结构能够明显地提高低噪声放大器的性能,并且能应用于两个不同频率。本文设计的低噪声放大器在低偏置电流（1．7mA）和低功耗（5．7mW）的情况下能取得1．69dB的噪声系数、15．96dB的电压增益、一8．5dBm的IIP3和-67dB的反向隔离。设计的BiFET低噪声放大器是采用了AMS0．8μm的BiCMOS混合信号工艺,经过优化可以用于工业、室内的远程无线控制系统包括无线门禁系统。     

基于65 nm CMOS工艺的小型化高增益低噪声放大器设计

基于65 nm互补金属氧化物半导体（Complementary Metal Oxide Semiconductor,CMOS）工艺研制了一款用于X波段的小型化高增益低噪声放大器（Low Noise Amplifier,LNA）.通过研究晶体管尺寸和偏置电压对噪声系数和增益性能的影响，确定了低噪声高增益情况下晶体管尺寸和偏置电压的取值.针对LNA的输入、输出和级间匹配，采用变压器匹配网络，使得LNA尺寸缩小至0.33 mm×0.73 mm，同时提高了电路的隔离度.在变压器中嵌入并联电容，降低了变压器的耦合系数.基于差分共源拓扑结构，引入中和电容技术，有效地抑制了晶体管栅-漏间寄生电容引起的米勒效应，提高了LNA的增益和稳定性.测试结果表明，在1 V电源电压下，该LNA的带内最大增益为22.9 dB，最小噪声系数为2.8 dB，功耗为49 mW.在射频收发系统中，本款LNA具有良好的应用前景.     

ADS下CMOS低噪声放大器的设计优化

运用仿真工具ADS,通过对CMOS共源共栅低噪声放大器的共源级栅宽,源级电感以及栅极电感值的扫描仿真,以Smith阻抗圆图的形式给出了一个直观的LNA设计优化流程,近似实现了最佳噪声源阻抗和输入阻抗的同时匹配.按照该方法设计的基于0.18 μm CMOS工艺,工作在1.58 GHz的低噪声放大器,其噪声系数为1.3 dB,S11为-28.4 dB,功耗为3.42 mW,从而很好地证实了该方法的可行性.     

基于ADS的C波段的低噪声放大器仿真设计研究

低噪声放大器是接收机中最重要的模块之一,文中采用了低噪声、较高关联增益、PHEMT技术设计的ATF-35176晶体管,设计了一种应用于5.5～6.5 GHz频段的低噪声放大器。为了获得较高的增益,该电路采用三级级联放大结构形式,并通过ADS软件对电路的增益、噪声系数、驻波比、稳定系数等特性进行了研究设计,最终得到LNA在该频段内增益大于32.8 dB,噪声小于1.5 dB,输入输出驻波比小于2,达到设计指标。     

5.8GHz低噪声放大器的设计与优化

设计了一种低压、低功耗、输出阻抗匹配稳定的CMOS差分低噪声放大器.基于源极电感负反馈共源共栅结构,提出了基于MOS管中等反型区最小化Vdd·Id的方法,以优化功耗.在共栅晶体管处并联正反馈电容,以提升电路增益.对电路的噪声系数、输出阻抗稳定性、芯片面积等也进行了优化.仿真结果表明,当电源电压为1V,工作频率为5.8 GHz时,设计的低噪声放大器的噪声系数为1.53 dB,输入回波损耗为-22.4 dB,输出回波损耗为-24.6 dB,功率增益为19.2dB,直流功耗为4.6 mW.     

低功耗CMOS低噪声放大器的分析与设计

基于TSMC 0.18μm CMOS工艺,设计了一种低功耗约束下的CMOS低噪声放大器。与传统的共源共栅结构相比,该电路在共源晶体管的栅源间并联一个电容,以优化噪声;并引入一个电感,与级间寄生电容谐振,以提高增益;通过减小晶体管的尺寸,实现了低功耗。模拟结果表明,在2.45 GHz工作频率下,增益大于14 dB,噪声系数小于1 dB,直流功耗小于2 mW。     

一款应用于GPS的CMOS低功耗高增益LNA

针对当前应用于GPS射频前端的LNA存在的不足,设计了一种新型的LNA.从电路结构、噪声匹配、线性度、阻抗匹配、电压增益以及功耗等方面详细讨论了该低噪声放大器的设计.电路采用CMOS 0.18μm工艺实现,经过测试,低噪声放大器的增益为40.8dB,噪声系数为0.525dB,PldB为-29.5dBm,1.8V电压下的消耗电流仅为1.4mA.电路性能充分满足应用要求.     

一种3.1~10.6GHz超宽带低噪声放大器设计

设计了一种基于TSMC 0.13μm CMOS工艺,用于3.1～10.6GHz带宽的CMOS低噪声放大器。输入级采用共栅极结构,在宽频带内能较好地完成输入匹配。放大级采用共源共栅结构,为整个电路提供合适的增益。输出则采用源极输出器来进行输出匹配。使用ADS2006软件进行设计、优化和仿真。仿真结果显示,在3.1GHz～10.6GHz带宽内,放大器的电源电压在1.2V时,噪声系数低于2.5dB,增益为20.5dB,整个电路功耗为8mW。     

基于CMOS工艺的一种低功耗高增益低噪声放大器

采用0．18μm CMOS工艺,两级共源结构实现了低功耗高增益的低噪声放大器（LNA）设计。共源结构的级联采用电流共享技术,从而达到低功耗的目的。电路的输入端采用源极电感负反馈实现50欧姆阻抗匹配。同时两级共源电路之间通过串联谐振相级联。该LNA工作在5．2GHz,1.8V电源电压,能提供20dB的增益（S21为20dB）,而噪声系数为1．9dB,输入匹配较好,S11为-32dB。     

短沟道下共栅结构宽带CMOS LNA的设计

基于短沟道MOS器件的过量因子随沟道长度降低缓慢增加的特征,研究了短沟道下共栅结构宽带低噪声放大器的噪声性能,并在0.18μm CMOS工艺下设计实现了共栅结构的宽带低噪声放大器.流片测试结果表明,在1.8 V电源电压、4.1 mA工作电流下,该系统获得6.1 dB的最小噪声系数;综合性能与长沟道下相近,符合理论分析和设计要求.     

Wide-band CMOS cascode low-noise amplifier design based on source degeneration topology

A design methodology for a wide-band CMOS low noise amplifier (LNA) with source degeneration is presented. By allowing an arbitrary source degeneration and employing a general input matching network, the proposed wide-band CMOS LNA can be shown for any choice of transistor width to achieve the minimum noise figure at all frequencies of interest. The transistor width simply affects the gain of the LNA at the cost of power dissipation. These results apply uniquely to CMOS LNAs, as they are derived from a quasi-static MOSFET model. To validate these design concepts, a wide-band LNA was realized in 0.25-/spl mu/m CMOS technology. The measured noise figure ranges from 2.7 to 3.7 dB over 3.2-4.8 GHz with power consumption of 20 mW. A close agreement with the theoretical results is observed.     

Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA

A typical common source cascode low-noise amplifier (CS-LNA) can be treated as a CS-CG two stage amplifier. In the published literature, an inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. In this work, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential cascode CS-LNA. It uses a smaller noise reduction inductor compared with the conventional inductor based technique. It can reduce the noise, improve the linearity and also increase the voltage gain of the LNA. The proposed technique is theoretically formulated. Furthermore, as a proof of concept, a 2.2 GHz inductively degenerated CS-LNA was fabricated using TSMC 0.35 mum CMOS technology. The resulting LNA achieves 1.92 dB noise figure, 8.4 dB power gain, better than 13 dB S11, more than 30 dB isolation (S12), and -2.55 dBm IIP3, with the core fully differential LNA consuming 9 mA from a 1.8 V power supply.     

A Systematical Approach for Noise in CMOS LNA

A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5.2GHz CMOS LNA.     

CMOS低噪声放大器中噪声的系统研究方法

采用系统研究方法来分析包括MOS器件的沟道噪声和感应栅噪声在内的CMOS低噪声放大器中的噪声,并提出了一个新的噪声系数解析式.基于此解析式,讨论了分布栅电阻和内部沟道电阻对噪声性能的影响.对噪声性能进行了两种不同的优化,并应用于5.2GHz CMOS低噪声放大器的设计.     

3.6~4.7GHz低噪声放大器

以一种经典的窄带低噪声放大器结构为基础,分析级联放大器的S参数,通过优化元件参数,获得了一种在3.6~4.7 GH z范围内具有低输入回波损耗、低噪声系数的放大器。采用标准的0.18μm RF CM O S工艺进行了设计和实现。芯片面积为0.6 mm×1.5 mm。测试结果表明:在3.6~4.7 GH z的范围内,该宽带低噪声放大器输入回波损耗小于-14 dB;噪声系数小于2.8 dB,增益大于10 dB。在1.8 V电源下功耗约为45 mW。     

Parasitic-aware analytical modeling of integrated CMOS inductively degenerated narrow-band low noise amplifiers

In this paper, we present an analytical modeling methodology for fully integrated inductively-degenerated CMOS narrow-band cascode Low Noise Amplifiers (LNA) that captures short channel transistor effects to enable rapid design space exploration in current and future process technologies. The modeling methodology captures the impact of parasitics on passive components, ESD-protection structures, and devices to accurately predict both impedance matching and noise figure. Our modeling is suitable for numerical optimization and fully automated synthesis for LNAs. The results indicate that the methodology models ESD-protected LNA circuits with 47.9% better accuracy in noise figure when compared with several current analytical modeling techniques with four orders of magnitude improvement in simulation time over circuit-level simulation. Given its speed and accuracy, the analytical modeling methodology is well-suited for design space exploration.     

Sub-0.2 dB Noise Figure Wideband Room-Temperature CMOS LNA With Non-50 Ω Signal-Source Impedance

This paper presents a wideband low-noise amplifier (LNA) designed to be used as the first stage of the receiver in the Square Kilometer Array radio telescope. The LNA design procedure and its layout features are discussed. The noise figure optimization procedure determines the signal-source resistance that results in reduced noise figure. When used in the radio telescope, the required signal-source resistance will be presented by the telescope custom-made antenna elements. The LNA, designed in 90 nm bulk CMOS, achieves sub-0.2 dB noise figure from 800 MHz to 1400 MHz, return loss of more than 11 dB, gain of more than 17 dB driven into a 50 load, output 1 dB compression point of 2 dBm, output IP3 of 12 dBm, and output IP2 of 22 dBm while consuming 43 mA from a 1 V supply. In the LNA implementation presented in this paper the load choke inductor and the source inductor are integrated whereas the gate-, bias-, and the choke-inductor between two transistors of the cascode are external. The noise figure of the presented LNA is to our knowledge the lowest noise figure achieved by a power matched wideband CMOS LNA at room temperature.     

Optimum Design for a Low Noise Amplifier in S-Band

An optimum design of a low noise amplifier （LNA） in S-band working at 2-4 GHz is described. Choosing FHC40LG high electronic mobility transistor （HEMT）, the noise figure of the designed amplifier simulated by Microwave Office is no more than 1.5 dB, meanwhile the gain is no less than 20 dB in the given bandwidth. The simulated results agree with the performance of the transistor itself well in consideration of its own minimum noise figure （0.3 dB） and associated gain （15.5 dB）. Simultaneously, the stability factor of the designed amplifier is no less than 1 in the given bandwidth.