Circuit techniques for 1.5-V power supply flash memory

We describe circuit techniques for a Flash memory which operates with a V_DD of 1.5 V. For the interface between the peripheral circuits and the memory core circuits, two types of level shifter circuits are proposed which convert a V_DD level signal into the high voltage signals needed for high performance. In order to improve the read performance at a low V_DD, a new self-bias bitline voltage sensing scheme is described. This circuit greatly reduces the delay's dependence on bitline capacitance and achieves 19 ns reduction of the sense delay at low voltages. Multilevel storage sensing with this circuit is also discussed     

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations

We have developed a circuit for determining an optimal supply voltage, V_OPT, for which energy consumption will be minimized in devices suffering from high-leakage. This V_OPT is determined on the basis of a trade-off between power consumption and operation time. Experimental results with a 90-nm CMOS device indicate that the proposed circuit successfully determines V_OPT with high accuracy. V_OPT operations with power gating at 40 MHz, and where V_DD = 0.67 V, results in an energy reduction of 52.8% over that achieved with DVFS alone at 5 MHz (1/20 of maximum operational frequency). Further, we propose a scheme for suppressing determination error, one that results in voltage error of less than 50 mV.     

Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers

This brief proposes lower power lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of PT², the proposed scheme can lead to either a power dissipation reduction of about 70% while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively, in 65-nm technology with V_DD = 1 V, minimum size gate capacitance, C_g = 1.5 fF, and minimum size output capacitance, C_o = 1 fF. Closed-form expressions that give the optimum threshold voltage and number of stages are presented.     

Low Power and High Speed Multi Threshold Voltage Interface Circuits

Employing multiple supply voltages (multi- V_DD) is an effective technique for reducing the power consumption without sacrificing speed in an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-V_th) level converters are proposed in this paper. The new multi-V_th level converters are compared with the previously published circuits for operation at different supply voltages. When the circuits are individually optimized for minimum power consumption, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, the speed is enhanced by up to 78% with the proposed voltage interface circuits in a 0.18- mum TSMC CMOS technology.     

Half-swing clocking scheme for 75% power saving in clockingcircuitry

We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half V_DD by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 μm CMOS technology, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation     

Circuit techniques for a 1.8-V-only NAND flash memory

Focusing on internal high-voltage (V_pp) switching and generation for low-voltage NAND flash memories, this paper describes a V _(pp) switch, row decoder, and charge-pump circuit. The proposed nMOS V_pp switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the V _pp leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed V_pp switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and V_pp switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 μA. The proposed pump scheme reduced the area required for charge-pump circuits by 40%     

High-efficiency dual transistor base drive circuit based on the Cukconverter topology

A dual transistor base drive circuit that unifies all important functions (on-state base current power supply for two power transistors, off-state negative U_be =-5 V base-emitter voltage, overcurrent and short-circuit protection scheme based on saturation voltage, and on- and off-state monitoring circuits) is described. The unit provides two base drive outputs using a single switching converter. It can be used to control two individual power transistors in different inverter configurations, e.g. common emitter or bridge configuration. The concept of a dual transistor base drive circuit using the Cuk switching regulator topology enables the low volume construction of a high-efficiency base drive unit for a high-power transistor inverter bridge leg. The circuit is powered from a common DC rail. The base current waveforms are characterized by steep slopes and an overcurrent peak at turn on     

Leakage Biased pMOS Sleep Switch Dynamic Circuits

In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits. pMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology     

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V_TH) of the transistors is reduced for high performance at low power-supply voltage (V_DD). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-μA bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V_TH, and keeps the V_TH and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-μm CMOS technology, which demonstrates the effectiveness of the scheme     

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V_CC voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 μm² crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 μm electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs     

Full-swing Schottky BiCMOS/BiNMOS and the effects of operatingfrequency and supply voltage scaling

Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than V_DD. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 μm BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits     

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The sleep switch circuit technique significantly reduces the subthreshold leakage energy as compared to both standard low-threshold voltage and dual threshold voltage domino logic circuits. A domino adder enters and leaves a low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods.     

Highly doped InGaP/InGaAs/GaAs pseudomorphic HEMT's with 0.35 μmgates

We fabricated 0.35-μm gate-length pseudomorphic HEMT DCFL circuits using a highly doped thin InGaP layer as the electron supply layer. The InGaP/InGaAs/GaAs pseudomorphic HEMT grown by MOVPE is suitable for short gate-length devices with a low supply voltage since it does not show short channel effects even for gate length down to 0.35 μm. We obtained a K value of 555 mS/Vmm and a transconductance g_m of 380 mS/mm for an InGaP layer 18.5 nm thick. Fabricated 51-stage ring oscillators show the basic propagation delay of 11 ps and the power-delay product of 7.3 fJ at supply voltage of V_DD of 1 V, and 13.8 ps and 3.2 fJ at V_DD of 0.6 V for gates 10 μm wide     

Two-dimensional power-line selection scheme for lowsubthreshold-current multi-gigabit DRAM's

A two-dimensional power-line selection scheme for an iterative CMOS circuit block is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks in a two-dimensional arrangement and selectively energized by two-dimensional power-line selection. It is shown to be suitable for dual word-line structure, particularly because of its single sub-word line activation. This scheme achieves a very large reduction of active current to one sixteenth, from 116 mA to 22 mA for a 1-V 16-Gb DRAM with dual word-line structure, while maintaining a speed comparable to existing multi-megabit DRAM's. The proposed scheme is promising for reducing the active power of future multi-gigabit DRAM's     

Power factor correction converter using delay control

A low cost universal input voltage single-controller power factor correction converter for a 200 W power supply is proposed. It consists of the PFC part followed by a DC-DC converter as in a conventional two-stage scheme. However a single PWM controller is used as in a single-stage PFC scheme. The switch in the PFC part is synchronized with the switch in the DC-DC converter and has a fixed frequency. Employing an adaptive delay scheme, the PPC switch is controlled to limit the capacitor voltage within a desired range for optimum efficiency and to reduce input current harmonic distortion. The design procedures of the delay scheme, the feedback loop, and experimented results are presented to verify the performance     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

A Low-Power SRAM Using Bit-Line Charge-Recycling

Low-power SRAM design is crucial since it takes a large fraction of total power and die area in high-performance processors. Reducing voltage swing of the bit-line is an effective way to save the power dissipation in write cycles. Voltage swing reduction of bit-lines is, however, limited due to possible write-failures. We propose a new low-power SRAM using bit-line charge recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance, instead of the power line. Applying such a charge recycling technique to the bit-line significantly reduces write power. A test chip with 32 Kbits (256 rows x 128 columns) is fabricated and measured in 0.13 mum CMOS to demonstrate operation of the proposed SRAM. Measurement results show 88% reduction in total power during write cycles compared to the conventional SRAM (CON-SRAM) at V_DD = 1.5 V and f = 100 MHz.     

A new control scheme for single-phase PWM multilevel rectifier withpower-factor correction

A new control scheme for a single-phase bridge rectifier with three-level pulsewidth modulation is proposed to achieve high power factor and low current distortion. The main circuit consists of a diode-bridge rectifier, a boost inductor, two AC power switches, and two capacitors. According to the proposed control scheme based on a voltage comparator and hysteresis current control technique, the output capacitor voltages are balanced and the line current will follow the supply current command. The supply current command is derived from a DC-link voltage regulator and an output power estimator. The major advantage of using a three-level rectifier is that the blocking voltage of each AC power device is clamping to half of the DC-link voltage and the generated harmonics of the three-level rectifier are less than those of the conventional two-level rectifier. There are five voltage levels (0, ±V_DC/2, ±V_DC) on the AC side of the diode rectifier. The high power factor and low harmonic currents at the input of the rectifier are verified by software simulations and experimental tests     

High-Temperature Operation of AlGaN/GaN HEMTs Direct-Coupled FET Logic (DCFL) Integrated Circuits

This letter presents the high-temperature performance of AlGaN/GaN HEMT direct-coupled FET logic (DCFL) integrated circuits. At 375 degC, enhancement-mode (E-mode) AlGaN/GaN HEMTs which are used as drivers in DCFL circuits exhibit proper E-mode operation with a threshold voltage (V_TH) of 0.24 V and a peak current density of 56 mA/mm. The monolithically integrated E/D-mode AlGaN/GaN HEMTs DCFL circuits deliver stable operations at 375 degC: An E/D-HEMT inverter with a drive/load ratio of 10 exhibits 0.1 V for logic-low noise margin (NM_L) and 0.3 V for logic-high-noise margin (NM_H) at a supply voltage (V_DD) of 3.0 V; a 17-stage ring oscillator exhibits a maximum oscillation frequency of 66 MHz, corresponding to a minimum propagation delay ( tau_pd) of 446 ps/stage at V_DD of 3.0 V     

Low-power on-chip supply voltage conversion scheme forultrahigh-density DRAMs

In order to achieve 3.3-V 1-Gb DRAM and beyond, a new on-chip supply voltage conversion scheme that converts 3.3-V external supply voltage, V_ext, to lowered 1.5-V internal supply voltage, V_ent, without any power loss within the voltage converter is proposed. This scheme connects two identical DRAM circuits in series between V_ixt and V_ss. By operation of two DRAM circuits with the same clock timing, the voltage between two DRAMs, V_int, is automatically fixed to 1/2V_ext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2V_ext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAMs. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty