ULSI中的铜互连线RC延迟

随着ULSI向深亚微米特征尺寸发展，互连引线成为ULSI向更高性能发展的主要限制因素。由互连引线引起的串扰噪音及RC延迟限制了ULSI的频率性能的提高，同时考虑到电迁移和功率损耗，人们开始寻找新的互连材料；低电阻率的铜互连材料和低介电常数介质的结合可以有效地发送互连线的性能，主要讨论了互连延迟的重要性以及发送和计算延迟的方法。     

低介电常数(low-k)介质在ULSI中的应用前景

本文讨论了ULSI的发展对低介电常数(low-k)介质的需求,介绍了几种有实用价值的low-k介质的研究和发展现况,最后评述了low-k介质在ULSI中应用的前景.     

低k绝缘层及其设备

铜互连、金属间低k绝缘层(k<3)和CMP工艺已成为制造高端IC的一个标准工艺。本文介绍了厚度已步入纳米尺度的低k绝缘层的最新研究动态和当前几种常用低k绝缘层材料,如FOx低k旋涂材料、黑金刚石系列低k薄膜和CORAL低k材料等。另外,还介绍了有关低k绝缘层材料的几种设备,如生长设备、蚀刻设备和低kCMP设备。     

碱性抛光液在CMP过程中对低k介质的影响

以p型111硅片为衬底,经过旋涂固化制备低介电常数(低k)材料聚酰亚胺。经过化学机械抛光(CMP)过程,考察实验前后低k材料介电性能的变化。实验中分别使用阻挡层抛光液、Cu抛光液以及新型抛光液对低k材料进行抛光后,利用电参数仪对低k材料进行电性能测试。结果显示,低k材料介电常数经pH值为7.09新型抛光液抛光后,k值由2.8变为2.895,漏电流在3.35 pA以下,去除速率为59 nm/min。经新型抛光液抛光后的低k材料,在电学性能等方面均优于阻挡层抛光液和Cu抛光液,抛光后的低k材料的性能能够满足应用要求。     

集成电路片内铜互连技术的发展

论述了铜互连取代铝互连的主要考虑,介绍了铜及其合金的淀积、铜图形化方法、以及铜与低介电常数材料的集成等。综述了ULSI片内铜互连技术的发展现状。     

0.18μm以下低k介质材料上的低离子等离子体去胶工艺

本文论述了下游式等离子体在多种Cu／低k材料上去胶及去残留物的工艺应用，主要有3类低k材料的实验数据——有机类、掺氮氧化物和多孔性低k材料，同时论述了在这些对应低k材料上新的等离子体气氛：(1)中性等离子体；(2)无氧和还原性等离子体；(3)无氧和无氮等离子体。     

ULSI低介电常数材料制备中的CVD技术

综述了制备ULSI低介电常数材料的各种CVD技术。详细介绍了PCVD技术淀积含氟氧化硅薄膜、含氟无定型碳膜与聚酰亚胺类薄膜的工艺,简要介绍了APCVD技术淀积聚对二甲苯类有机薄膜及RTCVD技术淀积SiOF薄膜的工艺。     

MOS晶体管技术

简要回顾MOS晶体管一些具有代表性的技术进展,分析了其在将来超大规模集成电路(ULSI)应用中的主要限制.从材料以及器件结构两个方向分别阐述了突破现有MOS技术而最有希望被将来ULSI工业所采用的新型晶体管技术.     

Forouhi-Bloomer离散方程在低k材料光学表征上的应用

半导体工艺中对低k介质材料的精确表征是工艺监控的重要环节,传统方法如扫描电子显微镜和透射电子显微镜存在耗时长和破坏性等缺点。使用一种结合了Forouhi-Bloomer离散方程组和宽光谱分光光度法的新方法,对低k薄膜进行光学表征,得到薄膜的折射率n、消光系数k和膜厚d,并将结果与椭偏仪的测量进行比较,证明了使用F-B方程在半导体工艺中精确表征低k材料的能力和这种方法快速无损的优点。     

纳米晶存储特性的研究

常温下硅纳米晶构成的MOSFET存储器具有低压、低功耗、体积小、高剂量和快速读写等优良特性,在ULSI中有重要的应用前景.它是当前ULSI研究中的一项热门专题,在国外一些著名刊物上屡见报道.本文介绍了这种器件的存储特性及其机理与最新研究进展.     

Materials' impact on interconnect process technology and reliability

We explain how the manufacturing technology and reliability for advanced interconnects is impacted by the choice of metallization and interlayer dielectric (ILD) materials. The replacement of aluminum alloys by copper, as the metal of choice at the 130-nm technology node, mandated notable changes in integration, metallization, and patterning technologies. Those changes directly impacted the reliability performance of the interconnect system. Although further improvement in interconnect performance is being pursued through utilizing progressively lower dielectric constant (low-k) ILD materials from one technology node to another, the inherent weak mechanical strength of low-k ILDs and the potential for degradation in the dielectric constant during processing pose serious challenges to the implementation of such materials in high-volume manufacturing. We consider the cases of two ILD materials, carbon-doped silicon dioxide and low-k spin-on-polymer, to illustrate the impact of the ILD choice on the process technology and reliability of copper interconnects.     

灵敏低k材料与铜兼容的去胶机

一种成功的抗蚀剂和刻蚀残渣去除胶机必须满足大批量IC制造环境中可接受的3个条件:(1)与灵敏低K介质材料的兼容性;(2)去除抗蚀剂和刻蚀残渣;(3)与基质金属包括铜、钴、钨等金属的兼容性。而AirProdul公司的EZ系列去胶机成功地满足了这些要求。一些含氟化物的产品与灵敏的低k介质,例如多孔的低k材料、HSQ和其它超低k材料是能够很好共处的。对由测量刻蚀速率以及键合保留物和暴露于这些除胶机的覆盖膜组成的介质材料确定的兼容性进行了评价,并对作图衬底的浸泡试验所确定的清洗效力也一并进行了评价。     

低压力Cu布线CMP速率的研究

采用低介电常数材料(低k介质)作为Cu布线中的介质层,已经成为集成电路技术发展的必然趋势.由于低k介质的低耐压性,加工的机械强度必须降低,这对传统化学机械抛光(CMP)工艺提出了挑战.通过对CMP过程的机理分析,提出了影响低机械强度下Cu布线CMP速率的主要因素,详细分析了CMP过程中磨料体积分数、氧化剂体积分数、FA/O螯合剂体积分数等参数对去除速率的影响.在4.33 kPa的低压下通过实验得出,在磨料体积分数为20%,氧化剂体积分数为3%,FA/O螯合剂体积分数为1.5%时可以获得最佳的去除速率及良好的速率一致性.     

Analysis of thermal stresses in copper interconnect/low-k dielectric structures

Numerical simulations of thermal stresses in copper (Cu) interconnect and low-k dielectric systems are carried out. The three-dimensional (3-D) finite-element analysis assumes a two-level metal structure connected by a via. Mechanical deformation is generated by thermal expansion mismatches during cooling and cyclic temperature changes. The thin barrier/etch stop layers, as well as oxide or polymer-based low-k dielectric materials, are all taken into account in the model. The stress and deformation fields are examined in detail; salient features having direct implications in device reliability are illustrated with representative contour plots. It is found that the use of low-k material in place of traditional oxide dielectric significantly reduces the triaxial tensile stresses in Cu but enhances plastic deformation, especially in the via region. The compliant low-k material causes the thin barrier layers to bear very high stresses. Deformation in the Cu line and via structure is more affected by the thermal expansion property of the dielectric, but the stresses in the barrier layers are more influenced by the elastic modulus of the dielectric.     

TEM样品制备辅助研究介质层可靠性失效机理

研究了TEM样品制备条件对Cu/低k制程ILD TDDB失效样品及含更低介电常数(k=2.7)介质层样品的TEM成像质量的影响,发现在一定的样品制备条件下低介电常数介质的疏松特性可在TEM成像时得到增强显示,进而揭示了某Cu/低k制程ILD TDDB可靠性失效样品的失效机理为芯片制造过程中介质层沉积温度异常导致其疏松特性增强,介电常数降低,从而导致其电绝缘性能下降而引起TDDB可靠性测试项目失效.     

超低k介质材料低损伤等离子体去胶工艺进展

介绍了三类常见的低k介质材料,并对空气隙(k=1)的发展进行了探讨;讨论了引起等离子体损伤的机理和传统的O2等离子体去胶工艺面临的困难;最后综述了近年来国际上提出的低损伤等离子体去胶工艺的研究进展。人们已经开发出一些对低k材料进行硅化处理的工艺,可以部分修复在刻蚀和去胶处理过程中被消耗掉的有机官能团。基于金属硬掩膜层和新型等离子体化学的集成方案将会展示出颇具前景的结果。     

VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices

Low-voltage low-power nonvolatile floating-gate memory device operation can be achieved by using alternative tunnel barriers consisting of at least two dielectric layers with different dielectric constants k. Low-k/high-k (asymmetric) and low-k/high-k/low-k (symmetric) barriers enable steeper tunneling current-voltage characteristics. Their implementation is possible with high-k dielectric materials that are currently investigated for SiO/sub 2/ replacement in sub-100-nm CMOS technologies. We show that a reduction in programming voltages of up to 50% can be achieved. This would significantly reduce the circuitry required to generate the high voltages on a nonvolatile memory chip, while maintaining sufficient performance and reliability.     

Effect of in-line electron beam treatment on the electrical performance of Cu/organic low-k damascene interconnects

The interface quality and reliability issues have shown significant importance in Cu/organic low-k damascene integration. In this letter, a post-etch in-line electron beam (E-beam) treatment was used to modify the interface properties of sidewall barrier/organic low-k dielectric without impairing either the film properties or the dielectric constant. X-ray photoelectron spectroscopy (XPS) analysis indicated that oxygen content at the low-k surface, which mostly came from oxygen/moisture intake from ambient during process, was eliminated by E-beam exposure and subsequent rapid thermal annealing. As a result, Cu/organic low-k interconnects exhibited a lower line-to-line leakage current and a higher breakdown strength. The interconnect structures, after this in-line E-beam treatment process, also showed a good reliability performance against thermal stress, with good leakage current characteristics after a 500-h burn-in at 200/spl deg/C.