Technology transfer between VLSI design and software engineering: CAD tools and design methodologies

Recent research on the explicit transfer of technology used in computer-aided design (CAD) tools and design methodologies is reported. First, several examples are given of applications of these technologies to software engineering. Then, three research projects are described which focused on applying software engineering principles to the VLSI design process. They are: a methodology, language, and assessment tool for multilevel mixed-mode VLSI designs; a research project that explored the potential for transfer of software design methodologies for managing VLSI design complexity; and a specification technique for "modules" in a VLSI design that localizes the impact of changes to the design. Next, a CAD tool and design methodology are described which consider the design of software and hardware together, and apply common techniques to both. Finally, some observations are made on the appropriateness of technology transfer between VLSI design and software engineering.     

Enhanced analog “yields” cost-effective systems-on-chip

As device feature sizes of analog MOS circuits are reduced to the deep-submicron ranges, the effect of process variability on circuit performance and reliability is magnified. Yield is becoming more and more critical and statistical methods are required to simulate the effect of process variability to enable circuit designers to “design-in” quality through circuit robustness. More work is needed particularly in the areas of modeling and statistical CAD of submicron, low-voltage mixed-signal ICs. The characterization work needed to tune models to specific VLSI technology, implementation into the SPICE and APLAC simulators, and use in design and optimization of analog and digital VLSI circuits     

Computer-aided design of VLSI circuits

With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have exist and no truly integrated computer-aided desisn (CAD) systems exist for the design of IC's. A structured approach both to circuit desisn and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of IC's, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requites an evolution from these techniques and design methods.     

An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I²L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (leq 2 microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n⁺buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

CAD systems for VLSI in Japan

With the advent of the VLSI era, computer-aided design (CAD) is increasing its importance, and much effort is now being expended on CAD by many IC manufacturers and laboratories in Japan. This paper reviews the historical aspect of the CAD systems developed in this field, and describes the current status of VLSI CAD systems and technologies, from device to system levels, in Japan. The CAD development activities for IC's were initiated in the late 1960's. At present, VLSI CAD systems and related CAD technologies in Japan seem to be in the adolescent stage-partly capable of practical use and partly still in the immature state.     

The impact of supercomputers on IC technology development and design

Very large scale integration (VLSI) has evolved at an enormous rate, progressing from hundreds of components on an integrated circuit (IC) in the 1960's to a million components on a chip in the foreseeable future. This paper reviews some of the computer-aided design (CAD) tools that are essential for VLSI technology development and circuit design and that also require large amounts of computer resources. Specifically, we describe programs for process simulation, device simulation, and circuit simulation. This paper also reviews the impact of high-performance computing facilities on the development and use of these programs at AT & T Bell Laboratories.     

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

Quadruply self-aligned MOS (QSA MOS)—A new short-channel high-speed high-density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually self-aligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for high conductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F × 2F cell (6 µm²/cell, namely 3 × 2 mm²/1 Mbit in 1-µm rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)     

Quadruply Self-Aligned MOS (QSA MOS) -- A New Short-Channel High-Speed High-Density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually selfaligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for highconductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F X 2F cell (6 /spl mu/m/sup 2//cell, namely 3 X 2 mm/sup 2//1 Mbit in 1-/spl mu/m rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)     

Study of the methods of calibration of the process OPC VT-5 models with a variable threshold

One of the most widely used approaches to simulation of complex lithographic systems is considered. The approach makes it possible to take into account the effect of the features of the manufacturing process on the transfer of very large-scale integration (VLSI) topology to a silicon wafer. The approach is based on the present-day aids for simulation and computer-aided design (CAD) of VLSI circuits and provides a means for reducing errors (that arise from the imperfection of the manufacturing process) in transferring the design onto the silicon wafer. A family of empirical VT-5 mathematical models involving a variable threshold is analyzed. The models are used in the CAD Calibre, Mentor Graphics Ltd. The results of calibration and verification of the process model for a polysilicon layer produced by the technology of Department of Microtechnology (DMT), Scientific Research Institute of System Analysis, Russian Academy of Sciences, in compliance with the 0.25 μm design standards are reported. The results of verification of the developed model over the contours of complex topological structures are reported. The verification was conducted with the use of the SEMCal module of the CAD Calibre.     

A versatile half-micron complementary BiCMOS technology formicroprocessor-based smart power applications

A modular, high density 0.5 μm Complementary BiCMOS technology with integrated high-voltage Lateral Diffused MOS (LDMOS) and conductivity modulated Lateral Insulated Gate Bipolar Transistor (LIGBT) structures designed for high performance, multi-functional integrated circuit applications is described. The advantages of VLSI processing and 0.5 μm compatible layout rules have been applied to the design and fabrication of the tight-pitch high-voltage devices without sacrificing the performance of 0.5 μm dual-poly (N+/P+) gate CMOS and complementary vertical bipolar transistors. Single chip integration of VLSI microprocessors with high-voltage and/or high-current input and output functions for “Smart Power” applications can be achieved using this technology     

Physical and CAD models for the implanted-channel VLSI MOSFET

A new approach is described for the modeling of practical MOS transistors that have nonuniform substrate doping profiles. The threshold characteristic is used to provide an accurate measure of body charge and thereby to give operating point dependences of the threshold voltage, body effect, mobility, and weak-inversion conduction. The results are incorporated into a simple and flexible CAD model suitable for existing and foreseeable devices. The model has continuity of current and all derivatives throughout all regions of operation. It provides an accurate representation of real transistors and minimizes numerical problems of convergence and stability. It has been implemented as level-4 in SPICE 2G.5 and is freely available for VLSI circuit design.     

State space synthesis of integrators based on the MOSFET square law

The authors present a design methodology on pure CMOS VLSI technology, which exploits the square law relationship between gate voltage and drain current in a saturated MOS transistor to implement state equations derived from a given transfer function. The process is illustrated with the design of an differential integrator     

Bulk-Driven Current Differencing Transconductance Amplifier

Low-voltage (LV) low-power (LP) integrated circuit design is becoming a leading trend in VLSI technology, particularly in special portable applications. In this paper, the principle of a bulk-driven MOS transistor is employed in the design of a novel LV LP current differencing transconductance amplifier (CDTA). Designs in the 0.25 μm CMOS technology have been verified via PSpice simulation. The supply voltages are only ±0.6 V.     

Hot-carrier generation in submicrometer VLSI environment

Submicrometer MOSFETs may suffer from reliability degradation, which has a strong correlation with substrate current. In order to know what is happening to substrate current in a VLSI environment, a substrate-current circuit simulator is developed. The simulator is applied to MOS unit circuit blocks, VLSI static memories, and dynamic memories, and their hot-carrier duty ratios are calculated. A new circuit technology, called normally-on enhancement MOSFET insertion (NOEMI), is proposed which can suppress hot-carrier generation. Several design implications for submicrometer VLSIs are obtained through the analysis.     

硬件描述语言VHDL及其应用

ＶＨＤＬ是一种超高速ＶＬＳＩ硬件描述语言，能对集成电路的功能和结构进行描述，用ＣＡＤ软件将其编译和转换，并自动形成线路，概要地介绍了ＶＨＤＬ的设计组织和数据类型，并对ＶＨＤＬ的特点及其在ＶＬＳＩ设计中的应用要点做了一些探讨。     

Computer-aided design for VLSI circuit manufacturability

It is noted that the nominal design created by CAD tools must often be modified to maximize manufacturing yield. Such maximization must be performed during the design to achieve an acceptable level of initial manufacturing yield and during fabrication to achieve the maximum rate of yield improvement in the entire product development cycle. The manufacturing-oriented component of the CAD of VLSI circuits is discussed. The concept of design for manufacturability is explained, and a number of issues and design problems relevant to achieving a high level of IC manufacturability are examined. An overview of needed and existing CAD tools that can be used to solve previously listed problems is presented     

Computer-aided design of an n-MOS custom IC-“Subscriber Chip” of the 32-lines microprocessor based PAX (private automatic exchange) system

A 40-pin custom IC-“Subscriber Chip” of the subscriber module of the Intel 8085A microprocessor based PAX system (32P₄-32 lines and four parallel conversations) has been designed using CAD techniques. The chip design is based on the LOCOS n-MOS(E-D) process, 8 micron minimum feature size geometries, λ-based design rules and the cell based design approach.DIF-POL contact for the gate-source interconnection of the depletion load transistors has been made with the buried contacts. System routing has been done on two layers: metal and polysilicon/diffusion. Single metal layer has been used for power and ground routing having interdigitated structure.Chip has also been designed for its testability analysis based on the chip partioning approach. Two phases of the testing have been evolved and the test pattern generation sequences got fully integrated with the chip layout.Latest CAD techniques: Applicon AGS/860 VLSI Interactive Graphics Design System, MOS circuit simulation program MSINC and Design Rule Check program (DRC) have been used for the design and chip layout. The entire chip has been laid-out in the area of 3.35 × 3.35 mm² integrating around 500 components including test devices and structures for the evaluation of devices and process parameters. The Electromask pattern generation (PG) tape has been prepared for making chrome masks.A set of eight masks are to be used in the fabrication of the chip and encapsulated in 40 pin LSI package. The subscriber chip makes the PAX system design simple and reliable.     

Wave-pipelining: a tutorial and research survey

Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined architectures, and sophisticated computer-aided design (CAD) tools has converted wave-pipelining from a theoretical oddity into a realistic, although challenging, VLSI design method. This paper presents a tutorial of the principles of wave-pipelining and a survey of wave-pipelined VLSI chips and CAD tools for the synthesis and analysis of wave-pipelined circuits     

MOS technology for VLSI

The scaling laws for MOS transistors are reviewed and the optimum performance predicted for both n-channel and p-channel devices are discussed. The physical and technological limitations for MOS VLSI are then described and some important technological challenges such as the implementation of new isolation techniques are pointed out. The mobility degragation effect due to velocity saturation is explained and illustrated by experimental data. The various limitations to the maximum operating voltage of scaleg devices are discussed. Finally, some considerations about speed and power consumption of scaled technologies are made.