Mpeg2 Video Encoding in Consumer Electronics

Only very recently, single-chip MPEG2 video encoders are being reported. They are a result of additional interest in encoding in consumer products, apart from broadcast encoding, where a video encoder contains several expensive chips. Only single-chip solutions are cost-effective enough to enable digital recording for the consumer. The professional broadcast encoders are expensive because they use the full MPEG toolkit to guarantee good image quality, at the lowest possible bit-rate. Some MPEG tools are costly in hardware and these are therefore not feasible in single-chip solutions. This results in higher bit-rates, that can be accepted because of the available channel and storage capacity of the latest consumer storage media, harddisk, digital tape (D-VHS) and Digital Versatile Disk (DVD). A consumer product is I.McIC, a single-chip MPEG2 video encoder. It operates in ML@SP mode which can be decoded by all MPEG2 decoders. The IC is highly-integrated, as it contains motion-estimation and compensation, adaptive temporal noise filtering and buffer/bit-rate control. The high-throughput functions of the MPEG algorithm are mapped onto pipelined dedicated hardware, whereas the remaining functions are processed by an application-specific instruction-set processor. Software for this processor can be downloaded, in order to suit the IC for different applications and operating conditions. The IC consists of several communicating processors which were designed using high-level synthesis tools, PHIDEO and DSP Station.     

A 250-MHz single-chip multiprocessor for audio and video signalprocessing

A 250-MHz single-chip multiprocessor, which can implement multichannel decoding, encoding, and transcoding of various audio and video standards, was fabricated using 0.25-μm CMOS technology and consumes 2.38 W at 2.5 V. The multiprocessor integrates four processors and 64-kB shared level-2 cache and exploits coarse-grained parallelism inherent in audio and video signal processing with multithreaded programming. Three coprocessors and scratch-pad memory have been added to each processing element and perform subword parallel processing, background data transfer, and bitstream processing for audio and video signal processing. Useful-skew and clock gating have been utilized to achieve high-speed operation and low power consumption. Consequently, the multiprocessor achieves MPEG2 (MP@HL) video decoding at 20 frames/s     

Low-power video encoder/decoder chip set for digital VCRs

This paper describes the realization of a video encoder/decoder chip set for the consumer use digital video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 digital component video signal into the standard-definition digital VCR (DV) format or decode the DV format signal into a component video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-μm 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-μm CMOS technology, contains about 500 k transistors on 71 mm² and 79 mm² die, respectively     

A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI

This paper describes a block processing unit in a single-chip MPEG-2 MP@ML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 m triple-layer metal CMOS cell-base technology at 54 MHz.     

基于S3C6410的MPEG4视频压缩滤波器的设计研究

传统的CMOS和CCD摄像头生成的视频文件体积庞大,若直接存储将占用很大的存储空间和传输带宽,给文件的存储和传输带来极大的不便。S3C6410处理器不仅支持摄像头输入,而且拥有支持MPEG-4视频编解码的协处理器。WinCE的DirectShow是一个强大的流媒体处理架构,通过各种功能不同的滤波器来实现视频的采集和压缩。因此使用SC6410处理器的WinCE系统实现视频的压缩处理,MPEG-4视频压缩滤波器的设计成为关键,该设计对此进行了深入研究,并展示其性能。     

A Scalable Architecture for MPEG-4 Wavelet Quantization

Wavelet-based image compression has been adopted in MPEG-4 for visual texture coding. All wavelet quantization schemes in MPEG-4—Single Quantization (SQ), Multiple Quantization (MQ) and Bi-level Quantization—use Embedded Zero Tree (EZT) coding followed by an adaptive arithmetic coder for the compression and quantization of a wavelet image. This paper presents the OZONE chip, a dedicated hardware coprocessor for EZT and arithmetic coding. Realized in a 0.5 m CMOS technology and operating at 32 MHz, the EZT coder is capable of processing up to 25.6 Mega pixel-bitplanes per second. This is equivalent to the lossless compression of 31.6 8-bit grayscale CIF images (352 × 288) per second. The adaptive arithmetic coder processes up to 10 Mbit per second. The combination of the performance of the EZT coder and the arithmetic coder allows the OZONE to perform visual-lossless compression of more than 30 CIF images per second. Due to its novel and scalable architecture, parallel operation of multiple OZONEs is supported. The OZONE functionality is demonstrated on a PC-based compression system.     

A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation

Affine transformation is widely used in image processing. Recently, it is recommended by MPEG-4 for video motion compensation. This paper presents a novel low power parallel architecture for texture warping using affine transformation (AT). The architecture uses a novel multiplication-free algorithm that employs the algebraic properties of the AT. Low power has been achieved at different levels of the design. At the algorithmic level, replacing multiplication operations with bit shifting saves the power and delay of using a multiplier. At the architecture level, low power is achieved by using parallel computational units, where the latency constraints and/or the operating latency can be reduced. At the circuit level, using low power building blocks (such as low power adders) contributes to the power savings. The proposed architecture is used as a computational kernel in video object coders. It is compatible with MPEG-4 and VRML standards. The architecture has been prototyped in 0.6 m CMOS technology with three layers of metal. The performance of the proposed architecture shows that it can be used in mobile and handheld applications.     

DCT-Domain Embedded Memory Compression for Hybrid Video Coders

Hybrid video compression schemes such as MPEG2 and H.263 use an image memory for motion-compensated coding. In VLSI implementations, this image is usually stored in external RAM because of its large size. To reduce the overall system costs, we propose to compress the image by a factor of 4 to 5 before storage, which then enables embedding of the image memory on the encoder IC itself. The proposed encoder architecture remains in the DCT-domain, so motion estimation and compensation are now performed from this domain. To control and guarantee the actual storage, scalable compression is used. A hardware implementation is feasible and worthwhile compared to traditional encoders with no noticeable loss in performance.     

An ultra low power adaptive wavelet video encoder with integratedmemory

This paper describes a low-power, single-chip video encoder intended for battery-operated portable applications. Design goals are minimizing system power as well as utilized bandwidth, and maximizing system integration. The encoder achieves competitive compression, with convenient bit rate scalability, using a peak power dissipation of several hundred μW on a video stream of 8-bit gray scale, 30 frame/s, and 128×128 demonstration resolution. Compression is performed using wavelet filtering, zero-trees, and arithmetic coding, all integrated on a single chip (3 million transistors, 1 cm², in 0.6 μm CMOS, operating at 500 kHz), with no external memory or control. Results do not include use of motion compensation, however, hooks are included at algorithmic and architectural levels to add motion compensation at the cost of power dissipation a few times higher, and more internal memory. In the absence of motion compensation, temporal correlation is still utilized through the use of simple frame differencing. The architectural centerpiece is a massively parallel, fine granularity SIMD array of processing elements (PEs). A mapping is made between small image blocks (4×4 pixels on the test chip) and PEs, with each PE containing both memory and logic required for its block. These results are obtained by careful coordination of design in a deep vertical manner, ranging from system, algorithmic, architectural, circuit, and layout, and designing simultaneously for all required algorithmic subcomponents     

A VLSI architecture for a real-time code book generator and encoderof a vector quantizer

Image compression applications use vector quantization (VQ) for its high compression ratio and image quality. The current VQ hardware employs static instead of dynamic code book generation as the latter demands intensive computation and corresponding expensive hardware even though it offers better image quality. This paper describes a VLSI architecture for a real-time dynamic code book generator and encoder of 512×512 images at 30 frames/s. The four-chip 0.8 μm CMOS design implements a tree of Kohonen self-organizing maps, and consists of two VQ processors and two image buffer memory chips. The pipelined VQ processor contains a computational core for both code book generation and encoding, and is scalable to processing larger frames     

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessorfor multimedia applications

We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and graphic processing capabilities for three-dimensional images, (b) programming flexibility, and (c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set. This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84×10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V     

VLSI systolic binary tree-searched vector quantizer for imagecompression

A high-speed image compression VLSI processor based on the systolic architecture of difference-codebook binary tree-searched vector quantization has been developed to meet the increasing demands on large-volume data communication and storage requirements. Simulation results show that this design is applicable to many types of image data and capable of producing good reconstructed data quality at high compression ratios. Various design aspects of the binary tree-searched vector quantizer including the algorithm, architecture, and detailed functional design are thoroughly investigated for VLSI implementation. An 8-level difference-codebook binary tree-searched vector quantizer can be implemented on a custom VLSI chip that includes a systolic array of eight identical processors and a hierarchical memory of eight subcodebook memory banks. The total transistor count is about 300000 and the die size is about 8.67×7.72 mm² in a 1.0 μm CMOS technology. The throughput rate of this high-speed VLSI compression system is approximately 25 Mpixels per second and its equivalent computation power is 600 million instructions per second     

Efficient VLSI for Lempel-Ziv compression in wireless datacommunication networks

We present a parallel algorithm, architecture, and implementation for efficient Lempel-Ziv (LZ)-based data compression. The parallel algorithm exhibits a scalable, parameterized, and regular structure and is well suited for VLSI array implementation. Based on our parallel algorithm and systematic design methodologies, two semisystolic array architectures have been developed which are low power and area efficient. The first architecture trades off the compression speed for the area and has a low run-time overhead for multichannel compression. The second architecture achieves a high compression rate (one data symbol per clock) at the expense of the area due to a large clock load and global wiring. Compared to a recent state-of-the-art parallel architecture, our first array structure requires significantly less chip area (≃330 k versus ≃36 k transistors) and more than an order of magnitude less power (≈1.0 W versus ≈70 mW) while still providing the compression speed required for most data communication applications. Hence, data compression can be adopted in portable data communication as well as wireless local area networks. The second architecture has at least three times less area and power while providing the same constant compression rate. To demonstrate the correctness of our design, a prototype module for the first architecture has been implemented using 1.2 μ complementary metal-oxide-semiconductor (CMOS) technology. The compression module contains 32 simple and identical processors, has an average compression rate of 12.5 million bytes/s, and consumes 18.34 mW without the dictionary (≈70 mW with a 4.1k SRAM for the dictionary) while operating at a 100 MHz clock rate (simulated)     

Design and Implementation of Computationally Efficient Image Compressor for Wireless Capsule Endoscopy

An image compressor inside wireless capsule endoscope should have low power consumption, small silicon area, high compression rate and high reconstructed image quality. Simple and efficient image compression scheme, consisting of reversible color space transformation, quantization, subsampling, differential pulse code modulation (DPCM) and Golomb–Rice encoding, is presented in this paper. To optimize these methods and combine them optimally, the unique properties of human gastrointestinal tract image are exploited. Computationally simple and suitable color spaces for efficient compression of gastrointestinal tract images are proposed. Quantization and subsampling methods are optimally combined. A hardware-efficient, locally adaptive, Golomb–Rice entropy encoder is employed. The proposed image compression scheme gives an average compression rate of 90.35 % and peak signal-to-noise ratio of 40.66 dB. ASIC has been fabricated on UMC130nm CMOS process using Faraday high-speed standard cell library. The core of the chip occupies 0.018 mm\(^2\) and consumes 35 \(\upmu {\text {W}}\) power. The experiment was performed at 2 frames per second on a \(256\times 256\) color image. The power consumption is further reduced from 35 to 9.66 \(\upmu \)W by implementing the proposed image compression scheme using Faraday low-leakage standard cell library on UMC130nm process. As compared to the existing DPCM-based implementations, our realization achieves a significantly higher compression rate for similar area and power consumption. We achieve almost as high compression rate as can be achieved with existing DCT-based image compression methods, but with an order of reduced area and power consumption.     

一种嵌入式移动视频监控系统的设计

介绍了一种基于嵌入式处理器的移动视频监控系统。系统硬件平台由CMOS图像传感器、G07007SB视频编码器、S3C4510B处理器组成，负责MPEG-4视频数据的采集和压缩编码；软件实现了MPEG-4数据的RTP封装和网络传输。     

DVB中视频编码器的设计

随着计算机技术和集成电路技术的飞速发展，数字电视取代模拟电视成为电视技术发展的必然，而视频压缩编码又是其中的关键。文中首先介绍了ＩＢＭ公司推出的ＭＰＥＧ－２编码芯片组，然后给出了一个利用该芯片组实现ＭＰＥＧ－２ＭＰ＠ＭＬ编码器的方案。     

A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications

A MIMD based multiprocessor architecture for real-time video processing applications consisting of identical bus connected processing elements has been developed. Each processing element contains a RISC processor for controlling and data-dependent tasks and a Low Level Coprocessor for fast processing of convolution-type video processing tasks. To achieve efficient parallel processing of video input signals, the architecture supports independent processing of overlapping image segments. Running at a clock rate of 40 MHz, a single processing element provides a peak performance of 640 Mega arithmetic operations per second (MOPS). For the real-time processing of basic video processing tasks like 3×3 FIR-filter, 8×8 2D-DCT and motion estimation, a single processing element provides a sufficient computational rate for video signals with Common Intermediate Format (CIF) at a frame rate up to 30 Hz. For hybrid source coding of CIF video signals at a frame rate of 30 Hz a multiprocessor system consisting of six processing elements is required. A linear speedup of the multiprocessor system compared to a single processing element is achieved. A VLSI implementation of a processing element in 0.8 µm CMOS technology is under development.     

Adaptive-Quantization Digital Image Sensor for Low-Power Image Compression

The recent emergence of new applications in the area of wireless video sensor network and ultra-low-power biomedical applications (such as the wireless camera pill) have created new design challenges and frontiers requiring extensive research work. In such applications, it is often required to capture a large amount of data and process them in real time while the hardware is constrained to take very little physical space and to consume very little power. This is only possible using custom single-chip solutions integrating image sensor and hardware-friendly image compression algorithms. This paper proposes an adaptive quantization scheme based on boundary adaptation procedure followed by an online quadrant tree decomposition processing enabling low power and yet robust and compact image compression processor integrated together with a digital CMOS image sensor. The image sensor chip has been implemented using 0.35-mum CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 bit per pixel, while maintaining reasonable peak signal-to-noise ratio levels and very low operating power consumption. In addition, the proposed compression processor is expected to benefit significantly from higher resolution and Megapixels CMOS imaging technology     

A video DSP with a macroblock-level-pipeline and a SIMD typevector-pipeline architecture for MPEG2 CODEC

A video DSP with macroblock-level-pipeline and a SIMD type vector-pipeline architecture (VDSP2) has been developed, using 0.5 μm triple-layer-metal CMOS technology. This 17.00 mm×15.00 mm chip consists of 2.5 M transistors, and operates at 100 MHz. The real-time encoder and decoder specified in the MPEG2 main profile at the main level can be realized with two VDSP2's and a motion estimation (ME) unit, and one VDSP2 respectively, at an 80 MHz clock rate, with a total power dissipation of 4.2 W at 3.3 V