New insights in polarity-dependent oxide breakdown for ultrathin gate oxide

In this work, a quantitative analysis is applied to resolve the newly reported polarity-dependent charge-to-breakdown (Q/sub BD/) data from thick oxides of 6.8 nm down to ultrathin oxides of 1.9 nm. Three independent sets of Q/sub BD/ data, i.e., n/sup +/poly/NFET stressed under inversion and accumulation, and p/sup +/ poly/PFET under accumulation are carefully investigated. The Q/sub BD/ degradation observed for p-type anodes, either poly-Si or Si-substrate, can be nicely understood with the framework of maximum energy released by injected electrons. Thus, this work provides a universal and quantitative account for a variety of experimental observations in the time-to-breakdown (T/sub BD/) and Q/sub BD/ polarity-dependence of oxide breakdown.     

Circuit implications of gate oxide breakdown

A model for the oxide breakdown (BD) current–voltage (I–V) characteristics has been experimentally verified on CMOS inverters. The implications of oxide BD on the performance of various CMOS circuit elements are discussed. Examples are shown of cell stability and bitline differentials in static memory (SRAM), signal timing, and inverter chains.     

Ultrathin gate oxide reliability: physical models, statistics, andcharacterization

The present understanding of wear-out and breakdown in ultrathin (t_ox < 5.0 nm) SiO₂ gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed     

Time dependent breakdown of ultrathin gate oxide

Time dependent dielectric breakdown (TDDB) of ultrathin gate oxide (<40 Å) was measured for a wide range of oxide fields (3.4<|E_ox|<10.3 MV/cm) at various temperatures (100⩽T⩽342°C). It was found that TDDB of ultrathin oxide follows the E model. It was also found that TDDB t₅₀ starts deviating from the 1/E model for fields below 7.2 MV/cm. Below 4.8 MV/cm, TDDB t₅₀ of intrinsic oxide increased above the value predicted by the E model obtained for fields >4.8 MV/cm. The TDDB activation energy for this type of gate oxide was found to have linear dependence on oxide field. In addition, we found that γ (the field acceleration parameter) decreases with increasing temperature. Furthermore, it was found that testing at high temperatures (up to 342°C) and low electric field values did not introduce new gate oxide failure mechanism. It is also shown that TDDB data obtained at very high temperature (342°C) and low fields can be used to generate TDDB model at lower temperatures and low fields. Our results (an enthalpy of activation of 1.98 eV and dipole moment of 12.3 eÅ) are in complete agreement with previous results by McPherson and Mogul. Additionally, it was found that TDDB is exponentially dependent on the gate voltage     

Role of hole fluence in gate oxide breakdown

A simple model which links the primary hole and Fowler-Nordheim (FN) electron injections to oxide breakdown is established and the calculation based on this model is in good agreement with our experiments. When the sum of the active trap density D^pri due to primary hole injection and the active trap density Dⁿ due to FN electron injection reaches a critical value D_cri, the oxide breaks down. The hole is two orders of magnitude more effective than FN electron in causing breakdown. These new findings are imperative in predicting oxide reliability and device lifetime     

Investigation of gate oxide breakdown in CMOS integrated circuits

Investigation of gate oxide breakdown in CMOS integrated circuits, aimed at establishing its dependence on substrate doping (type and level) and its acceleration by an electric field, has been performed in this paper. In order to do this, time-zero-dielectric-breakdown (ramp-voltage-stressed I-V) and time-dependent-dielectric-breakdown (constant-voltage-stressed I-t) tests were carried out and the gate oxide breakdown histograms and electric field acceleration factor were determined and discussed in detail.     

Influence of gate oxide breakdown on MOSFET device operation

The degradation of MOS transistor operation due to soft breakdown and thermal breakdown of the gate oxide was studied. Important transistor parameters were monitored during homogeneous stress at elevated temperature until a breakdown event occurred. In case of NMOSFETs the only noticeable signature of soft breakdown is an increase in off current due to enhanced gate induced drain leakage current (GIDL). A model is proposed and it is concluded that this effect only arises if the soft breakdown is located within the gate-to-drain overlap region. The influence of soft breakdown on PMOSFETs is discussed based on the model of enhanced GIDL for NMOSFETs. The degradation due to thermal breakdown of the gate oxide was investigated in detail. As a conclusion, a careful selection of device parameters is necessary in order to detect a device breakdown caused by thermal gate oxide breakdown.     

An approach to statistical analysis of gate oxide breakdown mechanisms

A credible statistical algorithm is required to determine the parameters of the bimodal Weibull mixture distribution exhibited by the gate oxide breakdown phenomenon, consisting of extrinsic early-life defect-induced failures and intrinsic wear-out failure mechanisms. We use a global maximization algorithm called simulated annealing (SA) in conjunction with the expectation–maximization (EM) algorithm to maximize the log-likelihood function of multi-censored gate oxide failure data. The results show that the proposed statistical algorithm provides a good fit to the stochastic nature of the test failure data. The Akaike information criterion (AIC) is used to verify the number of failure mechanisms in the given set of data and the Bayes’ posterior probability theory is utilized to determine the probability of each failure data belonging to different failure mechanisms.     

Modeling of oxide breakdown from gate charging during resist ashing

Plasma damage was observed after exposing an antenna capacitor structure to an O₂ plasma in a single wafer resist asher. The observed early breakdown is well modeled by surface charging caused by plasma nonuniformity. Here, the plasma nonuniformity was induced by gas flow and electrode configuration. The present results agree well with our previous results where magnetic field leads to a nonuniform plasma. In this model, nonuniformity leads to a local imbalance of ion and electron currents which charge up the gate surface and degrade the gate oxide. Using SPICE, a circuit model for the test structure and plasma measurements, the Fowler-Nordheim current through the thin oxide regions at different points on the wafer was calculated and found to agree well with the observed damage. The important implication of this work on oxide reliability is that the modeling gives a clear picture to this breakdown mechanism. The charging model can also be applied to any ashing process in any nonuniform plasma. Moreover, this model provides a physical basis for design rules of device structures for the fabrication of reliable gate oxides in submicron MOS technology     

Lifetime modeling of intrinsic gate oxide breakdown at high temperature

High resolution time-dependent dielectric breakdown tests are carried out on 7.2 nm gate oxide capacitors (n-type) in the electric field range 8.3–13.2 MV/cm at high temperatures (160–240 °C). It is proven that even at these high temperatures log(t_BD) is proportional to 1/E_OX and the time-to-breakdown mechanism matches the anode hole injection (AHI) model (1/E_OX model). In addition it is presented that the TDDB activation energy E_a for this type of gate oxide has linear dependence on stress electric oxide field.     

The statistical distribution of percolation current for soft breakdown in ultrathin gate oxide

Soft breakdown in ultrathin gate oxide has been studied using constant voltage stressing. The behavior of current increments resulting from a number of soft breakdown events has been characterized by statistical distribution. It is shown that the distribution of the current increment follows Weibull distribution rather than log normal distribution. The newly established Weibull slope is shown to be independent of the stressed voltage in the range investigated between 4.5 and 5.1 V. The temperature effect study shows that the Weibull slope reduces with increasing testing temperature. Furthermore, a strong dependence of the Weibull slope on the oxide thickness has been found. These observations can be explained well by geometrical configurations of the percolation path.     

A discussion of some known physical models for second breakdown

The problems about second breakdown can be discussed in three parts: 1) causes of localized high temperatures in the crystal, 2) mechanism of voltage drop, 3) physical state of the crystal after the voltage drop, i.e., the state of the second breakdown, when it is stable and reversible. About point 1) today very much is known. Point 2) cannot be discussed independent of point 3). In regard to point 3) three models have been published: 1) English and Power (1953). A small stable molten zone exists in the crystal. Visual observations (mesoplasmas) have led to this theory. Approximations show, that such a state is possible without destroying the transistor or the diode. 2) Melchior and Strutt (1964). High carrier densities occur at high temperatures and reduce the space charge in the junction in two steps with respect to the different impurity densities on both sides of the junction. This reduction causes the voltage drop. These temperatures are far below the melting point. 3) Weitzsch (1965). A small molten channel exists between the collector and the emitter in transistors or between the low-resistivity zone and the metal in diodes. More accurate calculations with rotational elliptic coordinates show the possibility of realizing such a state. There are sufficient calculations for model 3), which is an extension of model 1) only. Model 2) cannot be discussed in a closed form without knowledge of the ionization coefficients in the Townsend equation at high temperatures. There are two other models with possible low voltage state, but probably being not specific for second breakdown.     

Potential vulnerability of dynamic CMOS logic to soft gate oxide breakdown

The effect of gate oxide breakdown on a circuit designed to emulate a principle of dynamic CMOS logic is studied experimentally. Retention time of a soft node in the circuit is found to strongly decrease after a soft gate oxide breakdown path leading to the node is created in a pass transistor. Based on this observation, it is argued that some soft breakdowns may degrade soft node retention time below the time necessary for successful evaluation of the nodes charge. Consequently, a soft breakdown event in a dynamic CMOS circuit relying on uncorrected soft nodes may result in the failure of the circuit.     

Impact of MOSFET gate oxide breakdown on digital circuit operationand reliability

The influence of FET gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy, and circuit analysis. It is demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function. Time-to-breakdown data measured on individual FETs are shown to scale correctly to circuit level. SPICE simulations of the ring oscillator with the affected FET represented by an equivalent circuit confirm the measured influence of the breakdown on the circuit's frequency, the stand-by and the operating currents. It is concluded that if maintaining a digital circuit's logical functionality is the sufficient reliability criterion, a nonzero probability exists that the circuit will remain functional beyond the first gate oxide breakdown. Consequently, relaxation of the present reliability criterion in certain cases might be possible     

Dependence of gate oxide breakdown on initial charge trapping under Fowler-Nordheim injection

This work demonstrates that for constant oxide reliability stresses in the Fowler-Nordheim regime a low initial rate of charge trapping/detrapping results in long times to breakdown. It was found for MOS gate oxides that when the initial trapping has been completed at low fields times to breakdown enhance. Depending on the stress sequence measurement results can vary significantly which is of great relevance for correct oxide lifetime predictions.     

On implant-based multiple gate oxide schemes for system-on-chip integration

Integrating the entire system on a chip (SoC) is one of the main challenges for many researchers all over the world. One of the major breakthroughs toward achieving this goal has been the ability to manufacture multiple gate oxides for different requirements on the same chip. The most attractive of the techniques currently in the literature is the implantation of nitrogen in silicon, which can be used to achieve the goal of multiple gate oxide thickness. The rate of oxidation depends on the amount of nitrogen incorporated at the silicon/silicon oxide interface. By modulating the amount of nitrogen incorporated at the interface, the rate of oxidation and hence the oxide thickness can be moderated. This paper reviews the diffusion, oxidation, and device issues pertaining to the use of nitrogen implants in silicon and also compares it to other implant-based techniques related to the achievement of multiple oxide thickness across the chip for SoC integration.     

Evaluation of gate oxide breakdown effect on cascode class E power amplifier performance

A CMOS cascode class E power amplifier has been designed at 5.2 GHz. Its RF performances such as output and power-added efficiency have been examined in ADS simulation. The layout parasitic is accounted for in the post-layout simulation. Time-dependent drain-source voltage waveforms indicate that the drain of cascode transistor is subject to much higher voltage stress than that of main transistor. Analytical equation of output power including impact of gate-oxide breakdown is developed and compared with RF simulation results. Good agreement between the model predictions and ADS simulation is obtained. The gate-drain breakdown of the cascode transistor decreases the output power and power-added efficiency of the power amplifier significantly when the breakdown resistance is below 1 kΩ.