3300V碳化硅肖特基二极管及混合功率模块研制

基于数值仿真结果,采用结势垒肖特基(JBS)结构和多重场限环终端结构实现了3 300 V/50 A 4H-SiC肖特基二极管(SBD),所用4H-SiC外延材料厚度为35 μm、n型掺杂浓度为2× 1015cm-3.二极管芯片面积为49 mm2,正向电压2.2V下电流达到50 A,比导通电阻13.7 mΩ· cm2;反偏条件下器件的雪崩击穿电压为4 600 V.基于这种3 300 V/50 A 4H-SiC肖特基二极管,研制出3 300 V/600 A混合功率模块,该模块包含24只3 300 V/50 A Si IGBT与12只3 300 V/50 A 4H-SiC肖特基二极管,SiC肖特基二极管为模块的续流二极管.模块的动态测试结果为:反向恢复峰值电流为33.75 A,反向恢复电荷为0.807 μC,反向恢复时间为41 ns.与传统的Si基IGBT模块相比,该混合功率模块显著降低了器件开关过程中的能量损耗.     

On-State Characteristics of SiC power UMOSFETs on 115-/spl mu/m drift Layers

We describe the on-state performance of trench oxide-protected SiC UMOSFETs on 115-/spl mu/m-thick n-type 4H-SiC epilayers designed for blocking voltages up to 14 kV. An on-state current density of 137 A/cm/sup 2/ and specific on-resistance of 228 m/spl Omega//spl middot/cm/sup 2/ are achieved at a gate bias of 40 V (oxide field of 2.67 MV/cm). The effect of current spreading on the specific on-resistance for finite-dimension devices is investigated, and appropriate corrections are made.     

采用场板和边缘终端技术的大电流Ni/4H-SiC SBDs

研究了4H-SiC低缺陷密度外延层的制造和Ni/SiC肖特基势垒二极管的正、反向电学特性。采用了偏8°4H-SiC衬底上台阶控制外延方法进行同质外延,外延温度1580℃,最后得到了低缺陷密度的3英寸外延片。采用了原子力显微镜和扫描电子显微镜进行了测试。在外延片上进行的Ni/4H-SiC肖特基势垒二极管的制造,采用了B+离子注入形成的一个非晶区域作为边缘终端,然后使用经过1000℃下退火10min的PECVD生长的SiO2作为场板介质。最终得到的Ni/4H-SiC肖特基势垒二极管的理想因子为1.03,势垒高度为1.6eV,在反向偏压1102V时,漏电流密度只有1.15×10-3A/cm2。在正向压降3.5V时得到了7.47A的大电流输出,特征导通电阻为6.22Ω.cm2。     

4H-SiC SBD和JBS退火研究

在4H-SiC外延材料上制备了SBD和JBS器件,研究并分析了退火温度对这两种器件正反向特性的影响。结果表明,低于350℃退火可同时提高SBD和JBS的正反向特性。当退火温度高于350℃时,二者的正向特性都出现退化,SBD退化较JBS更为严重。JBS阻断电压随退火温度升高而增大,在退火温度高于450℃时增加趋势变缓。SBD阻断电压随退火温度升高先升后降,在500℃退火时达到一个最大值。可见一定程度的退火有助于提高4H-SiCSBD和JBS器件的正反向特性,但须考虑其对正反向特性的不同影响。综合而言,退火优化后JBS优于SBD器件性能。     

3 A/40 V新型肖特基势垒二极管的设计与研制

为提高传统肖特基二极管的击穿电压,减小了器件的漏电流,提高芯片利用率,文中设计研制了适合于裸片封装的新型肖特基势垒二极管(SBD)。利用Silvaco Tcad软件模拟,在器件之间采用PN结隔离,器件周围设计了离子注入形成的保护环,实现了在浓度和厚度分别为7.5×1012 cm-3和5 μm的外延层上,制作出了反向击穿电压45 V和正向导通压降0.45 V的3 A/45 V肖特基二极管,实验和仿真结果基本吻合。此外,还开发了改进SBD结构、提高其电特性的工艺流程。     

Demonstration of the first 10-kV 4H-SiC Schottky barrier diodes

This letter reports the demonstration of the first 4H-SiC Schottky barrier diode (SBD) blocking over 10 kV based on 115-/spl mu/m n-type epilayers doped to 5.6 /spl times/ 10/sup 14/ cm/sup -3/ through the use of a multistep junction termination extension. The blocking voltage substantially surpasses the former 4H-SiC SBD record of 4.9 kV. A current density of 48 A/cm/sup 2/ is achieved with a forward voltage drop of 6 V. The Schottky barrier height, ideality factor, and electron mobility for this very thick epilayer are reported. The SBD's specific-on resistance is also reported.     

High current density 800-V 4H-SiC gate turn-off thyristors

4H-SiC gate turn-off thyristors (GTOs) were fabricated using the recently developed inductively-coupled plasma (ICP) dry etching technique. DC and ac characterisation have been done to evaluate forward blocking voltage, leakage current, on-state voltage drop and switching performance. GTOs over 800 V dc blocking capability has been demonstrated with a blocking layer thickness of 7 μm. The dc on-state voltage drops of a typical device at 25 and 300°C were 4.5 and 3.6 V, respectively, for a current density of 1000 A/cm². The devices can be reliably turned on and turned off under an anode current density of 5000 A/cm² without observable degradation     

4500V碳化硅肖特基二极管研究

设计了一种阻断电压4 500V的碳化硅(SiC)结势垒肖特基(JBS)二极管。采用有限元仿真的方法对器件的外延掺杂浓度和厚度以及终端保护效率进行了优化。器件采用50μm厚、掺杂浓度为1.2×1015cm-3的N型低掺杂区。终端保护结构采用保护环结构。正向电压4V下导通电流密度为80A/cm2。     

600 V-30 A 4H-SiC肖特基二极管作为IGBT续流二极管的研究

采用碳化硅外延和器件工艺制造了碳化硅肖特基(SBD)二极管,耐压超过600 V。正向压降为1.6 V时,器件电流达到30A。作为IGBT续流二极管,600 V碳化硅肖特基二极管和国际整流器公司的600 V超快恢复二极管(Ultra fast diode)进行了对比:125℃IGBT模块动态开关测试中,碳化硅二极管的反向恢复能耗比硅二极管节省90%,相应的IGBT开通能耗节省30%。另外反向恢复中过电压从40%降为10%,这是由于碳化硅的软度高,提高了模块的可靠性。     

1200V/100A高温大电流4H-SiC JBS器件的研制

基于SiC结势垒肖特基(JBS)二极管工作原理及其电流/电场均衡分布理论,采用高温大电流单芯片设计技术及大尺寸芯片加工技术,研制了1 200 V/100 A高温大电流4H-SiCJBS二极管.该器件采用优化的材料结构、有源区结构和终端结构,有效提高了器件的载流子输运能力.测试结果表明,当正向导通压降为1.60 V时,其正向电流密度达247 A/cm2(以芯片面积计算).在测试温度25和200℃时,当正向电流为100 A时,正向导通压降分别为1.64和2.50 V;当反向电压为1 200 V时,反向漏电流分别小于50和200μA.动态特性测试结果表明,器件的反向恢复特性良好.器件均通过100次温度循环、168 h的高温高湿高反偏(H3TRB)和高温反偏可靠性试验,显示出优良的鲁棒性.器件的成品率达70％以上.     

Electrical parameters of a DC sputtered Mo/n-type 6H-SiC Schottky barrier diode

A Mo/n-type 6H-SiC/Ni Schottky barrier diode (SBD) was fabricated by sputtering Mo metal on n-type 6H-SiC semiconductor. Before the formation of Mo/n-type 6H-SiC SBD, an ohmic contact was formed by thermal evaporation of Ni on n-type 6H-SiC and annealing at 950 °C for 10 min. It was seen that the structure had excellent rectification. The electrical parameters were extracted using its current–voltage (I–V) and capacitance–voltage (C–V) measurements carried out at room temperature. Very high (1.10 eV) barrier height and 1.635 ideality factor values were reported for Mo/n-type 6H-SiC using ln I–V plot. The barrier height and series resistance values of the diode were also calculated as 1.413 eV and 69 Ω from Norde׳s functions, respectively. Furthermore, 1.938 eV barrier height value of Mo/n-type 6H-SiC SBD calculated from C–V measurements was larger than the one obtained from I–V data.     

A 4.15 kV 9.07-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC Schottky-barrier diode using Mo contact annealed at high temperature

In this letter, we report the fabrication of high-voltage and low-loss 4H-SiC Schottky-barrier diodes (SBDs) with a performance close to the theoretical limit using a Mo contact annealed at high-temperature. High-temperature annealing for the Mo contact was found to be effective in controlling the Schottky-barrier height at 1.2-1.3 eV without degradation of n-factor and reverse characteristics. We successfully obtained a 1-mm/sup 2/ Mo-4H-SiC SBD with a breakdown voltage (V/sub b/) of 4.15 kV and a specific on resistance (R/sub on/) of 9.07 m/spl Omega//spl middot/cm/sup 2/, achieving a best V/sub b//sup 2//R/sub on/ value of 1898 MW/cm/sup 2/. We also obtained a 9-mm/sup 2/ Mo-4H-SiC SBD with V/sub b/ of 4.40 kV and R/sub on/ of 12.20 m/spl Omega//spl middot/cm/sup 2/.     

4H-SiC normally-off vertical junction field-effect transistor with high current density

4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches.     

Electrical characteristics of 4.5 kV implanted anode 4H-SiC p-i-njunction rectifiers

4500 V 4H-SiC p-i-n junction rectifiers with low on-state voltage drop (3.3-4.2 V), low reverse leakage current (3×10^-6 A/cm²), and fast switching (30-70 ns) have been fabricated and characterized. Forward current-voltage measurements indicate a minimum ideality factor of 1.2 which confirms a recombination process involving multiple energy levels. Reverse leakage current exhibits a square root dependence on voltage below the punchthrough voltage where leakage currents of less than 3×10^-6 A/cm² are measured. Reverse recovery measurements are presented which indicate the presence of recombination at the junction perimeter where a surface recombination velocity of 2-8×10⁵ cm/s is found. These measurements also indicate drift layer bulk carrier lifetimes ranging from 74 ns at room temperature to 580 ns at 250°C     

AlGaN/GaN power HFET on silicon substrate with source-via grounding (SVG) structure

We have developed a high-power AlGaN/GaN HFET fabricated on 4-in conductive Si substrate with a source-via grounding (SVG) structure. The SVG structure enables efficient chip layout and high packing density by the vertical configuration. By establishing a high-quality epitaxial technology on a Si substrate and by significantly reducing the parasitic resistance, a very low specific on-state resistance of 1.9 m/spl Omega//spl middot/cm/sup 2/ is achieved. The breakdown voltage is as high as 350 V, which is attributed to the Si substrate acting as a backside field plate. Because of reduction of the parasitic inductance, very high level of current (2.0 kA/cm/sup 2/) transients, i.e., a turn-on time of 98 ps and a turn-off time of 96 ps, are successfully measured for the first time.     

High-voltage accumulation-layer UMOSFET's in 4H-SiC

A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 μm drift region), a specific on-resistance of 15.7 mΩ-cm ² at room temperature, and a gate oxide field of 3 MV/cm     

外延层厚度对垂直结构6H-SiC光导开关特性影响的研究

设计了新颖的具有垂直结构的6H-SiC光导开关。首先采用离子注入工艺在半绝缘6H-SiC衬底两侧生成一层p+离子注入层,然后利用外延工艺在其中的一侧生长一层n+外延层,并将此侧定义为开关的阴极。利用二维半导体器件仿真软件,研究了n+外延层厚度对6H-SiC光导开关特性的影响。结果表明,增加外延层厚度可以提高开关的击穿电压;而开关的导通电流,首先随着n+外延层厚度的增加而减小,在n+外延层厚度为5?m达到最小值,随后随着厚度的增加,导通电流增加。     

Breakdown voltage and reverse recovery characteristics offree-standing GaN Schottky rectifiers

Schottky rectifiers with implanted p⁺ guard ring edge termination fabricated on free-standing GaN substrates show reverse breakdown voltages up to 160 V in vertical geometry devices. The specific on-state resistance was in the range 1.7-3.0 Ω·cm ², while the turn-on voltage was ~1.8 V. The switching performance was analyzed using the reverse recovery current transient waveform, producing an approximate high-injection, level hole lifetime of ~15 ns. The bulk GaN rectifiers show significant improvement in forward current density and on-state resistance over previous heteroepitaxial devices     

High voltage (>1kV) and high current gain (32) 4H-SiC power BJTs using Al-free ohmic contact to the base

This letter reports the design and fabrication of 4H-SiC bipolar junction transistors with both high voltage (>1kV) and high dc current gain (/spl beta/=32) at a collector current level of I/sub c/=3.83A (J/sub c/=319 A/cm/sup 2/). An Al-free base ohmic contact has been used which, when compared with BJTs fabricated with Al-based base contact, shows clearly improved blocking voltage. A specific on-resistance of 17 m/spl Omega//spl middot/cm/sup 2/ has been achieved for collector current densities up to 289 A/cm/sup 2/.     

快速热退火对ITO薄膜及LED芯片性能的影响

采用金属有机化学气相沉积(MOCVD)技术在蓝宝石衬底上制备了GaN基LED外延层,采用磁控溅射法制备了氧化铟锡(ITO)薄膜,ITO薄膜用于制作与p-GaN的欧姆接触.研究了快速热退火温度为550℃,退火时间为200 s时,不同氧气体积流量对ITO薄膜性能及LED芯片光电性能的影响.结果表明:不通氧气时,ITO薄膜的方块电阻和透过率分别为33 Ω/口和93.1％,LED芯片出现电流拥挤效应,其电光转换效率只有33.3％;氧气体积流量为1 cm3/min时,ITO薄膜的方块电阻和透过率分别为70 Ω/口和95.9％,LED芯片的电流扩展不佳,其正向电压较高,电光转换效率为43.8％;氧气体积流量为0.4 cm3/min时,ITO薄膜的方块电阻和透过率分别为58 Ω/口和95.4％,LED芯片的电流扩展最佳,其亮度最高、正向电压最低,电光转换效率较高,为52.9％.