Characterization and CMRR Modeling of a Carbon-Nanotube Field-Emission Differential Amplifier

A novel vacuum field-emission differential amplifier (diff-amp) based on carbon-nanotube (CNT) emitters has been developed, modeled, and its ac performance characterized. A dual-mask microfabrication process was employed to achieve a single-chip diff-amp by integrating matched CNT field-emission triodes with built-in split gates and integrated anodes. The identical pair of triode amplifiers was well matched in device characteristics. The measured ac common-mode-rejection ratio (CMRR) of the diff-amp was ~ 50 dB. The proposed CMRR semianalytical model was validated with the experimental data. The successful implementation of the CNT diff-amp demonstrates a new way to achieve high-temperature and radiation-tolerant vacuum integrated circuits.     

一种高速信号的可编程有源连续时间均衡器的设计

介绍了一种基于0.18μm标准CMOS工艺实现的,用于均衡1.25 Gb/s高速信号的可编程有源连续时间均衡器。通过外部可编程逻辑器件输出的控制信号,控制该均衡器的输入信号Ctrl,从而改变其高频增益提升系数,最大可以实现长达40英寸(1 000 mm)的FR-4背板传输线衰减后的接收信号的均衡。该均衡器的电路主要由R-C电阻电容衰减差分放大器和MCML输出缓冲级组成,其中R-C放大器完成输入信号的高频增益提升,MCML缓冲级完成输出信号的整形并提供一定的增益。该均衡器的工作电压为1.8 V,在输入信号速率为1.25 Gb/s时,总的工作电流为1.6 mA。     

Shortwave Infrared Polarization Imaging and Monolithic Integrated Polarization Amplification Systems Based on Aligned Carbon Nanotube Arrays

Next-generation shortwave infrared (SWIR) imaging systems generally require a multidimensional information sensing capability (including intensity, wavelength, polarization, phase, etc.), a highly integrated photodetector unit, and information processing, allowing for miniaturization and low-cost production. However, traditional polarized SWIR imaging systems with integrated polarizer arrays as supplementary filters and silicon-based amplifying circuits are complicated and very expensive. Here, a SWIR polarization-sensitive photodetector and a monolithic integrated polarization amplification system (MIPAS) based on well-aligned carbon nanotube (CNT) arrays are demonstrated. The polarization-sensitive CNT photodetector exhibits anisotropic ratios of ≈5.18 and ≈7.56 at 1800 and 2000 nm wavelengths, respectively, and high-resolution characteristics that can be utilized to image SWIR laser spots with a radius of less than 10 µm. Furthermore, MIPAS including a CNT field-effect transistor, a CNT loading resistor, and a polarization-sensitive CNT photodetector is used to increase the anisotropic ratio of the CNT photodetector. The amplified anisotropic ratio is improved up to 173 and 243 at 1800 and 2000 nm wavelengths, respectively, which is the maximum reported in the SWIR band.  Our work demonstrates that the CNT polarization-sensitive photodetector has the potential for SWIR polarization imaging with a monolithic integrated polarization amplification system.     

Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications

Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient.     

Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects

This paper reviews the current state of research in carbon-based nanomaterials, particularly the one-dimensional (1-D) forms, carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), whose promising electrical, thermal, and mechanical properties make them attractive candidates for next-generation integrated circuit (IC) applications. After summarizing the basic physics of these materials, the state of the art of their interconnect-related fabrication and modeling efforts is reviewed. Both electrical and thermal modeling and performance analysis for various CNT- and GNR-based interconnects are presented and compared with conventional interconnect materials to provide guidelines for their prospective applications. It is shown that single-walled, double-walled, and multiwalled CNTs can provide better performance than that of Cu. However, in order to make GNR interconnects comparable with Cu or CNT interconnects, both intercalation doping and high edge-specularity must be achieved. Thermal analysis of CNTs shows significant advantages in tall vias, indicating their promising application as through-silicon vias in 3-D ICs. In addition to on-chip interconnects, various applications exploiting the low-dimensional properties of these nanomaterials are discussed. These include chip-to-packaging interconnects as well as passive devices for future generations of IC technology. Specifically, the small form factor of CNTs and reduced skin effect in CNT interconnects have significant implications for the design of on-chip capacitors and inductors, respectively.      

Emerging interconnects: a state-of-the-art review and emerging solutions

Aluminium was a primary material for interconnection in integrated circuits (ICs) since their inception. Later, copper was introduced as interconnect material which has better metallic conductivity and resistance to electromigration. As the aggressive technology scaling continues, the copper resistivity increased because of size effects, which causes increase in delay, power dissipation and electromigration. The need to reduce the resistor-capacitor??????? delay, dynamic power utilisation and the crosstalk commotion is as of now the fundamental main impetus behind the presentation of new materials. The purpose of this paper is to do a survey of interconnect material used in IC from introduction of ICs to till date. This paper studies and reviews new materials available for interconnect application which are optical interconnects, carbon nanotube (CNT), graphene nanoribbons (GNRs) and silicon nanowires which are alternatives to copper. While doing a survey of interconnect material, it is found that multiwalled CNTs, multilayer GNR and mixed CNT bundles are promising candidates and are ultimate choice that can strongly address the problems faced by copper but on integration basis copper would last for coming years.     

A direct-conversion receiver for DVB-H

A fully integrated low-power ultrahigh-frequency (UHF) tuner integrated circuit (IC) design for the digital video broadcasting-handheld (DVB-H) market is presented. A direct-conversion receiver is chosen over classical digital video broadcasting-terrestrial (DVB-T) architectures. The tuner IC covers UHF bands IV/V. The solution is based on a radio frequency integrated circuit (RFIC) and external low-noise amplifier (LNA) to meet the noise figure (NF) specification of 5 dB, IIP3 of 4dBm, and Gain of 89 dB. The IC includes an LNA, dual quadrature mixers, multiple bandwidth baseband (BB) filtering, three 4X voltage-controlled oscillators (VCOs), integer phase-locked loop (PLL), and reference oscillator. The design is implemented in a SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) technology and the die area is 11.5 mm/sup 2/.     

基于Pd/SWNT/Al结构的场效应晶体管的研究

碳纳米管因具有良好的物理机械性能而得到广泛的研究,其最重要的应用之一是构建场效应晶体管(FET).文章提出并研究了一种非对称接触的单壁碳纳米管场效应晶体管(SWNT-FET),并对其电学特性进行了表征.在该器件中,SWNT被作为FET的沟道,两种不同功函数的金属被用来与SWNT形成肖特基接触;SWNT一端与低功函数金属Al形成源极,另一端与高功函数金属Pd形成漏极.该类器件可应用于下一代纳米集成电路中.     

A 40-Gbit/s superdynamic decision IC fabricated with 0.12-μmGaAs MESFET's

This paper describes a 4O-Gbit/s decision integrated circuit (IC) fabricated with 0.12-μm gate length GaAs metal-semiconductor field-effect transistors (MESFET's). A superdynamic flip-flop circuit and a wide-band amplifier were applied in order to attain 40-Gbit/s operation. A conventional static decision IC was also fabricated for comparison. The dynamic decision IC operated up to 40 Gbit/s, which is twice as fast as the conventional static decision IC. Error-free 40-Gbit/s operation is the fastest among GaAs MESFET decision IC's     

Pad Deflection-Based Model of Chemical–Mechanical Polishing for Use in CAD IC Layout

The use of chemical–mechanical polishing (CMP) during the integrated circuit (IC) fabrication process has allowed for the aggressive interconnect patterning that is necessary for modern microprocessor technology. However, as IC technology has moved into the deep submicron realm, nonidealities during polishing have begun to play a significant role in device yield and circuit performance. In order to accurately predict circuit performance, designers must consider the effects of CMP prior to fabrication. A physics-based model to predict feature-scale wear of devices during polishing is presented and integrated into a CAD framework to test the model on various IC layouts. The model is benchmarked against experimental data and shown to be qualitatively accurate in predicting surface topography evolution.      

Covalently Bonded Graphene–Carbon Nanotube Hybrid for High‐Performance Thermal Interfaces

The remarkable thermal properties of graphene and carbon nanotubes (CNTs) have been the subject of intensive investigations for the thermal management of integrated circuits. However, the small contact area of CNTs and the large anisotropic heat conduction of graphene have hindered their applications as effective thermal interface materials (TIMs). Here, a covalently bonded graphene–CNT (G‐CNT) hybrid is presented that multiplies the axial heat transfer capability of individual CNTs through their parallel arrangement, while at the same time it provides a large contact area for efficient heat extraction. Through computer simulations, it is demonstrated that the G‐CNT outperforms few‐layer graphene by more than 2 orders of magnitude for the c‐axis heat transfer, while its thermal resistance is 3 orders of magnitude lower than the state‐of‐the‐art TIMs. We show that heat can be removed from the G‐CNT by immersing it in a liquid. The heat transfer characteristics of G‐CNT suggest that it has the potential to revolutionize the design of high‐performance TIMs.     

Novel and general carbon nanotube FET-based circuit designs to implement all of the 3 ternary functions without mathematical operations

In this paper, we propose new universal designs of ternary-valued logic (TVL) with high-speed, low-power and full swing output using carbon nanotube FETs (CNTFETs). All of the TVL functions (3⁹ functions) can be implemented in these designs. Ternary value logic is a promising alternative to binary logic due to the reduced integrated circuit (IC) interconnects and chip area. Therefore, a universal design of TVL is a good direction for the future of FPGA design using CNTFET. In this paper, new universal designs of ternary-valued logic based on CNTFETs are proposed and compared with the existing resistive-load CNTFET universal TVL designs. Extensive simulations have been performed in HSPICE to investigate the distribution of power consumption and the delay of the CNTFET-based universal cells due to variations in the supply voltage, the diameter of the CNT, and the room temperature. Simulation results show that the proposed universal TVL designs result in significantly lower power consumption and delay compared with previous resistive-load CNTFET universal TVL implementations.     

A Digital Receiver Architecture for Bluetooth in 0.25- μm CMOS Technology and Beyond

A digital receiver architecture for short-range communications systems like Bluetooth is presented. The architecture is tailored to a highly integrated Bluetooth single-chip integrated circuit (IC) and can easily be adapted to other communications systems using a Gaussian frequency-shift keying (GFSK ) modulation scheme. The single-chip IC integrates the complete digital baseband and radio frequency (RF) functionality on a single die and is realized in a 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology targeted for cost efficiency. The superior performance of this digital receiver architecture compared to the state-of-the-art short-range communications receivers is shown. Simulation and measurement results are presented showing a receiver sensitivity of 87 dBm and excellent co-channel and adjacent channel interference performance.     

试验设计与仿真相结合构造集成电路元模型的方法研究

集成电路的设计与优化常需要指标与参数简单、直接的模型,即电路的元模型.本文将试验设计与计算机仿真相结合构造集成电路的元模型.讨论了构造元模型中使用的4种试验设计类型与3种模型.结合低功耗集成运算放大器性能指标静态功耗元模型的构造,分析比较了不同方法的各自特点.从结果可以看出,将拉丁超立方抽样与Kriging模型相结合最适合仿真试验中的电路元模型的构造.     

Integration and electrical characterization of carbon nanotube via interconnects

Carbon nanotubes (CNTs) are considered a promising material for interconnects in the future generations of microchips because of their low electrical resistance and excellent mechanical stability. In particular, CNT-based contacts appear advantageous when compared with current tungsten or copper technologies and could therefore find an application as metal contacts interconnecting the transistors with the back end of line of the microchip. In this work, the integration of vertical CNT bundles in sub-micron contact holes is evaluated at wafer scale and the major integration challenges encountered in the practical realization of the process are discussed. Nickel PVD films were used to selectively grow CNT into the contact holes at temperatures as low as 400 °C, which is the thermal budget available for contacts. The height of the contacts and the length of the CNT are controlled by a chemical mechanical polishing step (CMP) after embedding the CNT into SiO₂. Ti/Au metal pads are then formed onto the CNT bundles by PVD and lift-off. The integrated CNT are electrically characterized and an annealing treatment was found to improve the CNT-via resistance. As the electrical properties of the CNT can be evaluated, the structure and the process presented constitute a test vehicle for the development of high-quality CNT-contacts.     

Electrical properties of carbon nanotube via interconnects for 30 nm linewidth and beyond

The continuous downward scaling in integrated circuit (IC) technologies has led to rapid shrinking of transistor and interconnect feature sizes. While scaling benefits transistors by increasing the switching speed and reducing the power consumption, it has an adverse impact on interconnects by degrading its electrical performance and reliability. Scaling causes reduction in interconnect linewidth, which leads to surge in resistance due to increased contributions from grain boundary and surface scattering of electrons in the metal lines. Further, current density inside interconnects is also enhanced by the reduced linewidth and is approaching or exceeding the current-carrying capacity of the existing interconnect metals, copper (Cu) and tungsten (W). The resulting failure due to electromigration presents a critical challenge for end-of-roadmap IC technology nodes. Therefore, alternative materials such as nanocarbons and silicides are being investigated as potential replacements for Cu and W as they have superior electrical and mechanical properties in the nanoscale. In this review, the electrical properties of nanocarbons, in particular carbon nanotubes (CNTs), are examined and their performance and reliability in the sub-100 nm regime are assessed. Further, the measured properties are used to project 30 nm CNT via properties, which are compared with those of Cu and W.     

A fully integrated 10-Gb/s tapped delay Hilbert transformer for optical single sideband

A 10-Gb/s SiGe HBT tapped delay Hilbert transformer (HT) integrated circuit (IC) is described. The four tap filter uses an integrated LC transmission line with a total delay of 180ps, and the HT has a nominal group delay of 120ps. The circuit is fabricated in a 47-GHz f/sub T/ SiGe HBT process and consumes 112mW from a -3.3-V supply. Measured s-parameters and time domain waveforms are shown to agree with theory. Measurements of a 10-Gb/s optical single sideband system indicate that 7dB of broadband sideband suppression is obtainable using the IC.     

Exploring the Performance Limit of Carbon Nanotube Network Film Field‐Effect Transistors for Digital Integrated Circuit Applications

Carbon nanotube (CNT) network thin film field‐effect transistors (TFTs), which used to be considered as low cost and low performance transistors for display driving or flexible electronics, have recently been used to construct digital integrated circuits (ICs). However, few studies have focused on exploring how optimal CNT TFTs can be achieved according to transistor standards in digital applications. In this work, sub‐micrometer TFTs based on high‐quality and high‐purity solution‐derived CNT films are fabricated and the potential performance restriction due to the switching‐off property of these transistors is explored. Specifically, subthreshold swing (SS) severely degrades upon scaling down the channel length or increasing the CNT density in TFTs, and a tradeoff between peak transconductance (g_m) and SS in CNT TFTs due to the random orientation distribution of CNTs has been observed in experiments and proven by theoretical simulations. A well‐designed balance between g_m and SS is necessary to build CNT TFTs with SS of 120 mV dec^?1 and g_m of 150 µS µm^?1 to meet device requirements in digital ICs powered by a supplied voltage, V_DD, lower than 2.0 V.     

VLSI计算机辅助设计框架──面向对象的DO模型及EOIDE框架的开发

本文叙述了一种新的集成电路计算机辅助设计框架的设计思想：提出了符合集成电路设计需要的新的四维数据模型，并设计了面向对象的工程数据库；提出了便于在框架中集成已开发完成的ＩＣ设计工具的松耦合的集成方式。讨论了用户管理、设计数据的版本管理以及在层次设计、多用户环境下的并发控制等在框架实施中的问题，提出了处理方案。基于上述思想，在ＨＰ／８００工作站ＵＮＩＸ操作系统下开发了集成电路设计框架ＥＯＩＤＥ（Ｅｎｔｉｔｙ－ＯｒｉｅｎｔｅｄＩＣＩｎｔｅｇｒａｔｅｄＤｅｖｅｌｏｐｍｅｎｔＥｎｖｉｒｏｎ－ｍｅｎｔ），并在框架上装入了单层门阵列设计工具（ＥＮＹＡ），设计了单层门阵列电路，结果良好。     

Integrable sinusoidal frequency doubler

A frequency doubling technique for sinusoidal signals is described. The circuit is fully compatible with silicon integrated circuit (IC) technology, and makes use only of integrated bipolar transistors and resistors. Basically a two-quadrant square-law device, the circuit can also be used for instantaneous or average power measurement.