Hot-electron immunity of SiO2 dielectrics with fluorineincorporation

The effect of fluorine incorporation in the gate oxide on the NMOSFET hot-electron immunity is examined. Fluorine is implanted in the polysilicon gate and diffused into the gate oxide. The hot-electron immunity of NMOSFETs is shown to increase with increasing fluorine doses. Measurement of device lifetime against substrate current shows that higher doses of fluorine lead to a change in the immunity to interface trap generation. Based on the results of Auger measurements, this has been correlated with a fluorine deficient layer near the interface     

Thickness limitations of SiO2 gate dielectrics for MOSULSI

The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined. Leakage current has been found to be a greater problem for static logic than for dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations, and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si₃N ₄ has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current     

超薄SiO2/HfO2双层栅介质的时变击穿特性和击穿机制的研究

The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.     

Electrical properties of MOSFET's with N2O-nitridedLPCVD SiO2 gate dielectrics

Electrical properties of MOSFETs with gate dielectrics of low-pressure chemical-vapor-deposited (LPCVD) SiO₂ nitrided in N₂O ambient are compared to those with control thermal gate oxide. N₂O nitridation of CVD oxide, combines the advantages of interfacial oxynitride growth and the defectless nature of CVD oxide. As a result, devices with N₂O-nitrided CVD oxide show considerably enhanced performance (higher effective electron mobility), improved reliability (reduced charge trapping, interface state generation, and transconductance degradation), and better time-dependent dielectric breakdown (TDDB) properties (t_BD ) compared to devices with control thermal oxide     

Analysis of reliability characteristics of high capacitance density MIM capacitors with SiO2-HfO2-SiO2 dielectrics

In this paper, reliability as well as electrical properties of high capacitance density metal-insulator-metal (MIM) capacitor with hafnium-based dielectric is analyzed in depth. The fabricated MIM capacitor exhibits not only high capacitance density but also low voltage coefficient of capacitance (VCC) and low temperature coefficient of capacitance (TCC). It also has a low leakage current level of about ∼1 nA/cm² at room temperature and 1 V. However, it is shown that voltage linearity has a different dependence on the polarity of applied bias as temperature increases maybe due to the bulk traps between the metal electrode and high-k dielectric interface. In addition, the effect of charge trapping and de-trapping on the voltage linearity is analyzed under constant voltage stress.     

TiO_2/SiO_2、ZrO_2/SiO_2多层介质膜光学损耗及激光损伤研究

以TiO_2/SiO_2及ZrO_2/SiO_2多层介质膜为例,测试了不同工艺条件及不同膜系结构下薄膜样品的光学损耗及激光损伤阈值,同时对实验结果作了初步的分析讨论.     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

A complementary molecular-model (including field and current) for TDDB in SiO2 dielectrics

A molecular physics-based complementary model, which includes both field and current, is introduced to help resolve the E versus 1/E TDDB model controversy that has existed for many years It is shown here that either TDDB model can be valid for certain specified field, temperature, and molecular bonding-energy ranges. For bond strengths < 3eV, the bond breakage rate is generally dominated by field-enhanced thermal processes at lower fields and elevated temperatures and the E-Model is valid. At higher fields, lower temperatures and higher bond strengths the bond breakage mechanism must be hole-catalyzed and the TDDB physics is described well by the 1/E - model.However, neither the simple E-model nor 1/E-model works well for oxide thickness below t_ox< 4 run where direct tunneling effects dominate.     

Hot-carrier injections in SiO2

We review the hot-carrier injection phenomena in gate-oxide and the related degradation in silicon MOSFETs. We discuss the basic degradation mechanisms and the nature of the created defects by carrier injections through the gate-oxide. Emphasis is put on the discussion of dynamic hot-carrier injections in MOSFETs and on the stress induced leakage currents in very thin (< 5 nm) gate-oxide.     

具有SiO2/SiNX/SiO2 复合绝缘层的有机薄膜晶体管

We have investigated a SiO_2/SiN_x/SiO_2 composite insulation layer structured gate dielectric for an organic thin film transistor(OTFT) with the purpose of improving the performance of the SiO_2 gate insulator. The SiO_2/SiN_x/SiO_2 composite insulation layer was prepared by magnetron sputtering.Compared with the same thickness of a SiO_2 insulation layer device,the SiO_2/SiN_x/SiO_2 composite insulation layer is an effective method of fabricating OTFT with improved electric characteristics and decrease...     

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks

We compare charge carrier generation/trapping related degradation in control oxide (SiO₂) and HfO₂/SiO₂ stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiOSi bonds in either of the devices. We demonstrate that compared to SiO₂ devices, HfO₂ devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO₂ devices at a given operating voltage.     

Accelerated testing of SiO2 reliability

This paper compares several popular accelerated test methods for projecting SiO₂ lifetime distribution or failure rate: constant-voltage and constant-current time-to-breakdown and charge-to-breakdown tests, ramp-voltage breakdown test, and ramp-current charge to-breakdown test. Charge trapping affects the electric field acceleration parameter for time-to-breakdown and the value of breakdown voltage. Practical considerations favor ramp breakdown testing for gate oxide defect characterization. The effective thinning model is used for defect characterization and the ramp-voltage breakdown test is shown to be superior to the ramp-current Q_BD test for extraction of the defect distribution. Measurement issues are also discussed     

Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta₂O₅ films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta₂O₅ were compared. The doped Ta₂O₅ exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta₂O₅ modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.     

High-frequency time-dependent breakdown of SiO2

The time-dependent dielectric breakdown of thin oxides (8.6-11 nm) are compared under DC, pulse, and bipolar pulse conditions for frequencies up to 4 MHz. Lifetime under unipolar pulse conditions does not deviate largely from that under DC conditions; however, lifetime under bipolar stress conditions increases by a factor of 40 to 100 at frequencies above 10 kHz. The field accelerations of breakdown time are similar for DC and pulse stressing     

Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions

The substitution of the SiO₂ gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO₂ thickness. To improve the quality of the high-k/Si interface a very thin SiO₂ film is grown between both materials. In this work, HfO₂/SiO₂ stacks with different SiO₂ thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO₂ in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO₂ interfacial layer influences the advanced stages of the stack degradation.     

The doped Si/SiO2 interface

A study is reported of the influence of dopant atoms on the SiSiO₂ interface states of thermally oxidized silicon. It was found that acceptor or donor atoms induce interface states and oxide charges. The effect is largest in the case of acceptor dopants and is independent of the doping process. The influence of the dopant atoms on oxide charge is probably related to the different segregation coefficients of acceptors and donors.     

Effect of RuO2 electrode on laser-MBE prepared HfO2 gate dielectrics

In this paper, we report our recent study of the effect of RuO₂ as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO₂, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO₂ for pMOS devices. Structural, dielectric and electric properties were investigated. RuO₂/HfO₂/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm⁻¹). Compared to the SiO₂ dielectric with the same EOT value, RuO₂/HfO₂/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO₂ top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 10¹² cm⁻². All the results above indicate that RuO₂ is a promising alternative gate electrode for LMBE grown HfO₂ gate dielectrics.     

SiO2/CeO2混合磨料对硅CMP效果影响

以获得高去除速率和低表面粗糙度为目标,建立了基于纳米氧化铈-硅溶胶复配混合磨料新模式。采用小粒径、低分散度的30 nm氧化铈-硅溶胶复配混合作为磨料,利用氧化铈对硅片表面化学反应产物硅酸胺盐的强络合作用,加快了硅衬底表面化学反应进程。分析了复合磨料抛光的机理,通过Aglient 5600LS原子力显微镜,测试了抛光前后的厚度及抛光后的硅片表面微粗糙度。实验结果表明,复合磨料抛光后硅片表面在10μm×10μm范围内粗糙度方均根值0.361 nm,表面微粗糙度降低16%以上,去除率为1 680 nm/min,硅CMP速率提高8%以上,实现了高去除速率、低表面粗糙度的硅单晶抛光。     

Flat-field spectrograph in SiO2/Si

The operation of a flat-field spectrograph in silica glass on silicon (SiO₂/Si) as a demultiplexer with 4-nm channel spacing in the 1.5-μm waveguide length region is demonstrated. The concept allows fabrication tolerances to be compensated simultaneously with the adjustment of fan-out. Fiber-to-fiber insertion loss of 10.1 dB and crosstalk attenuation >15 dB have been achieved