一种基于RapidIO通信协议的64b/67b码组边界锁定设计

本文介绍了基于RapidIO通信协议的64b/67b编码技术以及67b码组的概念,并针对码组边界的锁定难题提出了一种易于实现的逻辑设计,该设计实现了将由底层Serdes接收到的乱序67bit数据重新组合,从而锁定正确的67bit数据边界的功能。使用verilog硬件描述语言实现设计,硬件功能通过仿真编译工具验证。     

实时Motion JPEG2000视频编码系统设计

介绍了基于ADV202 JPEG2000编码芯片的Motion JPEG2000视频编码系统,该系统可实现SMPTE274M的实时编码,支持失真/无失真编码,与标准完全兼容.给出了系统硬件结构和软件流程设计,提出了一种利用帧间相关性减少编码计算量的码率控制方法.     

关于传输虚拟化中数据分组乱序问题的研究

对传输虚拟化相关问题及传输虚拟化中多路径并发传输的数据分组乱序问题进行了介绍,从静态的路径选择机制以及动态的数据分组调度模型方面分析了造成接收端数据分组乱序的主要原因,提出了基于路径往返时间的路径选择机制和基于权重轮询调度算法、时延均衡技术的数据分组调度模型.理论分析和仿真实验的结果表明,所提方案能够明显地缓解接收端数据分组的乱序问题,有效地降低了接收端缓存区容量的需求.     

一种5G系统NSA模式下的PDCP分流技术

5G NSA模式下,用户数据可在分组数据汇聚协议(Packet Data Convergence Protocol, PDCP)层分流后进行双链路传输,由于各链路特性不同且动态变化,接收端存在乱序现象,导致重传、接收缓冲区阻塞。针对以上问题,提出了一种适用于双连接架构,可实现PDCP层数据聚合乱序程度最小、系统速率最大的分流方法。建立双连接触发机制,确定分流界限;基于链路传输能力和缓存队列确定分流比例,通过时延补偿控制数据发送顺序。仿真结果表明,该算法较合适分流比例算法吞吐率提升30 Mb/s,重排序丢包率降低35%;较OMS算法吞吐量提高40 Mb/s,重排序丢包率降低50%。     

基于μC/OS-Ⅱ操作系统的液晶驱动解决方案

介绍了一种基于μC/OS-Ⅱ操作系统的LCD驱动程序,给出了硬件结构和软件模块.采用文中提出的显示缓冲区 屏幕刷新的方法,完全能够实现静态文本与滚屏动画的显示功能.     

基于PCI总线的数据接收卡的实现

介绍了一种基于PCI总线的数据接收卡的设计方法实现,给出了系统的硬件电路设计,并进一步讨论了数据传输与控制的硬件实现,最后介绍了设备的软件实现方法.用该方法实现的数据接收卡成本低、结构简单.     

电力系统高速数据采集系统设计

设计了一种基于DSP与AD7656的电力系统高速数据采集系统.分析了DSP与高速AD相结合的方案原理及其在电力系统高速数据采集系统的应用方法,介绍了硬件结构原理,给出硬件设计框图和软件流程图,并研制出电力系统高速数据采集系统.     

无线数传模块的设计

讨论了基于单片机及nRF401无线数传模块的设计,并重点介绍了其硬件及软件的实现.本设计模块结构简单、数据传输可靠,可广泛应用于无线通信系统.     

32位RISC微处理器"龙腾R2"浮点流水线的设计和实现

文章介绍了32位RISC微处理器“龙腾R2”浮点处理单元的体系结构和设计，重点讨论了乱序执行、乱序、结束的高性能浮点流水线设计。为了实现流水线中的精确中断响应，本文采用了一种基于操作数指数和操作类型的浮点异常预测的方法．根据预测结果决定流水线的发射策略。基于0．18μm标准单元综合的结果表明：采用该方法实现的浮点处理流水线．与顺序控制和基于Tomasub算法实现的浮点处理单元相比，整个FPU在付出较少硬件面积的情况下得到了理想的效果．满足功能和时序要求。     

JPEG解码器IP核的设计与实现

介绍了基于静止图像压缩标准JPEG解码器IP核的设计与实现.设计采用适于硬件实现的IDCT算法结构,通过增加运算并行度和流水线技术相结合的方法以提高处理速度.根据Huffman码流特点,采用新的Huffman并行解码硬件实现结构,用简单的算术运算代替复杂的配对模式,解码速度快,硬件成本低.该IP核可方便地集成到诸如数码...     

一种针对VC1自适应大小块的反变换结构

 针对VC1的四种自适应反变换模式,文章提出了一种基于8×8块的反变换结构.利用VC1变换矩阵的对称性,通过数据块重构,四种反变换模式统一为相同的结构,大大简化了硬件设计.文章同时提出了硬件实现结构,在满足应用要求的同时,有效减小了硬件规模.实验仿真表明,在108MHz工作频率下,能够有效支持标清和高清图像实时解码的反变换运算.     

Fast and scalable lock methods for video coding on many-core architecture

Many-core processors are good candidates for speeding up video coding because the parallelism of these applications can be exploited more efficiently by the many-core architecture. Lock methods are important for many-core architecture to ensure correct execution of the program and communication between threads on chip. The efficiency of lock method is critical to overall performance of chipped many-core processor. In this paper, we propose two types of hardware locks for on-chip many-core architecture, a centralized lock and a distributed lock. First, we design the architectures of centralized lock and distributed lock to implement the two hardware lock methods. Then, we evaluate the performance of the two hardware locks and a software lock by quantitative evaluation micro-benchmarks on a many-core processor simulator Godson-T. The experimental results show that the locks with dedicated hardware support have higher performance than the software lock, and the distributed hardware lock is more scalable than the centralized hardware lock.     

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

This investigation proposes a novel radix-4² algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4² single delay feedback path (R4²SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8times8 2D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8times8 2D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 times 8 2D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mum CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.     

一种动态可重构协处理器参数化系统级模型研究

提出了参数化系统级模型.该模型不依赖于具体结构,以任务布局与重构处理分离的两级结构处理任务调用,通过参数方式实现不同设计方案的硬件结构和布局算法的配置.采用SystemC语言对模型进行了建模验证,仿真结果表明,通过指定上下文的下载、配置和执行等时间开销参数,在系统级设计空间探索中,能很好地模拟动态重构协处理器.     

基于直流无刷电机的太阳能水泵控制系统设计

基于无位置传感器永磁无刷直流电机设计了一款以STM32为主控芯片的太阳能水泵控制系统。主要介绍了硬件设计和软件设计两大部分,硬件设计包含开关逆变电路、驱动电路、电压检测电路等。软件设计包含主程序、自检程序、中断程序和故障保护程序流程。设计核心是采用MOS管内阻采样三相电流,并通过反电势过零检测法获取转子位置信号。在三相潜水泵上进行验证,相关试验波形图和数据验证了该系统硬件电路的可靠性以及软件程序架构的可行性。     

可重用AVS芯片结构软硬件协同设计

根据软硬件设计思想设计一个结构划分合理的可重用的AVS视频解码器结构.通过ARM平台软件移植,然后使用ARM ESL工具对系统模块性能进行整体评估,然后根据评估结果以及硬件实现复杂度进行软硬件结构的划分,定制软硬件模块接口,从硬件扩展考虑把硬件部分设计为与H.264解码器兼容并用SystemC模拟,最后在SOC Designer 平台做协同验证及仿真.     

H.264解码器的系统设计及CAVLC的硬件实现

设计了一种软硬件协同处理的H.264解码器系统方案,基于该方案给出CAVLC解码模块的硬件实现结构,采用有限状态机实现解码的流程控制,并对其查表部分进行优化.验证结果表明,在尽量降低硬件资源损耗的基础上,该方案能满足H.264基本框架4CIF格式图片30 f/s(帧/秒)实时解码的要求.     

Reconfigurable finite-state machine based IP lookup engine for high-speed router

Internet protocol (IP) address lookup is one of the major performance bottlenecks in high-end routers. This paper presents an architecture for an IP address lookup engine based on programmable finite-state machines (FSMs). The IP address lookup problem can be translated into the implementation of a large FSM. Our hardware engine is then used to implement this FSM using a structured approach, in which the large FSM is broken down into a set of smaller FSMs which are then mapped into reconfigurable hardware blocks. The design of our hardware engine is based on a regular and well structured architecture, which is easy to scale. Our simulation results demonstrate that the FSM based architecture can easily scale to wire speed performance at OC-192 rates. Unlike previous approaches, the performance of our architecture is not constrained by memory bandwidth and is, therefore, in principle scalable with very large scale integration technology.     

一种基于嵌入式的视频音频采集系统

给出了一种基于嵌入式硬件平台和Linux操作系统,采用MPEG4视频压缩标准和PCM音频标准的视频和音频采集系统的实现方案。通过对硬件和软件的设计实现了数据的实时压缩和采集。给出了整个系统的逻辑结构,并分别详细论述了硬件和软件的设计流程,着重介绍了如何将MPEG4视频流和PCM音频流保存成AVI格式以及如何实现格式转换的过程。