共查询到19条相似文献,搜索用时 265 毫秒
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5G NSA模式下,用户数据可在分组数据汇聚协议(Packet Data Convergence Protocol, PDCP)层分流后进行双链路传输,由于各链路特性不同且动态变化,接收端存在乱序现象,导致重传、接收缓冲区阻塞。针对以上问题,提出了一种适用于双连接架构,可实现PDCP层数据聚合乱序程度最小、系统速率最大的分流方法。建立双连接触发机制,确定分流界限;基于链路传输能力和缓存队列确定分流比例,通过时延补偿控制数据发送顺序。仿真结果表明,该算法较合适分流比例算法吞吐率提升30 Mb/s,重排序丢包率降低35%;较OMS算法吞吐量提高40 Mb/s,重排序丢包率降低50%。 相似文献
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设计了一种基于DSP与AD7656的电力系统高速数据采集系统.分析了DSP与高速AD相结合的方案原理及其在电力系统高速数据采集系统的应用方法,介绍了硬件结构原理,给出硬件设计框图和软件流程图,并研制出电力系统高速数据采集系统. 相似文献
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文章介绍了32位RISC微处理器“龙腾R2”浮点处理单元的体系结构和设计,重点讨论了乱序执行、乱序、结束的高性能浮点流水线设计。为了实现流水线中的精确中断响应,本文采用了一种基于操作数指数和操作类型的浮点异常预测的方法.根据预测结果决定流水线的发射策略。基于0.18μm标准单元综合的结果表明:采用该方法实现的浮点处理流水线.与顺序控制和基于Tomasub算法实现的浮点处理单元相比,整个FPU在付出较少硬件面积的情况下得到了理想的效果.满足功能和时序要求。 相似文献
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介绍了基于静止图像压缩标准JPEG解码器IP核的设计与实现.设计采用适于硬件实现的IDCT算法结构,通过增加运算并行度和流水线技术相结合的方法以提高处理速度.根据Huffman码流特点,采用新的Huffman并行解码硬件实现结构,用简单的算术运算代替复杂的配对模式,解码速度快,硬件成本低.该IP核可方便地集成到诸如数码... 相似文献
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《Journal of Visual Communication and Image Representation》2014,25(7):1758-1762
Many-core processors are good candidates for speeding up video coding because the parallelism of these applications can be exploited more efficiently by the many-core architecture. Lock methods are important for many-core architecture to ensure correct execution of the program and communication between threads on chip. The efficiency of lock method is critical to overall performance of chipped many-core processor. In this paper, we propose two types of hardware locks for on-chip many-core architecture, a centralized lock and a distributed lock. First, we design the architectures of centralized lock and distributed lock to implement the two hardware lock methods. Then, we evaluate the performance of the two hardware locks and a software lock by quantitative evaluation micro-benchmarks on a many-core processor simulator Godson-T. The experimental results show that the locks with dedicated hardware support have higher performance than the software lock, and the distributed hardware lock is more scalable than the centralized hardware lock. 相似文献
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Chin-Teng Lin Yuan-Chu Yu Lan-Da Van 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(8):1058-1071
This investigation proposes a novel radix-42 algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-42 single delay feedback path (R42SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8times8 2D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8times8 2D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 times 8 2D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mum CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices. 相似文献
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提出了参数化系统级模型.该模型不依赖于具体结构,以任务布局与重构处理分离的两级结构处理任务调用,通过参数方式实现不同设计方案的硬件结构和布局算法的配置.采用SystemC语言对模型进行了建模验证,仿真结果表明,通过指定上下文的下载、配置和执行等时间开销参数,在系统级设计空间探索中,能很好地模拟动态重构协处理器. 相似文献
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Desai M. Gupta R. Karandikar A. Saxena K. Samant V. 《Selected Areas in Communications, IEEE Journal on》2003,21(4):501-512
Internet protocol (IP) address lookup is one of the major performance bottlenecks in high-end routers. This paper presents an architecture for an IP address lookup engine based on programmable finite-state machines (FSMs). The IP address lookup problem can be translated into the implementation of a large FSM. Our hardware engine is then used to implement this FSM using a structured approach, in which the large FSM is broken down into a set of smaller FSMs which are then mapped into reconfigurable hardware blocks. The design of our hardware engine is based on a regular and well structured architecture, which is easy to scale. Our simulation results demonstrate that the FSM based architecture can easily scale to wire speed performance at OC-192 rates. Unlike previous approaches, the performance of our architecture is not constrained by memory bandwidth and is, therefore, in principle scalable with very large scale integration technology. 相似文献