Design and implementation of a reliable and authenticated satellite image communication

According to the need for having a confident and secure communication of satellite images with minimum tolerable delay, a novel method is presented here as a design and implementation of modern techniques. This paper turns around novel algorithms, building systems with higher performance using multi-resolution decomposition. Computation and implementation of watermarking and compression are the main issues of this research. We used Discrete Wavelet Transform (DWT) as a basic tool along by compression and watermarking of satellite images. This is due to the fact that DWT supports features like progressive image transmission. Lifting-based scheme which often requires less computation resources has been used for constructing bi-orthogonal wavelet calculation cores. We used ModelSim to build the simulation results of the implemented structures described in VHDL.     

An Efficient VLSI Architecture for the Computation of 1-D Discrete Wavelet Transform

This paper presents a new architecture for VLSI implementation of the one dimensional Discrete Wavelet Transform (DWT). The architecture uses single filter for generation of both the DWT coefficients and scaling function for orthogonal wavelets as opposed to the conventional two filter approach. For multilevel decomposition, the fold back architecture principle, which interleaves the decimated scaling function back into the filter for subsequent levels, is applied. Limited use of memory in the design enables efficient implementation of the DWT computation in VLSI.     

Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations

This paper proposes two JPEG 2000 compliant architectures: one for DWT (Discrete Wavelet Transform) and one for IWT (Integer Wavelet Transform) implementation. First of all some theoretical issues about DWT and IWT are discussed, then, starting from transforms characteristics, the architectures are presented showing both performance and cost. In the literature many DWT architectures have been proposed; our implementation is a new architecture that computes the DWT using filters of interest for the forthcoming JPEG 2000 standard. Moreover, we propose a Lifting Scheme based architecture for IWT, JPEG 2000 compliant too. The proposed architectures are able to support real-time streams: the DWT one, which is made of 20,000 cells, with an input throughput of 160 Msamples per second and a clock frequency of 160 MHz, the IWT one, consisting of 50,000 cells, with an input throughput of 4.5 Msamples per second and an internal clock frequency of 108 MHz.     

JPEG2000小波变换器的VLSI结构设计

新一代静止图像压缩标准JPEG2000将离散小波变换(DWT)作为其核心变换技术,并推荐采用推举体制(lifting)快速算法来实现.空间组合推举体制算法(SCLA)大大降低了lifting的运算量.当选用9/7小波滤波器时,SCLA的乘法运算量只有lifting的7/12.本文提出了一种实现SCLA算法的VLSI结构,降低了基于lifting实现的运算量, 加快了变换的速度,减小了电路的规模.本文的二维正反小波变换器已经作为单独的IP核应用于我们目前正在开发的JPEG2000图像编解码芯片中.     

DWT based HMM for face recognition

A novel Discrete Wavelet Transform (DWT) based Hidden Markov Module (HMM) for face recognition is presented in this letter. To improve the accuracy of HMM based face recognition algorithm, DWT is used to replace Discrete Cosine Transform (DCT) for observation sequence ex- traction. Extensive experiments are conducted on two public databases and the results show that the proposed method can improve the accuracy significantly, especially when the face database is large and only few training images are available.     

离散小波变换的一种硬件实现

利用带状矩阵乘法技术 ,完成了新型的离散小波变换的一种硬件实现 ,并用 Verilog语言验证了设计方法。利用该方法可以大大增加设计的通用性。     

A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform

In this paper, an efficient semi-systolic array architecture for separable 2-D Discrete Wavelet Transform (DWT) is introduced. The semi-systolic array is applicable to any convolution that requires an arbitrary subsampling function. The semi-systolic array presents a better implementation of the convolution function of DWT. This kind of implementation offers a higher efficiency compared to regular systolic implementation when applied for 2-D DWT. The architecture has an efficiency of at least 91% which increases proportional to the number of octaves with no change in the architecture design except for minor modifications to the control logic and memory size. The propose architecture is scalable for different size of filter and different number of octave. The communication routing is minimum since data transfers are limited to immediate neighboring processors. The components of the architecture are fairly regular and consist of minimum number of computational units which makes it a good candidate for VLSI implementation.     

小波图像编码的硬件实现

设计了二维离散小波变换和快速零树编码的硬件结构,实现了一小波图像编码系统.编写了各个模块的Verilog HDL模型,并进行了仿真和逻辑综合.最后用Altera公司的CPLD对整个编码系统进行了验证.结果表明,设计的硬件结构是正确的,可以用来实现小波图像编码系统.     

一种基于提升的二维离散小波变换VLSI架构

离散小波变换(Discrete Wavelet Transform,DWT)需要较多的运算量以及较大的存储器空间,为了使之适用于实时的图像处理应用,就需要开发特殊的架构和芯片来提高离散小波变换的运算性能。基于提升的二维DWT提出了一种新型的VLSI结构——LLSP架构,其结合逐级和基于行的架构这两者特点,带来了硬件开销和存储器空间的降低,并可以用于多提升步骤的扩展以及多级二维离散小波变换。     

A fast Discrete Wavelet Transform algorithm for visual processing applications

For visual processing applications, the two-dimensional (2-D) Discrete Wavelet Transform (DWT) can be used to decompose an image into four-subband images. However, when a single band is required for a specific application, the four-band decomposition demands a huge complexity and transpose time. This work presents a fast algorithm, namely 2-D Symmetric Mask-based Discrete Wavelet Transform (SMDWT), to address some critical issues of the 2-D DWT. Unlike the traditional DWT involving dependent decompositions, the SMDWT itself is subband processing independent, which can significantly reduce complexity. Moreover, DWT cannot directly obtain target subbands as mentioned, which leads to an extra wasting in transpose memory, critical path, and operation time. These problems can be fully improved with the proposed SMDWT. Nowadays, many applications employ DWT as the core transformation approach, the problems indicated above have motivated researchers to develop lower complexity schemes for DWT. The proposed SMDWT has been proved as a highly efficient and independent processing to yield target subbands, which can be applied to real-time visual applications, such as moving object detection and tracking, texture segmentation, image/video compression, and any possible DWT-based applications.     

双树复小波变换及其应用综述

双树复小波变换是为克服通常的离散小波变换的缺陷而提出的。当对应小波基（近似）满足Hilbert变换关系时，双树复小波变换能够极大地减小通常的实小波变换中的平移敏感性，改善方向选择性。这些优点使双树复小波变换成为有效的图像配准融合工具，能够显著提高配准融合质量。     

提升格式的小波变换及在视频压缩中的应用

提升方法是计算离散小波变换的有效手段，将提升三维小波变换用于视频信号压缩。时间方向小渡变换选用Haar滤波器组，空间小波变换则在常规的图像编码所常用的D9/7滤波器组基础上，对其参数进行调整，进一步减少运算量。实验表明这种调整取得了与D9/7双正交小波基本一致图像编码效果，但提高了运算速度。     

多分辨率下的彩色图像分割方法

通过对彩色图像分割方法的研究,提出一种在多分辨率条件下彩色图像的分割方法。通过离散小波变换获得原始图像的低分辨率近似,并利用分水岭算法对低分辨率近似图像进行初始分割。对初始分割区域根据颜色信息和空间关系按照一定的先后顺序进行合并,直到形成理想的分割结果。对合并后的图像应用小波逆变换得到原始分辨率下的分割结果。在低分辨率下进行的分割和合并大大减小了计算量,提高了分割速度。     

多级多维离散小波变换的快速提升计算

提升方法是计算离散小波变换的有效手段,它由一系列的提升步和拉伸变换组成.在计算多级和多维离散小波变换时,现有方法在每一次小波分解的过程中都做完整的提升步计算和拉伸变换计算.我们发现该方法存在运算过程的冗余,为此本文提出了一种称之为后拉伸变换的提升方法,基本思想是计算完所有的提升步后,再统一进行拉伸变换.它能减少离散小波变换的乘法运算量.例如,对图像与视频压缩中应用广泛的Daubechies 9/7小波,做一维5级分解时与现有方法相比,乘法运算减少20%,而二维5级分解时,乘法运算减少28%.     

一个优化小波块量化矩阵的算法

小波变换以其良好的空间－频率局部特性,在图像编码标准JPEG2000和MPEG4中占据了重要位置.本文选用正交小波基对图像做小波变换,然后重新组织小波系数成小波块,最后提出了一个构造小波块量化矩阵以产生最优比特分配的算法.本算法用一种新的方式统计小波系数分布,并结合人体视觉系统的特点,采用动态策略在很大的比特率范围内产生最优的小波块量化矩阵.     

一种DWT与DCT相结合的音频数字水印技术

提出了一种将离散小波变化与离散余弦变换相结合的音频数字水印技术。利用离散小波变换的多分辨率特性和离散余弦变换的能量压缩能力,通过修改变换域的低中频系数,把降维后的二值图像嵌入到原始数字音频信号中。该算法可同时应用两种变换,而且嵌入和提取水印的方法简单。实验结果表明该算法水印不易破坏,对数字音频信号的低通滤波、叠加噪声等攻击均具有很好的隐蔽性和稳健性。     

Parallel pipeline implementation of wavelet transforms

Wavelet transforms have been one of the important signal processing developments in the last decade, especially for applications such as time-frequency analysis, data compression, segmentation and vision. Although several efficient implementations of wavelet transforms have been derived, their computational burden is still considerable. The paper describes two generic parallel implementations of wavelet transforms, based on the pipeline processor farming methodology, which have the potential to achieve real-time performance. Results show that the parallel implementation of the oversampled wavelet transform achieves virtually linear speedup, while the parallel implementation of the discrete wavelet transform (DWT) also outperforms the sequential version, provided that the filter order is large. The DWT parallelisation performance improves with increasing data length and filter order, while the frequency-domain implementation performance is independent of wavelet filter order. Parallel pipeline implementations are currently suitable for processing multidimensional images with data length at least 512 pixels     

Simplified biorthogonal discrete wavelet transform for VLSI architecture design

Biorthogonal discrete wavelet transform (BDWT) has gained general acceptance as an image processing tool. For example, the JPEG2000 standard is completely based on the BDWT. In BDWT, the scaling (low-pass) and wavelet (high-pass) filters are symmetric and linear phase. In this work we show that by using a specific sign modulator the BDWT filter bank can be realized by only two biorthogonal filters. The analysis and synthesis parts use the same scaling and wavelet filters, which simplifies especially VLSI designs of the biorthogonal DWT/IDWT transceiver units. Utilizing the symmetry of the scaling and the wavelet filters we introduce a fast convolution algorithm for implementation of the filter modules. In multiplexer–demultiplexer VLSI applications both functions can be constructed via two running BDWT filters and the sign modulator. This work was supported by the National Technology Agency of Finland (TEKES).     

Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs

The suitability of the 2D Discrete Wavelet Transform (DWT) as a tool in image and video compression is nowadays indisputable. For the execution of the multilevel 2D DWT, several computation schedules based on different input traversal patterns have been proposed. Among these, the most commonly used in practical designs are: the row–column, the line-based and the block-based. In this work, these schedules are implemented on FPGA-based platforms for the forward 2D DWT by using a lifting-based filter-bank implementation. Our designs were realized in VHDL and optimized in terms of throughput and memory requirements, in accordance with the principles of both the schedules and the lifting decomposition. The implementations are fully parameterized with respect to the size of the input image and the number of decomposition levels. We provide detailed experimental results concerning the throughput, the area, the memory requirements and the energy dissipation, associated with every point of the parameter space. These results demonstrate that the choice of the suitable schedule is a decision that should be dependent on the given algorithmic specifications.