CMOS电路IDDQ测试电路设计

针对CMOS集成电路的故障检测,提出了一种简单的IDDQ静态电流测试方法,并对测试电路进行了设计。所设计的IDDQ电流测试电路对CMOS被测电路进行检测,通过观察测试电路输出的高低电平可知被测电路是否存在物理缺陷。测试电路的核心是电流差分放大电路,其输出一个与被测电路IDDQ电流成正比的输出。测试电路串联在被测电路与地之间,以检测异常的IDDQ电流。测试电路仅用了7个管子和1个反相器,占用面积小,用PSpice进行了晶体管级模拟,实验结果表明了测试电路的有效性。     

CMOS集成电路瞬态电流片外电流传感器电路

瞬态电流(IDDT)测试经常被看作是静态电流(IDDQ)测试的替代或补充,特别在深亚微米技术中,受到越来越多的关注。根据一种基于电荷的瞬态电流片外电流传感器电路,并在其基础上进行改进并对两阶多米诺加法器电路进行仿真实验,实验结果表明,改进后的电路能有效读取集成电路中的瞬态电流,从而实现瞬态电流的测试。     

裸芯片的IDDQ测试筛选方法研究

IDDQ测试在裸芯片的测试筛选中非常有用,为了获得更高质量与可靠性的产品,许多公司在CMOS生产线中引入了IDDQ测试筛选技术,现在IDDQ测试筛选技术已经作为保证芯片可靠性的重要手段。本文介绍了IDDQ测试筛选技术的重要概念以及其在保证裸芯片可靠性方面的重要作用,并对深亚微米器件中的IDDQ测试筛选方法做了重点介绍。     

基于V93000 ATE的大电流测试方法研究

在当今超大规模集成电路的设计中,特别是在系统芯片SOC设计中,大电流电路已经非常普遍。实现对大电流电路的测试是集成电路测试中一个十分重要的内容。V93000集成电路测试系统是一款可扩展型平台,它集合了数字测试、模拟测试和射频测量等资源。通用性的电源供电资源可实现最大到100 A的电流测试。     

QTAG：静态电流标准监控器的研究进展

为了准备1995年国际测试会议(ITC),质量测试工作组(QTAG)将要正式通过一个静态电流测试(I_(DDQ))的标准监控器。本文说明了QTAG的背景,描述了该工作组在开发和评估新的电流监控器电路时所面临的挑战。本文还提供了几种可能的解决方案。     

0.13μm DSP芯片静态电流测试失效分析研究

静态电流(IDDQ)测试是一种很灵敏且具有成本效益的集成电路测试技术,针对0.13μm某种DSP芯片在量产初期所遇到的IDDQ测试失效情况,利用激光束诱导电阻值变化(OBIRCH)、电压对比(VC)、扫描电镜(SEM)和聚焦离子束(FIB)等电学与物理失效分析方法,确定由离子注入偏差所引起的MOS器件物理缺陷是造成IDDQ失效的原因,据此进行了离子注入光阻的工艺改进,最终实现了成品率的提升.     

CMOS IC漏极静态电流测试技术的现状与发展

全面介绍了CMOS集成电路漏极静态电流(IDDQ)测试技术的现状、应用及其发展趋势。与其它主要用于检测逻辑功能的测试技术不同，IDDQ主要用于检测电路的物理缺陷和工艺故障。作为逻辑功能测试的重要补充，IDDQ技术可提高集成电路的可测性和故障覆盖率，保证集成电路的可靠性。     

基于高精度电压／电流LEM模块的双通道传感器测试电源

简要介绍了电压／电流传感器测试电源的用途及应用场合，针对常规电压和电流传感器的特点，采用高精度电压／电流LEM模块为基准源，设计了一种双通道隔离型主电路拓扑及控制系统（并留有上位机控制和检测端口），并给出了该电源的技术参数。试验结果表明，该电源可以用于传感器的标定、多传感器一致性检测等方面。     

一种用于A/D转换器的低电压CMOS带隙电压基准源

设计了一种在1V电压下正常工作的用于A/D转换器的低功耗高精度的CMOS带隙电压基准.电路主要包括了一个带隙基准和一个运放电路,而且软启动电路不消耗静态电流.电路采用0.18μm CMOS工艺设计.仿真结果显示,温度从-40~125°C,温度系数约为1.93ppm/°C,同时电源抑制比在10kHz时为38.18dB.电源电压从0.9V到3.4V变化时,输出电压波动保持在0.17%以内;电路消耗总电流为5.18μA.     

面向电源噪声的动态电流测试

电源噪声在深亚微米设计中正变得越来越突出，而因电源噪声引起的电路故障测试也变得越来越重要。本文针对这一情况提出了动态电流测试来实现由电源噪声引起的故障测试。与IddQ测试不同，动态电流测试依据电路中的器件切换时电源电流的动态变化情况来判断电路中是否存在故障。通过仿真分析，动态电流测试是可行的。     

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits

In order to reduce IDDQ testing time, it is important to reduce the number of IDDQ measurement vectors, because IDDQ measurement is a time-consuming process. For obtaining minimum number of IDDQ measurement vectors for sequential circuits, fault simulation needs to be performed without fault-dropping, thus requiring very high simulation time. In this paper we propose algorithms to select small number of IDDQ measurement vectors. The proposed algorithms can concurrently simulate multiple faults and use heuristics for selection of IDDQ measurement vectors to reduce simulation time. Experimental results are presented to demonstrate the effectiveness of the proposed method.     

基于扫描的集成电路故障诊断技术

随着集成电路技术的飞速发展,人们对集成电路产品的可靠性要求越来越高,这就要求集成电路测试特别是故障诊断提出了更高的要求.基于扫描的故障诊断方法是广泛应用的故障诊断方法之一.介绍基于扫描的集成电路故障诊断方法,并详细介绍了一种改进的扫描诊断方法和一种基于扫描的全速诊断方法.     

Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing

In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 × 10⁷ gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.     

IDDQ测试原理及案例

概论IDDQ测试的演进规律,详解一个芯片IDDQ实测案例,包括测试平台、软件框图和数据分析。     

Current Testing Procedure for Deep Submicron Devices

This paper presents a test technique that employs two different supply voltages for the same IDDQ pattern. The results of the two measurements are subtracted in order to eliminate the inherent sub-threshold leakage. Summary of the experiment carried out on System on a Chip (SOC) device build in 0.35 technology is also shown. These experiments proved that the method is effective in detecting failures not detectable with the single limit IDDQ.     

一种检测冗余故障的瞬态电流测试方法

数字电路中的冗余故障是不能被传统的电压测试方法(VoltageTesting)和稳态电流测试方法(IDDQTest-ing)检测出来的。根据瞬态电流测试(IDDQTesting)的思想,提出一种检测冗余故障的方法,该方法利用扇出重汇聚结构当中从扇出点到重汇聚点的不同路径的延迟差,在重汇聚点形成冒险,以激活故障并进行传播。实验表明,此方法能够有效地检测冗余故障。     

Current monitoring circuit for fault detection in CMOS integrated circuit

This article presents a built-in current sensor (BICS), which detects faults using the current testing technique in CMOS integrated circuits. This circuit employs cross-coupled PMOS transistors, which are used as current comparators. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applied to deep sub-micron processes. The validity and effectiveness are verified through the HSPICE simulation on circuits with faults. The entire area of the test chip is 116×65 μm². The BICS occupies only 41×17 μm² of the area of the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 μm 2-poly-4-metal N-well CMOS process.     

Multi-VDD Testing for Analog Circuits

We present industrial results of a quiescent current testing technique suitable for RF testing. The operational method consists of ramping the power supply and of observing the corresponding quiescent current signatures. When the power supply is swept, all transistors are forced into various regions of operation. This has as advantage that the detection of faults is done for multiple supply voltages and corresponding quiescent currents, enhancing in this form the detectability of faults. We found that this method of structural testing yields fault coverage results comparable to functional RF tests making it a potential and attractive technique for production wafer testing due to its low cost, low testing times and low frequency requirements.José Pineda de Gyvez received the Ph.D. degree from the Eindhoven University of Technology. He is currently a principal scientist at Philips Research Laboratories, The Netherlands. Dr. Pineda was Associate Editor in IEEE Transactions on Circuits and Systems Part I and also Associate Editor for Technology in IEEE Transactions on Semiconductor Manufacturing. His research interests are in the general areas of design for manufacturability and analog signal processing.Guido Gronthoud received the electrical engineering degree from the Delft University in 1975. From 1976 to 1980 he worked at the Delft University on the design of Microwave systems. From 1980 he works with Philips. He has been working in the fields of circuit simulation and modelling for IC designs, CAD development for PCB design and electronic circuits and systems reliability. Since 1998 he is working on test innovation of digital and mixed-signal circuits. His interests are Defect Oriented Test, fault modeling and Process Related Test. He has authored and co-authored technical papers.     

IDDT Testing versus IDDQ Testing

IDDQ testing has progressed to become a worldwide accepted test method to detect CMOS IC defects. However, it is noticed that observing the average transient current can lead to improvements in real defect coverage, which is referred to IDDT testing. This letter presents a formal procedure to identify IDDT testable faults, and to generate input vector pairs to detect the faults based on Boolean process. It is interesting to note that those faults may not be detected by IDDQ or other test methods, which shows the significance of IDDT testing.