HALO结构pMOSFETs在Vg=Vd/2应力模式下应力相关的热载流子退化

研究了超薄栅(2.5nm)短沟HALO-pMOSFETs在Vg=Vd/2应力模式下不同应力电压时热载流子退化特性.随着应力电压的变化,器件的退化特性也发生了改变.在加速应力下寿命外推方法会导致过高地估计器件寿命.在高场应力下器件退化是由空穴注入或者电子与空穴复合引起的,随着应力电压的下降器件退化主要是由电子注入引起的.最后,给出了两种退化机制的临界电压并在实验中得到验证.     

在Vg=Vd/2应力模式下2.5nm氧化层pMOSFETs的新寿命预测模型

研究了2 .5 nm超薄栅短沟p MOSFETs在Vg=Vd/ 2应力模式下的热载流子退化机制及寿命预测模型.栅电流由四部分组成:直接隧穿电流、沟道热空穴、一次碰撞电离产生的电子注入、二次碰撞电离产生的空穴注入.器件退化主要是由一次碰撞产生的电子和二次碰撞产生的空穴复合引起.假设器件寿命反比于能够越过Si- Si O2 界面势垒的二次碰撞产生的二次空穴数目,在此基础上提出了一个新的模型并在实验中得到验证.     

在Vg=Vd/2应力模式下2.5nm氧化层pMOSFETs的新寿命预测模型

研究了2.5nm超薄栅短沟pMOSFETs在Vg=Vd/2应力模式下的热载流子退化机制及寿命预测模型.栅电流由四部分组成:直接隧穿电流、沟道热空穴、一次碰撞电离产生的电子注入、二次碰撞电离产生的空穴注入.器件退化主要是由一次碰撞产生的电子和二次碰撞产生的空穴复合引起.假设器件寿命反比于能够越过Si-SiO2界面势垒的二次碰撞产生的二次空穴数目,在此基础上提出了一个新的模型并在实验中得到验证.     

GaAs PHEMT器件的退化特性及可靠性表征方法

测量了应力前后GaAs PHEMT器件电特性的退化,指出了GaAs PHEMT阈值电压的退化由两个原因引起.栅极下AlGaAs层深能级的空穴积累可以解释阈值电压漂移中暂时性的、可恢复的那部分,积累在栅金属与半导体之间界面层的空穴可以解释阈值电压漂移中永久性的漂移.空穴积累来源于场助作用下电子的退陷和沟道中碰撞电离产生的空穴向栅极流动时被俘获.对高场下碰撞电离率的实验曲线进行拟合,得到碰撞电离率与器件沟道电场峰值的量化关系,可以对GaAs PHEMT器件的电性能和可靠性进行评估.     

GaAs PHEMT器件的退化特性及可靠性表征方法

测量了应力前后Ga As PHEMT器件电特性的退化,指出了Ga As PHEMT阈值电压的退化由两个原因引起.栅极下Al Ga As层深能级的空穴积累可以解释阈值电压漂移中暂时性的、可恢复的那部分,积累在栅金属与半导体之间界面层的空穴可以解释阈值电压漂移中永久性的漂移.空穴积累来源于场助作用下电子的退陷和沟道中碰撞电离产生的空穴向栅极流动时被俘获.对高场下碰撞电离率的实验曲线进行拟合,得到碰撞电离率与器件沟道电场峰值的量化关系,可以对Ga As PHEMT器件的电性能和可靠性进行评估     

脉冲应力增强的NMOSFET's热载流子效应研究

 本文研究了交流应力下的热载流子效应,主要讨论了脉冲应力条件下的热空穴热电子交替注入对NMOSFET's的退化产生的影响.在脉冲应力下,阈值电压和跨导的退化增强.NMOSFET's在热空穴注入后,热电子随后注入时,会有大的退化量,这可以用中性电子陷阱模型和脉冲应力条件下热载流子注入引起的栅氧化层退化来解释.本文还定量分析研究了NMOSFET's退化与脉冲延迟时间和脉冲频率的关系,并且给出了详细的解释.在脉冲应力条件下,器件的热载流子退化是由低栅压下注入的热空穴和高栅压下热电子共同作用的结果.     

脉冲应力增强的NMOSFET′s热载流子效应研究

本文研究了交流应力下的热载流子效应 ,主要讨论了脉冲应力条件下的热空穴热电子交替注入对NMOSFET′s的退化产生的影响 .在脉冲应力下 ,阈值电压和跨导的退化增强 .NMOSFET′s在热空穴注入后 ,热电子随后注入时 ,会有大的退化量 ,这可以用中性电子陷阱模型和脉冲应力条件下热载流子注入引起的栅氧化层退化来解释 .本文还定量分析研究了NMOSFET′s退化与脉冲延迟时间和脉冲频率的关系 ,并且给出了详细的解释 .在脉冲应力条件下 ,器件的热载流子退化是由低栅压下注入的热空穴和高栅压下热电子共同作用的结果     

漏雪崩应力下热载流子注入引起的MOSFET退变特性研究

本文对亚微米MOSFET在漏雪崩恒流应力(DAS)条件下热载流子注入引起的退变现象做了实验研究。实验结果表明:在一般的恒流应力条件下,栅氧化层中由空穴注入形成的空穴陷阱电荷对器件特性起主要影响作用。恒流应力过程中,任何附加的电子注入都可使器件退变特性发生明显变化,实验结果还证实,漏雪崩应力期间形成的空穴陷阱电荷可明显降低器件栅氧化层的介质击穿特性。     

衬底负偏置对FLASH器件耐久性退化的影响

研究了ETOXTM结构FLASH memory单元器件在VFG≈VD/2的热载流子写入应力条件下,衬底负偏置对单元器件耐久性退化的影响.结果表明:在既定的栅、漏偏置条件下,随着衬底负偏置的增加,器件耐久性退化会出现极小值.综合考虑了器件耐久性退化以及写入效率两方面的要求以后,确定了在VFG≈VD/2热载流子写入应力模式下,FLASH memory单元器件具有增强写入效率以及最小耐久性退化的最佳衬底负偏置条件.     

衬底负偏置对FLASH器件耐久性退化的影响

研究了ETOXTM结构FLASH memory单元器件在VFG≈VD/2的热载流子写入应力条件下,衬底负偏置对单元器件耐久性退化的影响.结果表明:在既定的栅、漏偏置条件下,随着衬底负偏置的增加,器件耐久性退化会出现极小值.综合考虑了器件耐久性退化以及写入效率两方面的要求以后,确定了在VFG≈VD/2热载流子写入应力模式下,FLASH memory单元器件具有增强写入效率以及最小耐久性退化的最佳衬底负偏置条件.     

The determination of impact ionization coefficients in ln0.2Ga0.8As/GaAs strained-layer superlattice mesa photodiodes

Sandia National Laboratories, Albuquerque, NM 87185 Photocurrent multiplication measurements have been performed on two different In_0.2Gao_0.8As/GaAs strained-layer superlattice (SLS)p ⁺n photodiode structures which are designed to permit simultaneous injection of electrons and holes. Initial devices were found to suffer from low quantum efficiencies produced by small electron diffusion lengths as well as mixed injection caused by lower than expected optical absorption coefficients in the SLSn ⁺ contact layers for hole injection conditions. Using a second device structure having a thicker n⁺ contact region, the electron multiplication factors are found to be larger than that of holes with a ratio of the electron to hole ionization coefficient of 1.4 for fields between 2.9 and 3.4 x 10⁵V/cm.     

SOI NLIGBT热载流子效应研究

SOI NLIGBT中热载流子效应分别通过直流电压的应力测试、TCAD仿真和电荷泵测试三种方法进行了研究。其中,不同直流电压应力条件下测得的衬底电流Isub和导通电阻Ron用来评估因热载流子效应引起的器件退化程度。为了进行理论分析,对器件内部的电场强度和碰撞离化率也进行了仿真。测试得到的电荷泵电流直接验证了器件表面的损伤程度。最后讨论了SOI LIGBT在不同栅压条件下的退化机制。     

Degradation Characteristics of n- and p-Channel Polycrystalline-Silicon TFTs Under CMOS Inverter Operation

The degradation characteristics of n- and p-channel polysilicon thin-film transistors (TFTs) under circuit operation were investigated by using CMOS inverter circuits consisting of n-channel TFTs with a lightly doped drain (LDD) structure and p-channel TFTs with a single-drain (SD) structure. A new test element made it possible to separately evaluate the degradation characteristics of each type of TFT during CMOS inverter operation. In regard to n-channel LDD TFTs, the device degradation is mainly caused by accumulated dc stress under the condition that the gate voltage is near the threshold voltage and the high drain voltage, i.e., the drain-avalanche hot-carrier (DAHC) stress condition. In p-channel SD TFTs, the device degradation is caused by the mutual interaction between DAHC stress and negative-bias-temperature (NBT) stress. Hole injection due to NBT stress is accelerated by DAHC-stress-induced trapped electrons under inverter-circuit operation. The effect is thus enhanced not only by the increase in the number of hole injections but also by the increase in the number of electron injections. It was found that the device characteristics of p-channel TFTs are more rapidly degraded as the rising time of the input pulse becomes shorter. This degradation is caused by the transient increase in the number of hot electrons, which are generated when holes are emitted from the trap states when the p-channel TFTs are turned off.      

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.     

Degradation of bipolar transistor current gain by hot holes duringreverse emitter-base bias stress

Experimental evidences are given which demonstrate that degradation of the common-emitter forward current gain h_FE of submicron silicon npn bipolar transistors at low reverse emitter-base junction applied voltage is caused by primary hot holes of the n⁺ /p emitter tunneling current rather than secondary hot electrons generated by the hot holes or thermally-generated hot electrons. Experiments also showed similar kinetic energy dependence of the generation rate of oxide/silicon interface traps by primary hot electrons and primary hot holes. Significant h_FE degradation was observed at stress voltages less than 2.4 V     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds