A 2.2-mW CMOS bandpass continuous-time multibit /spl Delta/-/spl Sigma/ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications

A delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter featuring 68-dB dynamic range and 64-dB signal-to-noise ratio in a 1-MHz bandwidth centered at an intermediate frequency of 2 MHz with a 48-MHz sample rate is reported. A second-order continuous-time modulator employing 4-bit quantization is used to achieve this performance with 2.2 mW of power consumption from a 1.8-V supply. The modulator including references occupies 0.36 mm/sup 2/ of die area and is implemented in a 0.18-/spl mu/m five-metal single-poly digital CMOS process.     

A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-/spl mu/m CMOS

A high-resolution multibit sigma-delta analog-to-digital converter (ADC) implemented in a 0.18-/spl mu/m CMOS technology is introduced. The circuit is targeted for an asymmetrical digital subscriber line (ADSL) central-office (CO) application . An area- and power-efficient realization of a second-order single-loop 3-bit modulator with an oversampling ratio of 96 is presented. The /spl Sigma//spl Delta/ modulator features an 85-dB dynamic range over a 300-kHz signal bandwidth. The measured power consumption of the ADC core is only 15 mW. An innovative biasing circuitry is introduced for the switched-capacitor integrators.     

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

This paper describes a third-order sigma-delta (/spl Sigma//spl Delta/) modulator that is designed and implemented in 0.18-/spl mu/m CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm/sup 2/ silicon area.     

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.     

Integrated stereo /spl Delta//spl Sigma/ class D amplifier

A 2/spl times/40 W class D amplifier chip is realized in 0.6-/spl mu/m BCDMOS technology, integrating two delta-sigma (/spl Delta//spl Sigma/) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency.     

Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time /spl Sigma//spl Delta/ ADC

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-/spl mu/m BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (/spl Sigma//spl Delta/) ADC has 84-dB dynamic range over a total bandwidth of /spl plusmn/135 kHz for an active area of 0.4 mm/sup 2/. Hence, most of the channel filtering is realized in a CMOS IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm/sup 2/.     

A CMOS smart temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.5/spl deg/C from -50/spl deg/C to 120/spl deg/C

A low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 /spl mu/m CMOS process. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. To obtain a high initial accuracy in the readout circuitry, chopper amplifiers and dynamic element matching are used. High linearity is obtained by using second-order curvature correction. With these measures, the sensor's temperature error is dominated by spread on the base-emitter voltage of the PNP transistors. This is trimmed after packaging by comparing the sensor's output with the die temperature measured using an extra on-chip calibration transistor. Compared to traditional calibration techniques, this procedure is much faster and therefore reduces production costs. The sensor is accurate to within /spl plusmn/0.5/spl deg/C (3/spl sigma/) from -50/spl deg/C to 120/spl deg/C.     

A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping

Direct digital synthesis of signals in the hundreds of megahertz can lead to simpler, smaller transceivers, free of images and LO feedthrough that plague systems requiring analog upconversion. We present a 3-bit, 2 GS/s, /spl Delta//spl Sigma/-modulated DAC in InP HBT technology. The DAC is linearized using bandpass mismatch shaping. The mismatch shaper uses seven tunable 1.5-bit discrete-time bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. These /spl Delta//spl Sigma/ modulators operate in the analog domain to decrease system complexity and power consumption. The mismatch-shaped DAC can generate narrowband signals between 250-750 MHz with >68 dB SNR in a 1-MHz bw, >74-dB SFDR, and <-80-dBc intermodulation distortion with an 8.1-W power consumption.     

Integrated high-/spl kappa/ (/spl kappa/ /spl sim/19) MIM capacitor with Cu/low-/spl kappa/ interconnects for RF application

We demonstrate a high-performance metal-high /spl kappa/ insulator-metal (MIM) capacitor integrated with a Cu/low-/spl kappa/ backend interconnection. The high-/spl kappa/ used was laminated HfO/sub 2/-Al/sub 2/O/sub 3/ with effective /spl kappa/ /spl sim/19 and the low-/spl kappa/ dielectric used was Black Diamond with /spl kappa/ /spl sim/2.9. The MIM capacitor (/spl sim/13.4 fF//spl mu/m/sup 2/) achieved a Q-factor /spl sim/53 at 2.5 GHz and 11.7 pF. The resonant frequency f/sub r/ was 21% higher in comparison to an equivalently integrated Si/sub 3/N/sub 4/-MIM capacitor (/spl sim/0.93 fF//spl mu/m/sup 2/) having similar capacitance 11.2 pF. The impacts of high-/spl kappa/ insulator and low-/spl kappa/ interconnect dielectric on the mechanism for resonant frequency improvement are distinguished using equivalent circuit analysis. This letter suggests that integrated high-/spl kappa/ MIM could be a promising alternative capacitor structure for future high-performance RF applications.     

6-k/spl Omega/ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range

A high-gain, 43-Gb/s InP HBT transimpedance-limiting amplifier (TIALA) with 100-/spl mu/A/sub pp/ sensitivity and 6 mA/sub pp/ input overload current is presented. The circuit also operates as a limiting amplifier with 40-dB differential gain, better than 15-dB input return loss, and a record-breaking sensitivity of 8 mV/sub pp/ at 43 Gb/s. It features a differential TIA stage with inductive noise suppression in the feedback network and consumes less than 450mW from a single 3.3-V supply. The TIALA has 6-k/spl Omega/ (76dB/spl Omega/) differential transimpedance gain and 35-GHz bandwidth and comprises the transimpedance and limiting gain functions, an auto-zero dc feedback circuit, signal level monitor, and slicing level adjust functions. Other important features include 45-dB isolation and 800-mV/sub pp/ differential output.     

Millimeter-wave high-power 0.25-/spl mu/m gate-length AlGaN/GaN HEMTs on SiC substrates

Reports on the CW power performance at 20 and 30 GHz of 0.25 /spl mu/m /spl times/ 100 /spl mu/m AlGaN/GaN high electron mobility transistors (HEMTs) grown by MOCVD on semi-insulating SiC substrates. The devices exhibited current density of 1300 mA/mm, peak dc extrinsic transconductance of 275 mS/mm, unity current gain cutoff (f/sub T/) of 65 GHz, and maximum frequency of oscillation (f/sub max/) of 110 GHz. Saturated output power at 20 GHz was 6.4 W/mm with 16% power added efficiency (PAE), and output power at 1-dB compression at 30 GHz was 4.0 W/mm with 20% PAE. This is the highest power reported for 0.25-/spl mu/m gate-length devices at 20 GHz, and the 30 GHz results represent the highest frequency power data published to date on GaN-based devices.     

Flash ADC architecture

A 4-bit, 2.5 V modified flash analogue-to-digital converter (ADC) has been designed. In this design, the new flash topology only requires 2/sup (N-2)/+2 comparators. For comparison reasons, this new ADC architecture is operated at 400 MHz, consumes a total power of 1.68 mW and generates a total noise power of 4.86/spl times/10/sup -15/. /spl Delta/f(V/sup 2/) at this frequency.     

A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS

A third-order continuous-time multibit (4 bit) /spl Delta//spl Sigma/ ADC for wireless applications is implemented in a 0.13-/spl mu/m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm/sup 2/.     

A 14-bit, 10-Msamples/s D/A converter using multibit /spl Sigma//spl Delta/ modulation

A 14-bit digital-to-analog converter based on a fourth-order multibit sigma-delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5-/spl mu/m CMOS technology and operates from a single 2.5-V supply.     

1.55-/spl mu/m InP-InGaAsP Fabry-Perot lasers with integrated spot size converters using antiresonant reflecting optical waveguides

We demonstrate a new concept for InGaAsP-InP 1.55-/spl mu/m Fabry-Perot lasers integrated with spot size converters using type-A antiresonant reflecting optical waveguides. The fabrication of such devices allows to avoid the growth of thick layers of quaternary material with low Ga and As fraction, which are difficult to achieve and grow. Reduced far-field divergence angles (10/spl deg/ /spl times/ 27/spl deg/) and improved coupling to cleaved standard single-mode fibers (2.6-dB coupling loss) are achieved. The proposed device is compatible with conventional epitaxial techniques and lithographic methods.     

A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications

This paper describes the design and realization of a 15-bit 30-MS/s three-step ADC for imaging applications with a peak-to-peak signal to rms noise ratio (DR/sub pp/) of 85 dB. The offsets of the residue amplifiers are independently background calibrated. The ADC is realized in single-poly, 0.18-/spl mu/m CMOS, measures 1.4 mm/sup 2/, and dissipates 145 mW from 1.8-V and 3.3-V supplies.     

A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s

This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment temperature, and power-supply voltage, as well as the variations in chip fabrication. It utilizes information from the digital calibration process and does not require additional analog circuits. The prototype ADC occupies an area of 0.5/spl times/2.3 mm/sup 2/ in a 0.18-/spl mu/m dual-gate CMOS technology; with a power supply of 2.8 V, it consumes 19.2, 33.7, 50.5, and 72.8 mW when operating at 10, 20, 30, and 40 MS/s, respectively. The peak differential nonlinearity (DNL) is less than 0.5 least significant bit (LSB) for all the sampling speeds with temperature variation up to 80/spl deg/C. When operated at 20 MS/s with 1-MHz input, the ADC achieves 72.1-dB SNR and 71.1-dB SNDR.     

A 17.1-17.3-GHz image-reject downconverter with phase-tunable LO using 3/spl times/ subharmonic injection locking

A 17-GHz RF receiver, consisting of a low-noise amplifier (LNA) and doubly balanced mixers coupled by a monolithic 3.7:1 step-down transformer, realizes over 75 dB of image rejection in a production 100-GHz f/sub T/ SiGe BiCMOS technology. A new coupling transformer winding improves the magnetic coupling coefficient by more than 20% compared to conventional designs, which reduces parasitic effects and increases the overall efficiency of the LNA/mixer combination. Quadrature LO signals with electronically tunable phase are generated by a subharmonically injection-locked oscillator. The measured receiver IIP3 is -5.1 dBm with 17.3-dB conversion gain and 6.5-dB noise figure (SSB 50 /spl Omega/) at 17.2 GHz. The 1.9/spl times/1.0 mm/sup 2/ IC consumes 62.5 mW from a 2.2-V supply.     

Impact of capacitor dielectric relaxation on a 14-bit 70-MS/s pipeline ADC in 3-V BiCMOS

In this paper, phenomena of charge absorption and relaxation in the plasma enhanced chemical vapor deposition (PECVD) silicon nitride dielectric (Si/sub 3/N/sub 4/) used in the capacitors of a 45-GHz f/sub T/, 0.4-/spl mu/m L/sub min/ SiGe BiCMOS are observed and interpreted. When such capacitors are used to design a pipelined 14-bit 70-MS/s switched-capacitor analog-to-digital converter (ADC), dielectric relaxation is identified as the cause of 8-LSB-wide gaps in the integral nonlinearity, which leads to the degradation of the converter performance even at low frequencies. The effect has been analyzed via Matlab behavioral simulations and SPICE circuit simulations. Ad-hoc experimental tests aimed at detecting residual amounts of charge left in the capacitors as a memory of previous states have been also carried out. After low-density low-pressure chemical vapor deposition (LPCVD) oxide capacitors (SiO/sub 2/) are introduced in the process, a new ADC test chip delivers 72.5-dBFS SNR, 82-dBc SFDR, 11.7-bit ENOB at 70 MS/s and 1-MHz input. The circuit features a die size of 5.3 /spl times/ 5.3 mm/sup 2/ and dissipates 1 W from the 3.3-V supply.     

Highly linear 2.5-V CMOS /spl Sigma//spl Delta/ modulator for ADSL+

We present a 90-dB spurious-free dynamic range sigma-delta modulator (/spl Sigma//spl Delta/M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-/spl mu/m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within /spl plusmn/0.85 and /spl plusmn/0.80 LSB/sub 14 b/, respectively. The /spl Sigma//spl Delta/ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the /spl Sigma//spl Delta/ modulator.