p-Channel MOS transistor in indium antimonide

A p-channel MOS transistor in InSb single crystal, operating at 77 K, is described. The source and drain are defined by etching a mesa structure in a cadmium diffused p layer into a tellurium-doped InSb substrate. The gate is formed by evaporation of chromium gold on top of a layer of SiO2, deposited at 215°C. The MOS transistor is characterized by a threshold voltage of -3 V and an effective hole mobility of 330 cm². V^-1.s^-1.     

High-performance EEPROMs using N- and P-channel polysiliconthin-film transistors with electron cyclotron resonanceN2O-plasma oxide

High-performance EEPROMs using n- and p-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) N₂O-plasma oxide have been demonstrated. Both programming and erasing were accomplished by Fowler-Nordheim (F-N) tunneling within 1 ms regardless of programming and erasing voltages. The poly-Si TFT EEPROMs have a threshold voltage shift of 4 V between programmed and erased states; furthermore, they maintain a large threshold voltage shift of 2.5 V after 1×10⁵ program and erase cycles. This is attributed to the excellent charge-to-breakdown (Qbd) up to 10 C/cm² of ECR N₂O-plasma oxide     

High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Electrical properties of tellurium thin films

Semiconducting properties of evaporated tellurium thin films, in the thickness range of 100 to 400 Å, are studied and correlated with observed structural properties. It is found that less-than-monolayer gold films can act as nucleation sites and stimulate the growth of large crystallites in deposited Te films. The Au-nucleated Te films are preferentially oriented with the c axis in the substrate plane and have crystallite diameters ranging from 2 to 5 µm. Hall mobilities as high as 250 cm²/V ċ s are observed in 400-Å Au-nucleated films with 5-µm crystallites. These large-grain films exhibit a temperature dependence for mobility of the form µ ∼ T^3/2between 85°K and 250°K, while the carrier concentrations in the films do not change appreciably with temperature. Transconductances greater than 1000 µmhos are achieved for Au-nucleated Te thin-film transistors with 3-mil channels (operating with a saturated drain current of 1 mA). Several devices exhibit field-effect mobilities greater than 100 cm²/V ċ s, a value consistent with the observed Hall mobilities for similar films. Transconductance measurements indicate that Te thin-film transistor (TFT) instabilities result primarily from hole trapping at the Te-insulator interface. It is possible to alter the threshold voltage of Te TFTs by applying a gate bias at room temperature. Improved stability (changes in V0less than 50 mV in 1 h) is observed at 77°K. From the observed changes in threshold, a lower limit of the trapping-state density at the surface is inferred to be 5×10¹²traps/cm². The surface-state density at the Te-SiO interface is estimated to be less than 6×10¹²surface states/cm²ċ eV as determined from capacitance and conductance measurements.     

Positive flatband voltage shift in MOS capacitors on n-type GaN

GaN MOS capacitors were fabricated using silicon dioxide deposited by low-pressure chemical vapor deposition oxide at 900°C. The MOS capacitor flatband voltage shift versus temperature was used to determine a pyroelectric charge coefficient of 3.7 × 10⁹ q/cm²-K, corresponding to a pyroelectric voltage coefficient of 7.0 × 10⁴ V/m-K     

10 A, 2.4 kV Power DiMOSFETs in 4H-SiC

We report the characteristics of large area (3.3 × 3.3 mm ²) high-voltage 4H-SiC DiMOSFETs. The MOSFETs show a peak MOS channel mobility of 22 cm²/V·s and a threshold voltage of 8.5 V at room temperature. The DiMOSFETs exhibit an on-resistance of 4.2 mΩ·cm² at room temperature and 85 mΩ·cm² at 200°C. Stable avalanche characteristics at approximately 2.4 kV are observed. An on-current of 10 A is measured on a 0.103 cm² device. High switching speed is also demonstrated. This suggests that the devices are capable of high-voltage, high-frequency, low-loss switching applications     

Electron microprobe analysis of impurity heterogeneities in thermally grown silicon oxide

The electron probe X-ray microanalyzer is a powerful tool for studying impurity distribution and motion in thin films. This analytical instrument is capable of detecting metallic impurities present in areas as small as 1 × 10^-6mm²and in concentrations of greater than 1 × 10¹⁹atoms/cm³. The analysis requires no sample preparation and is essentially a nondestructive test. This instrument was used to examine unoxidized and oxidized silicon surfaces and a finished microcircuit. With the electron microprobe, aluminum-bearing regions approximately one microns in diameter were detected on the bare surface of mechanically polished silicon slices. These aluminum-rich regions are believed to be alumina abrasive used in polishing. If these regions are not removed by chemical etching they will generate oxide defects during oxidation. These defects were found to contain Al (1 × 10²¹atoms/cm³and Na (1 × 10²⁰atoms/cm³). Other oxide defects, i.e., pinholes, generated during oxidation varied in size from 0.5 to 5.0 microns and were found to contain Na (1×10²¹atoms/cm³) and K (5×10²¹atoms/cm³). Mg and Ca (1 × 10²⁰atoms/cm³) were occasionally observed in these defects. After oxidation, all these impurities could be removed with a hot hydrochloric acid and deionized water rinse; surprisingly, this treatment reduced the silicon surface charge in the MOS structure (X_{0} cong 1500Å) by approximately 1.4 × 10¹¹charges/cm². The surface charge could be further reduced by heating the oxidized wafer at 900°C in a silicon nitride tube.     

Threshold voltage shift of n-channel Si-gate MOSFET's

The relationship between the threshold voltage shift of the n-channel Si-gate MOSFET and the implant dose of boron ions has been examined theoretically and experimentally when these ions are implanted with an energy of 60 keV through a gate oxide of 1200 Å into a p-type silicon substrate of the acceptor concentration of 7 × 10¹⁴/cm³. The effect of high-temperature treatment after ion implantation on the threshold voltage shift has been considered. The good agreement between the theory and the experiment verifies that the model used is reasonable. The threshold voltage shift with the dose is expressed by about 5 × 10^-12V.cm²below a dose of 5 × 10¹¹ions/cm². Above this value, the increase of the threshold voltage shift becomes slow and the slope takes the value of about 2 × 10^-12V.cm²due to the maximum surface depletion layer.     

Anomalous radiation effect in p-channel MOSFET's under electron irradiation

An anomalous shift in the gate threshold voltage of high-transconductance p-channel MOSFET's has been observed during exposure to space-like radiation of 2 × 10¹²electrons/cm²that is two and one half to three times its saturation value at 2 × 10¹⁴electrons/cm²and is five to seven times its pre-irradiation value.     

Stabilization of MOS structures by Boron ion implantation

Bias and temperature stress measurements have been used to study the effect of¹¹B ion implantation into MOS structures. The boron energies were selected so that the projected range of the implanted distribution was approximately equal to the device oxide thickness. Boron ion doses ranged from 10¹¹to 2 × 10¹²/cm². The bias temperature stress consisted of 10⁶V/cm applied at 300°C for 5 min. In all cases, the stability of the implanted capacitors was found to be significantly improved over the unimplanted.     

Quadruple-well CMOS for VLSI technology

A novel process has been developed to fabricate high-density CMOS with four wells. These wells are self aligned to increase packing density. Two of them are relatively deep wells used to optimize both n- and p-channel active devices. The other two are shallow wells under field oxide to form channel stops for both device types. The channel stops provide rigorous isolation among similar devices and between the devices of the opposite polarity. Subthreshold leakage currents in isolation regions are <0.05 pA/µm when devices are biased at <16.5 V. The channel stops also suppress lateral parasitic bipolar action. To reduce the vertical bipolar gain, a new process technique employing a double-retrograde well and transient annealing has been established. For the CMOS structure with 2-µm p⁺-to-p-well spacing, we have eliminated latchup by suppressing the beta product to below unity. Moreover, the quadruple-well approach has produced active n- and p-channel FET's with excellent characteristics such as low threshold voltage (∼±0.5 V), low subthreshold slope (≲95 mV/dec), low contact resistivity (∼10^-7Ω-cm²), and high channel mobility (620 and 210 cm²/V . s).     

High performance poly-crystalline silicon thin film transistorsfabricated using remote plasma chemical vapor deposition of SiO2

A remote plasma chemical vapor deposition (RPCVD) of SiO₂ was investigated for forming an interface of SiO₂/Si at a low temperature below 300°C. A good SiO₂/Si interface was formed on Si substrates through decomposition and reaction of SiH₄ gas with oxygen radical by confining plasma using mesh plates. The density of interface traps (D_it) was as low as 3.4×10¹⁰ cm^-2eV^-1. N- and p-channel Al-gate poly-Si TFTs were fabricated at 270°C with SiO₂ films as a gate oxide formed by RPCVD and laser crystallized poly-crystalline films formed by a pulsed XeCl excimer laser. They showed good characteristics of a low threshold voltage of 1.5 V (n-channel) and -1.5 V (p-channel), and a high carrier mobility of 400 cm²/Vs     

Effect of zinc impurity on silicon solar-cell efficiency

Zinc is a major residue impurity in the preparation of solar-grade silicon material by the zinc vapor reduction of silicon tetrachloride. This paper projects that in order to get a 17-percent AM1 cell efficiency for the Block IV module of the Low-Cost Solar Array Project,¹the concentration of the zinc recombination centers in the base region of silicon solar cells must be less than 4 × 10¹¹Zn/cm³in the p-base n+/p/p+ cell and 7 × 10¹¹Zn/cm³in the n-Base p+/n/n+ cell for a base dopant impurity concentration of 5 × 10¹⁴atoms/cm³. If the base dopant impurity concentration is increased by a factor of 10 to 5 × 10¹⁵atoms/cm³, then the maximum allowable zinc concentration is increased by a factor of about two for a 17-percent AM1 efficiency. The thermal equilibrium electron and hole recombination and generation rates at the double-acceptor zinc centers are obtained from previous high-field measurements as well as new measurements at zero field described in this paper. These rates are used in the exact dc-circuit model to compute the projections.     

In-situ low energy BF2+ion doping for silicon molecular beam epitaxy

An experimental study of the p-type ion dopant BF2+ in silicon molecular beam epitaxy (MBE) is described. BF2+ was used to dope MBE layers during growth to levels ranging from 1 × 10¹⁶/cm³to 4 × 10¹⁸/cm³over a growth temperature range of 650°C to 1000°C. The layers were evaluated using spreading resistance, chemical etching, and secondary ion mass spectroscopy. Complete dopant activation was observed for all growth temperatures. Remnant fluorine in the epitaxial layer was less than 2 × 10¹⁶/cm³in all cases. Diffused p-n junction diodes fabricated in BF2+-doped epitaxial material showed hard reverse breakdown characteristics.     

Reduction in minority carrier storage effect by fluorine ion implantation damage

Damage is produced in p-n diodes by fluorine ion implantation to reduce minority carrier storage effect. The switching time, reverse leakage current, andI-Vcharacteristics were investigated for annealing temperature between 450°C and 650°C. The accelation energy is 130 keV and doses are 10¹³-10¹⁵/cm². Annealing causes restoration in switching time, but leakage current increases with annealing temperature rise for doses more than 1 × 10¹⁴/cm². The best diodes indicate 1.5-order reduction in switching time and 10 nA in reverse leakage current. These properties, caused by implantation damage, are retained after long-cycle annealing at 450°C and are expected to be stable under practical use. These diodes can be obtained by annealing at 450°C and they furnish satisfactory diode performance.     

A method of determining impurity diffusion coefficients and surface concentrations of drift transistors

In order to control the electrical parameters of drift transistors, it was found necessary to control the impurity concentration gradient in the base. An extension of the space charge widening theory provides a method of calculating this gradient, the surface concentration, and the diffusion coefficient. By this method, the diffusion coefficient of arsenic into germanium at 725°C was found to be 3.1 × 10^-12cm²/second and the initial surface concentration was of the order of 10²⁰atoms/cm³. Universal graphs for design calculations and rapid reference are presented.     

Anodic oxidation of Si in oxygen/chlorine plasma

By adding a few percent of chlorine to oxygen plasma, the anodization rate of Si was enhanced; for example, the rate was doubled for oxygen containing 3-percent chlorine. With a chlorine concentration of 1.5 percent, the density of trap states at the Si-SiO2interface was reduced from 7×10¹¹/cm².eV to 5×10¹¹/cm².eV at the midgap of Si; after annealing at 800°C in argon for 60 min, it was reduced to 8 × 10¹⁰/cm².eV, and did not return to the original value after heating the specimen to 800°C. The density and capture cross section of traps in plasma-anodic oxide were also measured using the constant-current avalanche-injection method. The number of electron traps with small cross sections in plasmaanodic SiO2films was reduced by annealing them at 800°C in argon, but SiO2films which were anodized in oxygen/chlorine plasma showed an increase of trap density under the same annealing condition.     

Low-cost process for fabricating polysilicon transistors

A process for the fabrication of p-channel polysilicon MOS transistors is described. The process is compatible with the use of low-temperature glass substrates and replaces the use of ion implantation for the source/drain doping with in situ doped polysilicon. MOS transistors made with this process exhibit an on/off current ratio of 2.5×10⁵, a mobility of 16 cm²/V-s, and a subthreshold slope of 1.3 V/decade     

MOSFET's on Au-diffused high-resistivity Si substrates

Si MOSFET's on Au-diffused high-resistivity substrates were fabricated and their electrical properties were investigated. At 80 K, the current leakage between the source and drain of both n- and p-channel devices decreased below 10^-10A, and the devices exhibited normally-off behaviors. Au concentrations (N) in Si substrates as a function of diffusion temperature Tdiffwas determined from the change in the threshold voltage.Nversus Tdiffthus obtained is in fairly good agreement with that obtained by other methods. Dependence of effective mobility on Tdiffwas investigated in the form of a MOS device. The effective mobility decreased with increasing Tdiff, and it became clear that the diffusion temperature must be lower than about 700°C to obtain semi-insulating substrates with reasonably high carrier mobility. A C-MOS inverter was fabricated using an Au-diffused Si substrate, where no isolation wells were needed, in operation at low temperatures.