Low power noise immune node voltage comparison keeper design for high speed architectures

The demand for high speed and area minimization has directed the designers towards dynamic CMOS logic design. The domino logic is one of the famous logic in dynamic CMOS logic. The designer needs to compromise the circuit speed and power consumption to reduce the impact of noise in domino logic circuit design. In this work, low power domino logic circuit is proposed to decrease power consumption with improvement in noise immunity. The low power consumption is achieved at the cost small sacrifice in delay. However, the proposed logic circuit has attained better Power Delay Product (PDP) as compared to existing noise tolerant circuits. The experimental simulation results shows the proposed logic exhibit 3.4% power reduction when compared with the low power domino logic circuit [10] for two input OR gates. The proposed logic had a little compromise with delay in the existing logics. However, the Power Delay Product (PDP) of proposed logic circuit has reduced as compared to existing techniques. The proposed logic also provides the better improvement in noise immunity parameters such as UNG and ANTE as compared to the existing logics. The proposed logic circuit based application circuit such as 4:1 multiplexer also provides better improvement in case of power consumption and noise immunity.     

一种低功耗CMOS分频电路设计技术

本文首先介绍了为降低ＶＬＳＩ系统功耗在产品定义、结构设计、逻辑设计和电路设计各个级别上所采取的技术，然后具体讨论了一咱低功耗ＣＭＯＳ电路的设计特点，包括采用参考电压、动态电路和电平转换电路等。     

Low power adiabatic logic based on FinFETs

With the aggressive scaling of device technology,the leakage power has become the main part of power consumption,which seriously reduces the energy recovery efciency of adiabatic logic.In this paper,a novel low-power adiabatic logic based on FinFET devices has been proposed.Due to the lower leakage current,higher on-state current and design flexibility of FinFETs,the proposed adiabatic logic shows considerable power reduction,performance improvement and area saving compared with CMOS adiabatic logic.An 8-state clock chain as the test circuit has been demonstrated based on the 32-nm FinFET Predictive Technology Model.The simulation results show that adiabatic circuit based on FinFET devices achieves a power reduction of up to84.8%and a limiting frequency of up to 55 GHz.     

Design of reversible logic based full adder in current-mode logic circuits

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.     

Design and analysis of area efficient QCA based reversible logic gates

The CMOS technology has been plagued by several problems in past one decade. The ever increasing power dissipation is the major problem in CMOS circuits and systems. The reversible computing has potential to overcome this problem and reversible logic circuits serve as the backbone in quantum computing. The reversible computing also offers fault diagnostic features. Quantum-dot cellular automata (QCA) nanotechnology owing to its unique features like very high operating frequency, extremely low power dissipation, and nanoscale feature size is emerging as a promising candidate to replace CMOS technology. This paper presents design and performance analysis of area efficient QCA based Feynman, Toffoli, and Fredkin universal reversible logic gates. The proposed designs of QCA reversible Feynman, Toffoli, and Fredkin reversible gates utilize 39.62, 21.05, and 24.74% less number of QCA cells as compared to previous best designs. The rectangular layout area of proposed QCA based Feynman, Toffoli, and Fredkin gates are 52, 28.10, and 40.23%, respectively less than previous best designs. The optimized designs are realized employing 5-input majority gates to make proposed designs more compact and area efficient. The major advantage is that the optimized layouts of reversible gates did not utilize any rotated, translated QCA cells, and offer single layer accessibility to their inputs and outputs. The proposed efficient layouts did not employ any coplanar or multi-layer wire crossovers. The energy dissipation results have been computed for proposed area efficient reversible gates and thermal layouts are generated using accurate QCAPro power estimator tool. The functionality of presented designs has been performed in QCADesigner version 2.0.3 tool.     

针对IDEA加密算法的差分功耗攻击

研究分析国际数据加密算法IDEA的特点,采用差分功耗分析攻击方式进行密钥破解,针对IDEA算法提出一种基于汉明距离的差分功耗攻击方法.该攻击方法是一种典型的加密芯片旁路攻击方式,其理论基础为集成电路中门电路在实现加密算法时的物理特性、功耗模型及数据功耗相关性.详细介绍了针对IDEA加密系统进行差分功耗攻击的设计与实现,开发了相应的仿真实验平台,实验成功破解了IDEA加密算法的密钥,从而给IDEA加密算法研究者提供了有益的安全设计参考.实验表明,未加防护措施的IDEA加密系统难以抵御差分功耗的攻击.     

Reversible binary subtractor design using quantum dot-cellular automata

In the field of nanotechnology, quantum dot-cellular automata (QCA) is the promising archetype that can provide an alternative solution to conventional complementary metal oxide semiconductor (CMOS) circuit. QCA has high device density, high operating speed, and extremely low power consumption. Reversible logic has widespread applications in QCA. Researchers have explored several designs of QCA-based reversible logic circuits, but still not much work has been reported on QCA-based reversible binary subtractors. The low power dissipation and high circuit density of QCA pledge the energy-efficient design of logic circuit at a nano-scale level. However, the necessity of too many logic gates and detrimental garbage outputs may limit the functionality of a QCA-based logic circuit. In this paper we describe the design and implementation of a DG gate in QCA. The universal nature of the DG gate has been established. The QCA building block of the DG gate is used to achieve new reversible binary subtractors. The proposed reversible subtractors have low quantum cost and garbage outputs compared to the existing reversible subtractors. The proposed circuits are designed and simulated using QCA Designer-2.0.3.     

Implementing a one-bit reversible full adder using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technique is one of the emerging and promising nanotechnologies. It has considerable advantages versus CMOS technology in various aspects such as extremely low power dissipation, high operating frequency and small size. In this paper, designing of a one-bit full adder is investigated using a QCA implementation of Toffoli and Fredkin gates. Then, a full adder design with reversible QCA1 gates is proposed regarding to overhead and power savings. Our proposed full adder design is more preferable when considering both circuit area and speed. The proposed design uses only two QCA1 gates and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells.     

深亚微米CMOS电路漏电流快速模拟器

随着工艺的发展 ,功耗成为大规模集成电路设计领域中一个关键性问题 降低电源电压是减少电路动态功耗的一种十分有效的方法 ,但为了保证系统性能 ,必须相应地降低电路器件的阈值电压 ,而这样又将导致静态功耗呈指数形式增长 ,进入深亚微米工艺后 ,漏电功耗已经能和动态功耗相抗衡 ,因此 ,漏电功耗快速模拟器和低功耗低漏电技术一样变得十分紧迫 诸如HSPICE的精确模拟器可以准确估计漏电功耗 ,但仅仅适合于小规模电路 首先证实了CMOS晶体管和基本逻辑门都存在堆栈效应 ,然后提出了快速模拟器的漏电模型 ,最后通过对ISCAS85& 89基准电路的实验 ,说明了在精度许可 (误差不超过 3% )的前提下 ,模拟器获得了成百倍的加速 ,同时也解决了精确模拟器的内存爆炸问题     

Novel low power reversible binary incrementer design using quantum-dot cellular automata

This paper demonstrates the design of n-bit novel low power reversible binary incrementer in Quantum-Dot Cellular Automata (QCA). The comparison of quantum cost in quantum gate based approach and in QCA based design agreed the cost efficient implementation in QCA. The power dissipation by proposed circuit is estimated, which shows that the circuit dissipates very low heat energy suitable for reversible computing. All the circuits are evaluated in terms of logic gates, circuit density and latency that confirm the faster operating speed at nano scale. The reliability of the circuit under thermal randomness is explored which describes the efficiency of the circuit.     

交流接触器节能专用芯片的设计与实现

在对交流接触器能耗进行分析的基础上,根据交流接触器可用强激磁吸动和弱激磁吸持的特点,将其电磁系统的交流运行方式改为直流运行方式,采用自转换式改变占空比的节能方案,设计开发了一款智能型交流接触器节能专用集成电路芯片ZDLX。此芯片采用0.5μm混合信号CMOS工艺。实测结果表明,此芯片配合交流接触器使用后可将后者功耗降低90%(仅为原功耗的10%)。因此该节能专用芯片ZDLX具有重要的社会和经济价值。     

家用小功率光伏发电系统的设计

文中首先介绍了光伏发电系统的国内外研究现状,并得出了理论研究较多,涉及到实际产品研发较少的结论。在此背景下分析了光伏发电系统基本架构和逆变器拓扑结构,重点对比研究了工频变压器隔离并网型（DC/AC+AC/AC）、非隔离式并网型（DC/DC+DC/AC）、高频变压器隔离并网型（DC/AC/DC+DC/AC）等3种常见逆变器结构;然后结合家用这一实际情况对这3种结构进行了一一剖析,在此基础上提出了DC/DC+DC/AC/DC+DC/AC的3级架构设计方案,其中包括斩波电路、推挽升压电路、逆变电路三部分;最后以STM32ZET6单片机为系统核心控制器件,设计并完成光伏发电系统中各个硬件板卡的焊接和调试功能,通过测试样机得到实验数据。实验结果表明文中提出的DC/DC+DC/AC/DC+DC/AC架构设计方案易实现,实验样机能源利用效率和稳定性较高,体积小,能够满足家用要求。     

无线传感器网络低功耗真随机源设计

针对无线传感器网络(WSNs)密码安全应用过程中的低功耗需求和无线传感器网络节点集成微型化的趋势,提出一种新的真随机源设计方法用于生成高质量密钥来保证密码算法安全性。该方法基于概率计算单元构建斐波那契振荡随机源。由于概率计算单元工作状态在MOS管的亚阈值电流区,工作电流小使得设计功耗极低。同时,防止电路停振,设计概率信号放大单元保证随机振荡正确性。本设计在中芯国际SMIC 0.13μm工艺下进行仿真验证,所产生的真随机序列性能良好。与基于数字逻辑门的振荡真随机源相比,功耗减小1000倍,面积也有明显减小,适合应用于无线传感器网络之中。     

An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits

In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal p     

Designing CMOS Circuits for Switch-Level Testability

Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.     

Function synthesis algorithm based on RTD-based three-variable universal logic gates

Compared with complementary metal–oxide semiconductor (CMOS), the resonant tunneling device (RTD) has better performances; it is the most promising candidate for next-generation integrated circuit devices. The universal logic gate is an important unit circuit because of its powerful logic function, but there are few function synthesis algorithms that can implement an n-variable logical function by RTD-based universal logic gates. In this paper, we propose a new concept, i.e., the truth value matrix. With it a novel disjunctive decomposition algorithm can be used to decompose an arbitrary n-variable logical function into three-variable subset functions. On this basis, a novel function synthesis algorithm is proposed, which can implement arbitrary n-variable logical functions by RTD-based universal threshold logic gates (UTLGs), RTD-based three-variable XOR gates (XOR3s), and RTD-based three-variable universal logic gate (ULG3s). When this proposed function synthesis algorithm is used to implement an n-variable logical function, if the function is a directly disjunctive decomposition one, the circuit structure will be very simple, and if the function is a non-directly disjunctive decomposition one, the circuit structure will be simpler than when using only UTLGs or ULG3s. The proposed function synthesis algorithm is straightforward to program, and with this algorithm it is convenient to implement an arbitrary n-variable logical function by RTD-based universal logic gates.     

单片机系统设计中低功耗的探讨

通过CMOS电路的功耗分析及MCU待机功能的简单介绍,提出了单片机系统低功耗设计的总体原则,并从硬件和软件方面介绍了具体的实现低功耗方法。     

基于逻辑门类型的老化路径约减算法

随着CMOS集成电路工艺尺寸的不断缩小,电路可靠性问题日益严重,而由NBTI效应引起的电路老化问题尤其突出。由于实际电路大多比较复杂,路径较多,如果对所有路径进行老化预测,工作量会非常大。针对这一实际难题提出了一种基于电路路径中门种类和数目的迭代算法,用来划分和约减电路中不受老化影响电路功能的电路路径。该方法根据路径中每类门的数目和门种类对电路老化的不同影响程度将电路路径进行分类,约减掉不需要预测老化的路径,减少了老化预测的工作量,提高了电路老化预测的效率。     

Novel designs of nanometric parity preserving reversible compressor

Reversible logic is a new field of study that has applications in optical information processing, low power CMOS design, DNA computing, bioinformatics, and nanotechnology. Low power consumption is a basic issue in VLSI circuits today. To prevent the distribution of errors in the quantum circuit, the reversible logic gates must be converted into fault-tolerant quantum operations. Parity preserving is used to realize fault tolerant in this circuits. This paper proposes a new parity preserving reversible gate. We named it NPPG gate. The most significant aspect of the NPPG gate is that it can be used to produce parity preserving reversible full adder circuit. The proposed parity preserving reversible full adder using NPPG gate is more efficient than the existing designs in term of quantum cost and it is optimized in terms of number of constant inputs and garbage outputs. Compressors are of importance in VLSI and digital signal processing applications. Effective VLSI compressors reduce the impact of carry propagation of arithmetic operations. They are built from the full adder blocks. We also proposed three new approaches of parity preservation reversible 4:2 compressor circuits. The third design is better than the previous two in terms of evaluation parameters. The important contributions have been made in the literature toward the design of reversible 4:2 compressor circuits; however, there are not efforts toward the design of parity preservation reversible 4:2 compressor circuits. All the scales are in the nanometric criteria.     

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

Floating point digital signal processing technology has become the primary method for real time signal processing in most digital systems presently. However, the challenges in the implementation of floating point arithmetic on FPGA are that, the hardware modules are larger, have longer latency and high power consumption. In this work, a novel efficient reversible floating point fused arithmetic unit architecture is proposed confirming to IEEE 754 standard. By utilizing reversible logic circuits and implementation with adiabatic logic, power efficiency is achieved. The hardware complexity is reduced by employing fused elements and latency is improved by decomposing the operands in the realization of floating point multiplier and square root. To validate the design, the proposed unit was used for realization of FFT and FIR filter which are important applications of a DSP processor. As detection is one of the core baseband processing operations in digital communication receivers and the detection speed determines the data rates that can be achieved, the proposed unit has been used to implement the detection function. Simulation results and comparative studies with existing works demonstrate that the proposed unit efficiently utilizes the number of gates, has reduced quantum cost and produced less garbage outputs with low latency, thereby making the design a computational and power efficient one.