Jitter and phase noise in ring oscillators

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed     

Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and$1/f$Noise

Phase noise and timing jitter in oscillators and phase-locked loops (PLLs) are of major concern in wireless and optical communications. In this paper, a unified analysis of the relationships between time-domain jitter and various spectral characterizations of phase noise is first presented. Several notions of phase noise spectra are considered, in particular, the power-spectral density (PSD) of the excess phase noise, the PSD of the signal generated by a noisy oscillator/PLL, and the so-called single-sideband (SSB) phase noise spectrum. We investigate the origins of these phase noise spectra and discuss their mathematical soundness. A simple equation relating the variance of timing jitter to the phase noise spectrum is derived and its mathematical validity is analyzed. Then, practical results on computing jitter from spectral phase noise characteristics for oscillators and PLLs with both white (thermal, shot) and$bf 1/f$noise are presented. We are able to obtain analytical timing jitter results for free-running oscillators and first-order PLLs. A numerical procedure is used for higher order PLLs. The phase noise spectrum needed for computing jitter may be obtained from analytical phase noise models, oscillator or PLL noise analysis in a circuit simulator, or from actual measurements.     

Jitter in ring oscillators

Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit κ, which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction     

差分环形振动器的相位噪声与时间抖动研究

基于差分环形振荡器的相位噪声理论,详细介绍了相位噪声、时间抖动的定义,提出了相位噪声的计算公式,并推导了由相位噪声到时间抖动的换算公式。实施了Matlab和Spectre联合仿真,结果验证了计算公式的准确性。相位噪声在环路带宽外的计算值与Spectre仿真值的绝对误差不超过2.35 dB;时间周期抖动计算值与Spectre仿真值的绝对误差为1.847 ps,可对低相位噪声的差分环形振荡器设计提供参考和指导。     

CMOS Oscillators for Clock Distribution and Injection-Locked Deskew

The distribution and alignment of high-frequency clocks across a wide bus of links is a significant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a buffer into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional buffering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 $mu hbox{m}$ digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. The measured phase noise is $-101~hbox{dBc}/hbox{Hz}$ @ 1 MHz frequency offset. A clock alignment technique based upon injection-locked quadrature-LC or ring oscillators is then proposed. Although injection-locked oscillators (ILOs) are known to be capable of deskewing and jitter filtering clocks, a study of both LC and ring ILOs indicates significant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting different phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. The technique is demonstrated using a LC QVCO at 20 GHz while burning only 20 mW of power and providing an 8 dB improvement in phase noise. A ring oscillator deskews a 2 to 7 $~$GHz clock while consuming 14 mW in 90 nm CMOS.      

5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS

Voltage supply scaling in CMOS processes requires lower inductance and higher capacitance in conventional LC oscillators. Forcing several LC oscillators to run in phase is a valuable means of achieving the wanted phase noise with practical values of inductances and capacitances. However, in-phase oscillator arrays suffer from the up-conversion of transistors' flicker noise, in the presence of oscillator mismatches. A multitank oscillator topology is proposed, which has superior tolerance to mismatches and removes this mechanism of noise degradation. In order to assess such topology, an 802.11 a-compliant VCO with four coupled oscillators has been designed in a 0.13-mum CMOS technology. A phase noise better than -120 dBc/Hz at 1-MHz offset has been achieved along the 4.7-5.9-GHz tuning range     

Analytical Equations for Nonlinear Phase Errors and Jitter in Ring Oscillators

In this paper, we present a simple analytical equation for capturing phase errors in 3-stage ring oscillators. The model, based on a simple but useful idealization of the ring oscillator, is provably exact for small noise perturbations. Despite its simplicity and purely analytical form, our model correctly captures the time- dependent sensitivity of oscillator phase to external perturbations. It is thus well suited for estimating both qualitative and quantitative features of ring oscillator phase response to internal noises, as well as to power, ground and substrate interference. The nonlinear nature of the model makes it suitable for predicting injection locking as well. Comparisons of the new model with existing phase models are provided, and its application for correct prediction of thermal jitter demonstrated. Requiring knowledge only of the amplitude and frequency of the oscillator, the model is ideally suited for early design exploration at the system and circuit levels.     

一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环

用简单的鉴频鉴相器结构实现了一个快锁定低抖动的锁相环.鉴频鉴相器仅仅由两个异或门组成,它可以同时获得低抖动和快锁定的性能.锁相环中的电压控制振荡器由四级环形振荡器来实现,每级单元电路工作在相同的频率,并提供45°的相移.芯片用0.18μm CMOS工艺来实现.PLL输出的中心频率为5GHz,在偏离中心频率500kHz处,测量的相位噪声为-102.6dBc/Hz.锁相环的捕获范围为280MHz,RMS抖动为2.06ps.电源电压为1.8V时,功耗仅为21.6mW(不包括输出缓冲).     

Technique for Flicker Noise Up-Conversion Suppression in Differential LC Oscillators

A novel technique for the suppression of the flicker noise up-conversion in a differential LC oscillator topology is proposed. Relaxation mechanism and tunable noise filtering of the relaxation thresholds provide simultaneous suppression of differential pair and bias transistor flicker noise contributions. The proposed technique is validated on a fully monolithic oscillator architecture and 0.35-mum standard CMOS process by Cadence SpectreRF for the frequency range of 2.9-5.9 GHz. The phase noise improvement at 10 kHz offset versus a single-differential-pair LC oscillator is 6-15 dB across the tuning range.     

A study of phase noise in colpitts and LC-tank CMOS oscillators

This paper presents a study of phase noise in CMOS Colpitts and LC-tank oscillators. Closed-form symbolic formulas for the 1/f/sup 2/ phase-noise region are derived for both the Colpitts oscillator (either single-ended or differential) and the LC-tank oscillator, yielding highly accurate results under very general assumptions. A comparison between the differential Colpitts and the LC-tank oscillator is also carried out, which shows that the latter is capable of a 2-dB lower phase-noise figure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted. Several prototypes of both Colpitts and LC-tank oscillators have been implemented in a 0.35-/spl mu/m CMOS process. The best performance of the LC-tank oscillators shows a phase noise of -142dBc/Hz at 3-MHz offset frequency from a 2.9-GHz carrier with a 16-mW power consumption, resulting in an excellent FoM of /spl sim/189 dBc/Hz. For the same oscillation frequency, the FoM displayed by the differential Colpitts oscillators is /spl sim/5 dB lower.     

推–推振荡器共用谐振器分析与低相位噪声设计

为实现低相位噪声平面振荡器,对推-推振荡器的共用谐振器与相位噪声优化方法进行了研究。提出一种基于多环式开口谐振环的差分传输线,通过加载一对耦合谐振环的方式实现2个单元振荡器之间的弱耦合,提高了共用谐振器的频率选择特性。基于该结构设计并实现了一种X波段推-推振荡器,在设计中采用一种基于振荡器有源品质因子的相位噪声优化方法。测试结果表明：该振荡器在输出二次谐波9.52 GHz处的相位噪声为-115.48 dBc/Hz@100 kHz,基波抑制度达到-54.55 dBc。     

Simulation of phase noise generated by white noise in 1.7 GHz CMOSLC oscillator

The phase noise resulting from upconversion of white noise in a CMOS LC oscillator is investigated. HSPICE simulations of phase noise resulting from the random-phase white noise in a 1.7 GHz CMOS LC oscillator have been performed and demonstrate that the phase noise resulting from the upconversion of white noise has a 1/f-dependence on the offset frequency and becomes larger as the white noise increases. The results provide a confirmation by circuit simulations of Leeson's empirical formula, and provide a technique for the design of low noise oscillators     

Predicting random jitter - Exploring the current simulation techniques for predicting the noise in oscillator, clock, and timing circuits

The random jitter performance of clock, oscillator, and timing circuits can be predicted by using steady-state circuit simulation techniques that determine phase noise by analyzing the impact on phase due to thermal, flicker, channel, and shot noise present in the electronic devices. Given the phase noise response, and the steady-state operating conditions of the circuit, a wide variety of jitter measurements can be computed. Each involves a transformation of the phase noise results, with accuracy hinging on the quality of the phase noise response over a suitable range of offset frequencies     

Jitter characteristics of an on-chip voltage reference-locked time-to-digital converter

The noise and jitter characteristics of an on-chip voltage reference-locked ring oscillator used in the time-to-digital converter (TDC) of the integrated receiver of a pulsed time-of-flight laser rangefinder are presented. The frequency of the ring oscillator, 683 MHz, was locked to the on-chip voltage reference by means of a frequency-to-voltage converter, resulting in better than 90 ppm/°C stability. The noise and jitter transfer characteristics of the loop were derived, and simulations were performed to see the effects of different noise types (white and 1/f noise) on the cumulative jitter of the locked ring oscillator. Finally, these results were verified by jitter measurements performed using an integrated time-to-digital converter (TDC) fabricated on the same die (0.18 μm CMOS process). The cumulative jitter of the on-chip reference-locked ring oscillator was less than 30 ps (sigma value) over a time range of 70 ns, which made it possible to use this oscillator as the heart of a TDC when aiming at centimetre-level precision (1 cm = 67 ps) in laser ranging.     

A study of phase noise in CMOS oscillators

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise, are identified and formulated. Based on the same concepts, a CMOS relaxation oscillator is also analyzed. Issues and techniques related to simulation of noise in the time domain are described, and two prototypes fabricated in a 0.5-μm CMOS technology are used to investigate the accuracy of the theoretical predictions. Compared with the measured results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at 5 MHz offset have an error of approximately 4 dB     

RF Oscillator Based on a Passive RC Bandpass Filter

A passive RC bandpass filter (BPF) based voltage-controlled-oscillator (VCO) operating at 2.5 GHz is presented. In GHz frequency range, a preferred type of an oscillator is either an LC oscillator or a ring oscillator. An LC oscillator exhibits an excellent phase noise performance while its fabrication cost is expensive due to the inductors. On the other hand, a ring oscillator can be built with standard CMOS devices resulting in a cheap fabrication cost. However, it has a poor phase noise and jitter performance and is sensitive to power supply noise. This paper proposes a RC BPF-based oscillator. Its property is closer to a LC oscillator rather than a ring oscillator and, as a result, improves the jitter performance due to power supply noise. Also, it can be fabricated in a standard CMOS process since there is no inductor. To prove the proposed concept, a RC BPF-based oscillator was designed and fabricated in a standard 0.13-$mu{hbox {m}}$ CMOS technology. An operating frequency of 2.5 GHz and phase noise of $-$ 95.4 dBc/Hz at 1$~$MHz offset was measured. Power consumption was 2.86 mW from a 1.3$~$ V supply voltage.      

Design of a Tunable Differential Ring Oscillator With Short Start-Up and Switching Transients

Timing measurements such as jitter and skew in the range of picoseconds, for circuits with multigigahertz clocks or multigigabit-per-second serial communication interfaces are common. A Vernier-oscillator-based time-to-digital converter (TDC) is a circuit that allows picosecond-timing measurements by means of two tunable oscillators. In such a circuit, the oscillator jitter, tuning response, start-up transient, and frequency switching transient play an important role in the TDCs measurement time and accuracy. In this work, we discuss the design of an optimized, differential CML-based ring oscillator and its impact on a TDC design. Simulation results from the new oscillator show that the oscillator's short start-up and frequency switching transients have negligible effects on the accuracy of the TDC measurements. TDC simulation results show that, using two of these oscillators, accurate timing measurements in the range of 10 to 900 ps can be achieved with best-case accuracy of ~2 ps.     

Full Time-Varying Phase Noise Analysis for MOS Oscillators Based on Floquet and Sylvester Theorems

In this paper a set of full time-varying analyzing methods of phase noise for oscillators based on Floquet and Sylvester theorems are established, it provides a good idea for designing oscillators with perfect phase noise performance. The periodic state solution space of a linear periodic time-varying system is constructed with Floquet and Sylvester theorems, and the phase noise perturbation vectors of an oscillator autonomous system are characterized on this space. The analytical expressions of the phase noise spectrums, both 1/(Δ f)² and Lorentzian forms, are obtained, and the contributions to the phase noise of each noise sources are determined. With a generator approach and some modification, the method could be extended to the flicker noise. For RF front-end oscillators composed of MOS active devices, planar inductors and MOS varactors, the time-varying model parameters of the small signal equivalent circuits are constructed according to the periodic varying working-points. By the means of automatic small-signal equivalent-circuit construction, state-variable selection and periodic time-varying state-matrix generation, the system perturbation vectors and phase noise power spectrums are efficiently calculated. For a 10 GHz MOS oscillator, the 1/(Δ f)² and Lorentzian spectrums are calculated. Comparing with the results of SpectreRF, it indicates the proposed methods are accurate and reliable, especially the Lorentzian spectrum close to the carrier is more reasonable than previous methods. Every noise source contributions to the phase noise are listed and the results are analyzed. At last the applications of the methods to designing low phase noise oscillators and to analyzing the phase noise of composite systems, as well as the difficulty of flicker noise analysis, are addressed.     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

Influence of noise intensity on the spectrum of an oscillator

This paper investigates the influence of high-intensity noise on the correlation spectrum of a two-dimensional (2-D) nonlinear oscillator. An exact analytical solution for the correlation spectrum of this 2-D oscillator is provided. The analytical derivations are well suited for oscillators with white noise of any intensity, but computational constraints on the solution of the partial differential equation may make it impractical for cases where the number of state variables exceeds three. The spectral results predicted by our analytical method are verified by numerical simulations of the noisy oscillator in the time domain. We find that the peak of the oscillator spectrum shifts toward higher frequencies as the noise intensity is increased, as opposed to the fixed oscillation frequency predicted in the existing literature. This phenomenon does not appear to have been reported previously in the context of phase noise in oscillators.