A new low-noise FET structure

A novel monolithic FET topology has demonstrated improved minimum noise figure when compared with a conventional pi-gate FET. The structure, referred to as the spider FET, has allowed noise figures to be achieved in monolithic LNA applications that are 0.3 dB lower than in the standard 0.5-μm GaAs MESFET ion-implantation process. The improved spider FET performance is achieved by reducing the gate feed resistance and minimizing the parasitic gate-to-source capacitance in the region of the gate feed. The spider FET shows promise in 0.25-μm MESFET and HEMT (high electron mobility transistor) applications, as well as in power FET applications     

Noise performance of gallium arsenide field-effect transistors

After a brief review of the noise-generating mechanisms intrinsic to the GaAs FET, an enumeration is given of the various parasitic elements associated with the FET which affect the noise performance. These elements include, among others, the gate metallisation and source contact resistances, drain-gate feedback capacitance, and source lead inductance. Numerous graphs are presented to illustrate the effects of these elements and the various design parameters on the noise performance. A comparison is made between the theoretically predicted and the measured noise performance of microwave GaAs FET's. The best state-of-the-art noise performance as reported by various laboratories is illustrated graphically for single-stage and multistage FET amplifiers. Finally, some speculation is attempted in regard to the possible reductions in noise figure to be expected from technological and design improvements of GaAs FET's.     

Determination of the Electrode Capacitance Matrix for GaAs FET's

In this paper, a method is presented which provides the electrode capacitance matrix for GaAs FET's. The method incorporates a Green's function, valid for conductors printed on or embedded in a grounded substrate, with the moment method technique. Although calculations for various geometries of printed conductors are considered, emphasis is placed on the computation of self- and mutual-capacitances for the source, gate, drain equivalent circuit of a GaAs FET. As an example, the speed power characteristics of a depletion-rnode GaAs FET inverter circuit are examined, as a function of device width, pad and gate length.     

Above 10 GHz frequency dividers with GaAs advanced saint and air-bridge technology

GaAs advanced SAINT without excess gate metal overlap on the dielectric film and air-bridge technology are applied to dual-clocked BFL M/S binary frequency dividers. Operation above 10 GHz is achieved owing to reduction of gate parasitic capacitances and parasitic capacitances between interlayer lines.     

High-speed GaAs dynamic frequency divider using a double-loopstructure and differential amplifiers

GaAs 2.0-8.0-GHz and 6.0-10.5-GHz dynamic frequency dividers have been developed. These dynamic dividers have a double-loop structure using a differential amplifier for high-speed and stable operation despite supply-voltage fluctuations. This structure operates from a single voltage supply. An advanced WSi self-aligned gate process technology (0.1-μm long gate) was used to improve the high-frequency characteristics of the FET     

GaAs dual-gate Schottky-barrier FET's for microwave frequencies

The benefits inherent in the tetrode structure and the potential of GaAs are combined to realized a dual-gate FET with low noise and a wide dynamic range at microwave frequencies. A design theory of the dual-gate FET is constructed on the basis of the Lehovec-Zuleeg model for single-gate FET's. The theory has led to a new device structure having a second gate with a deeper pinchoff voltage than the first which shows improved gain and noise performance. Also derived is the importance of minimizing parasitic feedthrough due, for example, to packages. Samples were fabricated using n-type epitaxial GaAs. The first and second gates were Schottky barriers, 1.2 and 2.5 µm long. The improved channel structure was accomplished by reducing the thickness of the epitaxial layer under the first gate. Samples were mounted and characterized in specially designed small-size ceramic packages with a feedthrough capacitance of only 0.004 pF. The possibility of gain control by means of second gate bias over a wide bandwidth is demonstrated.     

Extremely low-noise performance of GaAs MESFETs with wide-headT-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-μm Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L_h) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anhold's method. A current gain cutoff frequency (f_T) and a maximum stable gain (MSG) decrease monotonously as L_h increases on account of parasitic capacitance. However, the device with L_h of 1.0 μm, which has lower gate resistance than 1.0 Ω, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMT's     

Self-aligned submicron gate digital GaAs integrated circuits

Digital normally-off (ENFET) GaAs integrated circuits have been fabricated using a novel self-aligned gate process that has produced high speed ring-oscillators with propagation delays as low as 25 ps and other low power circuits with power dissipation as small as 16 µW (at room temperature). The process is unique in that it permits control of parasitic FET source resistance and gate capacitance and also can achieve submicron gate lengths using conventional optical lithography.     

Broadband GaAs FET optical front-end circuit up to 5.6 GHz

Design and performance of transimpedance preamplifiers for multi-gigabit/s optical repeaters are reported using 0.3 ?m gate length GaAs FETs and a Ge-APD with a sensitive area of 30 ?m diameter. Through reduction of parasitic inductance and stray capacitance in chip assembly, a 3 dB down bandwidth of 8.2 GHz is achieved without a Ge-APD. A 3 dB down bandwidth of 5.6 GHz and good pulse response to 6.5 Gbit/s RZ pattern optical signals are achieved in an optical front-end circuit with a Ge-APD.     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

A new low-noise AlGaAs/GaAs 2DEG FET with a surface undoped layer

A high-performance N-AlGaAs/GaAs selectively doped two-dimensional electron gas (2DEG) FET with a surface undoped layer has been designed and demonstrated. Simple analysis based on the short-channel approximation revealed that an increase in a total layer thickness between a gate electrode and 2DEG at a hetero-interface results in a higher cutoff frequency and a lower noise figure than conventional 2DEG FET's. This is because the gate capacitance can be markedly reduced without a significant decrease in the transconductance owing to a parasitic source resistance. The surface undoped layer intentionally employed in this work can permit the total layer thickness to increase, i.e., the gate capacitance to reduce, without changes in the 2DEG density and in the source resistance. This structure also gives high gate breakdown voltage because of a small neutral region in n- (AlGa)As and a low surface electron field, which possibly yields excellent performance 2DEG FET's for practical use. Fabricated (AlGa)As/ GaAs 2DEG FET's exhibited noticeable room-temperature performances of 0.95-dB noise figure with 10.3-dB associated gain at 12- and 45-GHz cutoff frequency. These are the best data ever reported for 0.5-µm gate length FET's.     

Planar GaAs MOSFET integrated logic

Selective and multiple ion implantations directly into a semi-insulating GaAs substrate were utilized to fabricate planar integrated circuits with deep-depletion plasma-grown native oxide gate GaAs MOSFET's. 1.2-µm gate 27-stage enhancement/depletion (E/D) type ring oscillators, with the circuit optimized to reduce parasitic capacitance, were fabricated (using conventional photolithography) to assess the speed-power performance in digital applications. A minimum propagation delay of 72 ps with a power-delay product of 139 fJ was obtained, making these devices the fastest among current GaAs and Si logic fabricated by conventional photolithography. A minimum power-delay product of 36 fJ with a propagation delay of 157 ps was obtained. The power-delay product is comparable with that of 1.2-µm gate GaAs E-MESFET logic, and the speed is more than twice as great. This paper includes a comparison of the theoretical cut off frequency of MESFET and MOSFET logic devices operating in depletion mode. Results indicate that MOSFET logic has superior potential for high-speed operation.     

0.3-μm advanced SAINT FET's having asymmetricn+-layers for ultra-high-frequency GaAs MMIC's

Improvements in the microwave performance and noise performance of buried p-layer self-aligned gate (BP-SAINT) FETs are discussed. Specifically, a self-aligned gate electrode and an asymmetric n⁺ -layer structure are investigated. The self-aligned gate electrode reduces parasitic gate capacitances by 0.13 to 0.23 pF/mm compared with a conventional BP-SAINT FET. The asymmetric n⁺-layer structure reduces short-channel effects (drain conductance, threshold voltage shift, etc.) and gate-drain capacitance. A 0.3-μm gate-length FET was realized without an increase of short-channel effects by using an asymmetric n⁺-layer structure (advanced SAINT). Improvement of microwave performance is confirmed in this FET structure     

Saturated resistor load for GaAs integrated circuits

Saturated resistors, two-terminal load devices, have been fabricated and evaluated as pull-up loads for GaAs digital integrated circuits. The saturated resistor loads exhibit superior device characteristics compared with FET active loads. Up to 100-percent improvement in the uniformity Of the saturation current has been obtained. Ring oscillators with saturated resistor pull-up loads have shown ∼ 20-percent lower speed-power products than ring oscillators with FET active loads. This superior circuit performance is attributed to 1)no gate capacitance, and 2) less backgating effect. Reliability studies using accelerated aging have shown that circuits are more reliable when saturated resistor loads are used.     

Compensation of parasitic source capacitance in an FET differential amplifier

The amplitude and phase responses and high-frequency stability of an FET differential amplifier can be improved by compensating the parasitic source capacitance with a small capacitor between the gate and source of the input FET. This provides a significant improvement in the performance of oscillators and tuned or wideband amplifiers.     

Large-signal criteria for the design of GaAs FET distributed power amplifiers

An analysis of the GaAs FET distributed network for power amplification shows that the principal circuit values and performance characteristics can be expressed in terms of the GaAs FET large-signal voltages, currents, and power per millimeter of gate width, together with the required power and bandwidth only. The method is useful as a first design step in which the FET structure and distributed network are designed together to realize a monolithic traveling-wave power amplifier.     

FET大信号模型中等效电容方程的改进

精确地描述FET器件大信号微波特性阻抗对单片微波集成电路设计极其重要。为了能准确地模拟FET器件大信号微波特性,在大信号器件模型中,有必要研究栅等效电容模型,尤其在高频段。在总结前人研究的基础上,构造了新型的栅源/栅漏电容方程。通过与6×80μm GaAs PHEMT器件大信号负载牵引测试数据的对比,表明:精确的栅等效电容模型极大地提高非线性模型对FET大信号特性的预测能力。这将有助于器件模型和MMIC设计。     

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance Rsand gate capacitance Cg, the shallow n⁺implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance gm, low source resistance Rs, small gate capacitance Cg, and small deviation of threshold voltagepart V_{th}, and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.     

Low-power gigabit logic by GaAs SSFL

Experimental results on improved GaAs Schottky-barrier coupled Schottky-barrier gate FET logic (SSFL) are reported. A 13-stage ring oscillator, gate dimensions 1.2×20 ?m2, showed tpd=55 ps/gate at P=3.5 mW/gate. Also, a divide-by-two circuit was confirmed, starting normal operation from a single initialisation pulse.     

An analytical approach to the capacitance-voltage characteristicsof double-heterojunction HEMTs

The two-dimensional electron gas concentration and capacitance in AlGaAs/GaAs/AlGaAs double-heterojunction high-electron-mobility transistors (DH-HEMTs) are calculated as a function of gate voltage using simple iterative solutions of analytical equations. The results show very good agreement with experimental data, as well as with characteristics predicted by complex numerical methods. The calculations are extended to predict the capacitance-voltage characteristics in the presence of parasitic conduction when the gate does not fully control the two-dimensional gas. The developed charge control and capacitance models are easy and inexpensive to run. They are therefore very useful for microwave circuit designs. Furthermore, they can be used for performance prediction and design optimization of DH-HEMTs. The influence of technological parameters, such as layer thickness and aluminum composition, on device performance are presented