A design system for on-chip oversampling A/D interfaces

An integrated design system for the analysis, design, and implementation of on-chip A/D interfaces using oversampling A/D converters has been developed. The system unifies a diverse base of design knowledge required for mixed analog and digital circuits and covers the design process from specification to mask layout for a variety of configurations. A hierarchical design estimation approach was used to guide system development, allowing designers to quickly estimate performance at a high level of abstraction and to update these estimates as the design progresses. At lower levels of abstraction, architecture templates are used to encapsulate information about particular filter implementations and to simplify the design process. Designers use performance estimates to guide the design process and to make the critical decisions about the choice of algorithm and architecture. Accurate simulation models have been integrated into the design system to allow examination and verification. Results from a 14-b signal acquisition module are presented to illustrate use of the tools and the typical tradeoffs faced at different levels of abstraction. This system illustrates how various design automation techniques can be combined to provide better optimization for a complex system design and to shorten design cycles for custom converters to a matter of days     

Calibrating simulation tools for nanometer designs

Next-generation silicon processes will challenge system-on-a-chip (SOC) designers to increase the accuracy of the data they feed to their high level tools. Minimum circuit features of 250 nm (0.25 μm) or below are demanding. The tools that simulate them will need transistor models and interconnect parameters that reflect nothing less than the actual physical properties of the process in which ICs are to be manufactured. These silicon-calibrated models can then pass their accuracy on to capable transistor-level simulation tools. Silicon calibration calls for for tighter relationships and more effective communication than is now found among silicon foundries electronic design automation (EDA) companies, and IC design groups. The EDA tools must be regularly updated, to equip design engineers to cope with the challenges of nanometer design. Although simulation tools may never predict silicon behavior with 100 percent accuracy, EDA tool vendors and IC fabrication facilities share a responsibility to calibrate their tool suites as closely as possible with actual silicon     

SoC设计中的低功耗策略

低功耗设计已经成为片上系统(SoC)设计的主题.当今的设计已经从过去的性能、面积二维目标转变为性能、面积和功耗的三维目标.本文深入探讨了片上系统设计中的低功耗设计策略,在晶体管和逻辑门级、寄存器传输级和系统结构级各设计抽象层次上阐述了低功耗设计所面临的问题,并给出了各级的低功耗优化策略.     

Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process, from system specifications to integrated circuit layout, is carried out with the aid of specialized computer programs for the analysis, synthesis, and optimization at each design level: the filter network, the architecture, and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed which is integrated using a 5-/spl mu/m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis and optimization aids at each design level it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput, and moderate power consumption.     

An overview of today’s high-level synthesis tools

High-level synthesis (HLS) is an increasingly popular approach in electronic design automation (EDA) that raises the abstraction level for designing digital circuits. With the increasing complexity of embedded systems, these tools are particularly relevant in embedded systems design. In this paper, we present our evaluation of a broad selection of recent HLS tools in terms of capabilities, usability and quality of results. Even though HLS tools are still lacking some maturity, they are constantly improving and the industry is now starting to adopt them into their design flows.     

A novel high-throughput method for table look-up based analog design automation

Analog circuit synthesis ofen requires repeated evaluations of circuit under design to reach the final design goals. Circuit simulations using SPICE can provide accurate assessment of circuit performance. Spice simulations are costly and incur significant overhead. A faster transistor-level evaluation is needed to provide higher throughput for synthesis applications. Further, miniaturization of FET’s has added physical effects into SPICE models, which complicated their equations with every generation. That complication has forced analog synthesis tool developers and circuit designers alike to perform circuit evaluations using SPICE.Analog circuit design tools largely failed in their declared goal, to take over circuit optimization tasks from human designers mainly due to over simplications using custom-developed equations for evaluating circuit performance. Since it is more and more difficult to accurately capture transistor behavior with each new generation of silicon technology, a more practical approach to analog design automation is to keep human engineers at the center of the design flow by providing them with as much needed decision-supporting data as quickly as possible. Mapping the trade-off landscape of a topology with respect to design specifications, for example, can save designers trial and error time. This approach to analog design automation requires less accuracy from the simulation sign-off tools, such as SPICE. However, it demands much faster response for circuit performance evaluations with sufficient accuracy.In this paper, a new solution to both calculation overheads and model complexity is proposed. The proposed fast evaluation method uses a novel look-up table (LUT) algorithm to extract circuit information from complex physics-based transistor models used by SPICE. The model makes use of contemporary memory space, by replacing equations with look-up tables in addition to advanced interpolation methods. The achieved improvement is over 100× throughput and complete decoupling from physical phenomena compared to SPICE run-time, in exchange for few gigabytes of data per device. Examples are shown for the effectiveness of replacing SPICE with our model in a transistor sizing flow, while keeping 99% of the samples inside the 5% error range on 180 nm and 40 nm CMOS processes. The proposed solution is not intended to replace sign-off quality tools, such as SPICE. Rather, it is intended to be used as a fast performance evaluator in analog design automation flows.     

A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

There has been a constant endeavor towards improving the available circuit design automation tools to match technological advancements in the electronic industry. However, inadequate research efforts in the analog domain are holding back the exploitation of advanced technologies. A dearth of design expertise in the analog domain is the principal driving force for the growth of Design Automation (DA) tools. Transistor sizing is one of the most crucial steps in the analog IC design. In this paper, we put forward a new computer aided design framework for the sizing of transistors in MOS Integrated Circuit (IC) amplifiers by incorporating powerful modeling capabilities of Artificial Neural Networks (ANN). ANNs have proven to be efficient and accurate modeling tools in several applications. The proposed tool is capable of directly computing transistor related design parameters, of the MOS IC amplifier and associated peripheral circuitry. The proposed tool thus avoids several time-consuming simulations and/or tuning runs at the very bottom level of analog IC amplifier implementation, using a given CMOS process. It also reduces manual intervention in the design process, thus enhancing the automation of the design process. This paper presents design examples of several analog IC functional modules that are developed and verified successfully.     

Simulation of thermal diffusion in transistors using transmissionline matrix modelling

A variety of solid-state devices are being developed for use in systems where they are required to produce pulses of microwave power at specified duty cycles. The design of these devices is interesting as they will be smaller and have less thermal capacity than an equivalent continuous-wave source generating the same microwave power. This size reduction is important as it can result in improved electrical efficiency and a higher frequency of operation. The author describes the application of transmission line matrix diffusion modelling to the transient thermal design of a transistor structure and compares the technique with finite difference and finite element approaches     

Power analysis of embedded software: a first step towards softwarepower minimization

Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical component of the design specification of these systems. At present, however, power analysis tools can only be applied at the lower levels of the design-the circuit or gate level. It is either impractical or impossible to use the lower level tools to estimate the power cost of the software component of the system. This paper describes the first systematic attempt to model this power cost. A power analysis technique is developed that has been applied to two commercial microprocessors-Intel 486DX2 and Fujitsu SPARClite 934. This technique can be employed to evaluate the power cost of embedded software. This can help in verifying if a design meets its specified power constraints. Further, it can also be used to search the design space in software power optimization. Examples with power reduction of up to 40%, obtained by rewriting code using the information provided by the instruction level power model, illustrate the potential of this idea     

Design for reliability of generic sensor interface circuits

Numerous applications require the use of robust and reliable integrated circuits. In order to develop such circuits, a wide variety of influences need to be considered and also compensated if necessary. For a complete consideration of all reliability issues, the circuit has to be investigated on different levels of abstraction and together with the complete overlying system. These requirements are addressed in this work by using cross-layer design methods for the development of a generic sensor interface as an example for a complex integrated circuit. During the development, a reliability-aware design is used and major physical effects are taken into account, which alter the overall behavior of the system. Furthermore, modeling techniques are applied to port influences and circuit components from one level of abstraction to another. Possible countermeasures and compensation techniques for a reliable circuit design are also analyzed on transistor and system level. The result is a sensor interface circuit, which can be used to investigate all effects of interest and suitable countermeasures on different abstraction levels.     

Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM

IBM's high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a transistor width tuner that optimizes performance and area. We also describe the application of electrical rule checking used to enforce consistent design practices. Finally, we discuss a macro extraction tool that determines parasitic resistance and capacitance of interconnect from a layout     

Multilevel optimization in the design of a high-performance GaAsmicrocomputer

Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer     

Modeling the wiring of deep submicron ICs

The semiconductor industry has fuelled the enormous growth of the electronics industry with an unending flow of even better, faster, cheaper chips. These chip improvements, in turn, have been stoked by steady progress in semiconductor process technology, which, as Moore's law predicts, doubles IC transistor counts every 18 months. Supporting this progress is the infrastructure provided by design tools, which today, however, comes up short against the process advances crucial to tomorrow's chips. Why? Because present design tools and methodologies presuppose that chip performance is determined by the transistor. That supposition may have been true a few years ago, but no more. Chip performance now depends on the interconnect. The new significance of interconnect performance is driving changes throughout the logic design flow because logic synthesis engines and other tools assume that timing can be predicted before the physical layout is done. But pre-layout and post-layout timing values no longer converge, and design tools must evolve to match this change in process technology. The first step is for vendors to create tools that accurately predict the performance of designs in this interconnect-dominated technology. The author discusses the importance of timing, 2D and 3D modelling of the interconnects, and deep submicron effects     

Modelling the operation of pass transistor and CPL gates

Pass transistor logic and complementary pass-transistor logic (CPL) are becoming increasingly important in the design of a specific class of digital integrated circuits owing to their speed and power efficiency as compared with conventional CMOS logic. In this paper, a simple and very accurate technique for the timing analysis of gates that involve pass transistor logic is presented. This investigation offers for the first time the possibility of simulating pass transistor and CPL gates by partitioning the behaviour of complex structures into well defined subcircuits whose interaction is studied separately. Using the proposed analysis, which is validated by results for two submicron technologies, most pass-transistor logic styles can be modelled efficiently. Consequently, a significant speed advantage can be gained compared with simulation tools that employ numerical methods such as SPICE.     

Rule checking at the register level

For huge, complex circuits, checking design rules at a level of abstraction above the gate level can identify architectural problems early on. Today's more mature equivalence checkers require little user input, but are not able to verify the quality or correctness of an original design. By adding RTL-DRC capability to formal verification tools, they can be used to find and correct RTL design problems early in the design cycle, with little or no extra effort necessary on the part of the designer     

Test Challenges in Nanometer Technologies

Device scaling has led to the blurring of the boundary between design and test: marginalities introduced by design tool approximations can cause failures when aggressive designs are subjected to process variation. Larger die sizes are more vulnerable to intra-die variations, invalidating analyses based on a number of given process corners. These trends are eroding the predictability of test quality based on stuck-at fault coverage. Industry studies have shown that an at-speed functional test with poor stuck-at fault coverage can be a better DPM screen than a set of scan tests with very high stuck-at fault coverage. Contrary to conventional wisdom, we have observed that a high stuck-at fault test set is not necessarily good at detecting faults that model actual failure mechanisms. One approach to address the test quality crisis is to rethink the fault model that is at the core of these tests. Targeting realistic fault models is a challenge that spans the design, test and manufacturing domains: the extraction of realistic faults has to analyze the design at the physical and circuit levels of abstraction while taking into account the failure modes observed during manufacture. Practical fault models need to be defined that adequately model failing behavior while remaining amenable to automatic test generation. The addition of these fault models place increasing performance and capacity demands on already stressed test generation and fault simulation tools. A new generation of analysis and test generation tools is needed to address the challenge of defect-based test. We provide a detailed discussion of process technology trends that are responsible for next generation test problems, and present a test automation infrastructure being developed at Intel to meet the challenge.     

SoC门级功耗分析方法

随着IC设计规模的增大和运行频率的提高,设计中低功耗的需求也随之提高,在芯片投片之前,能够比较准确的评估出芯片的功耗是当前设计中非常关键的技术点之一。比较四种不同层次的功耗分析方法,门级功耗分析兼有精度高,分析速度快的优点。根据SPI接口电路实践,描述了门级功耗工具的使用方法,并通过门级和晶体管级分析的对比测试证明该方法能较为准确的估算出新品的功耗,为SoC项目的正常研发提供帮助。     

Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design

System-level design (SLD) is considered by many as the next frontier in electronic design automation (EDA). SLD means many things to different people since there is no wide agreement on a definition of the term. Academia, designers, and EDA experts have taken different avenues to attack the problem, for the most part springing from the basis of traditional EDA and trying to raise the level of abstraction at which integrated circuit designs are captured, analyzed, and synthesized from. However, my opinion is that this is just the tip of the iceberg of a much bigger problem that is common to all system industry. In particular, I believe that notwithstanding the obvious differences in the vertical industrial segments (for example, consumer, automotive, computing, and communication), there is a common underlying basis that can be explored. This basis may yield a novel EDA industry and even a novel engineering field that could bring substantial productivity gains not only to the semiconductor industry but to all system industries including industrial and automotive, communication and computing, avionics and building automation, space and agriculture, and health and security, in short, a real technical renaissance. In this paper, I present the challenges faced by industry in system level design. Then, I propose a design methodology, platform-based design (PBD), that has the potential of addressing these challenges in a unified way. Further, I place methodology and tools available today in the PBD framework and present a tool environment, Metropolis, that supports PBD and that can be used to integrate available tools and methods together with two examples of its application to separate industrial domains