Dynamic characterization of a-Si TFT-LCD pixels

A dynamic analysis of an amorphous silicon (a-Si) Thin-Film-Transistor-Liquid-Crystal-Display (TFT-LCD) pixel is presented using new a-Si TFT model and new Liquid Crystal (LC) capacitance models for SPICE simulators. This analysis is useful to all Active Matrix LCD designers for evaluating and predicting the performance of LCD's. The a-Si TFT model is developed to simulate important a-Si TFT characteristics such as off-leakage current, threshold voltage shift due to voltage stress and temperature, localized states behavior, and bias- and frequency-dependent gate to-source and gate-to-drain capacitance. In addition, the LC Capacitance model is developed using simplified empirical equations. The modeling procedure is useful to TFT and LCD designers who need to develop their own models. Since our experiments simulate critical TFT-LCD transient effects such as the voltage drop due to gate-to-source capacitance and dynamic off-leakage current, it is possible to accurately characterize TFT-LCD's in the time domain. The analysis and models are applicable to today's optical characterizations of Flat-Panel-Displays (FPD's)     

A new poly-Si TG-TFT with diminished pseudosubthreshold region: theoretical investigation and analysis

In this paper, we have proposed a new poly-Si triple-gate thin-film transistor (TG-TFT) where the front gate consists of two materials and three sections in order to reduce the OFF state leakage current without affecting the ON state voltage. We have used one and three grain-boundaries in the channel for analyzing the electrical characteristics of the poly-Si TG-TFT. The key idea in this paper is to make the dominant conduction mechanism in the channel to be controlled by the accumulation charge density modulation by the gate and not by the gate-induced grain barrier lowering. As a result, we demonstrate that the TG-TFT exhibits a highly diminished pseudosubthreshold region resulting in a substantial OFF state leakage current without any significant change in the ON voltage when compared to a conventional poly-Si TFT (C-TFT). Using two-dimensional and two-carrier device simulation, we have examined various design issues of the TG-TFT and provided the reasons for the improved performance.     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

A new poly-Si TFT structure with air cavities at the gate-oxideedges

We propose a new poly-Si TFT structure employing air cavities at the edges of gate oxide in order to reduce the threshold voltage shift after electrical stress and to decrease the large leakage current. Due to the low dielectric constant of air, the air cavity behaves as a thick insulator reducing the vertical electric field near the drain, so that poly-Si region under air cavity acts as an offset. The new poly-Si TFT structure has been successfully fabricated by employing wet etching of the gate oxide followed by atmospheric pressure chemical vapor deposition (APCVD) oxide deposition. Our experimental results show that the leakage current is considerably reduced without decrease of the on-current and the device stability such as threshold voltage shift under high-gate bias is also improved     

A novel self-aligned polycrystalline silicon thin-film transistorusing silicide layers

A novel self-aligned polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated using the three layers of poly-Si, silicon-nitride, and thin amorphous silicon. Gate and source/drain silicide formation was carried out simultaneously following silicon nitride and amorphous silicon patterning, enabling the use of only two mask steps for the TFT. The fabricated poly-Si TFT using laser annealed poly-Si exhibited a field-effect mobility of 30.6 cm²/Vs, threshold voltage of 0.5 V, subthreshold slope of 1.9 V/dec., on/off current ratio of ~10⁶, and off-state leakage current of 7.88×10^-12 A/μm at the drain voltage of 5 V and gate voltage of -10 V     

基于单色光下ADS模式TFT-LCD闪烁漂移的对比研究

基于挠曲电效应理论,本文对比研究了红、绿、蓝3种单色光对ADS 模式TFT-LCD 闪烁漂移的影响。主要考察了3种单色背光在能量相同以及不同亮度条件下的闪烁漂移和TFT光漏电流[Photo I_off]特性。实验结果表明I_off在正常范围内变化时,并不显著影响闪烁漂移量,初步认为:不同光照条件下离子的产生数量和产生速度差异是该条件下导致闪烁漂移的主要因素。     

Low temperature polycrystalline silicon thin film transistor withsilicon nitride ion stopper

The authors have fabricated a new low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) with silicon nitride (SiN _x) ion-stopper and laser annealed poly-Si. The fabricated poly-Si TFT using SiN_x as the ion-stopper as well as the gate insulator exhibited a field effect mobility of 110 cm²/Vs, subthreshold voltage of 5.5 V, subthreshold slope of 0.48 V/dec., and on/off current ratio of ~10⁶. Low off-state leakage current of 2.4×10^-2 A/μm at the drain voltage of 5 V and the gate voltage of -5 V was achieved     

TFT-LCD高温光照漏电流改善研究

造成TFT不稳定的问题点一般认为有两种:一是沟道内半导体材料内部的缺陷,另一个是栅极绝缘层内的或是绝缘层与沟道层界面的电荷陷阱。TFT-LCD在长期运行时由于高温及光照的影响会导致漏电流增加,进而对TFT造成破坏。分析研究表明,TFT沟道在刻蚀完成后,沟道内部存在一定的缺陷以及绝缘层与沟道层界面存在电荷陷阱,平面电场宽视角核心技术-高级超维场转换技术型产品由于设计的原因面临着如果进行氢处理会导致与其与氧化铟锡中的铟发生置换反应,导致铟的析出,所以无法采用氢处理。理论分析表明Si-O键稳定,本文主要介绍通过氯气/氧气和六氟化硫/氧气对TFT沟道进行处理改善高温光照漏电流。结果表明,通过氯气/氧气和六氟化硫/氧气处理TFT沟道后,高温光照漏电流从18.19pA下降到5.1pA,可见氯气/氧气和六氟化硫/氧气对沟道处理可有效改善高温光照漏电流。     

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the on state, an inversion layer is induced by the subgate as a drain so that the on current is still high and the poly-Si region under the subgate behaves as an offset, reducing the off-state leakage current during the off-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum off-state leakage current of the new TFT is decreased from 1.4/spl times/10/sup -10/ to 1.3/spl times/10/sup -11/ without sacrifice of the on current. In addition, the on-off current ratio is significantly improved.     

Study of polycrystalline-Si thin-film transistors with different channel layer thickness at low bias voltage

A sub-micron poly-Si TFT device, operating at a drain bias of 1.5 V, has been studied with respect to channel layer thickness. A thinner channel layer may lead to better good gate control over the entire channel region, thus resulting in a lower threshold voltage. Similarly, under negative gate bias, a thinner channel layer would sustain larger vertical electric field. However, a thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-Si TFT device with a thinner channel layer, the leakage current would be more effectively suppressed by the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-Si TFT device with 20-nm channel layer can cause an off-state leakage of about 0.1 pA/μm at a drain bias of 1.5 V, and an on/off current ratio higher than 8 orders can be achieved.     

Stable polycrystalline silicon TFT with MICC

We studied the bias-induced changes in the performance of the poly-Si thin-film transistor (TFT) by metal-induced crystallization of amorphous silicon through a cap layer (MICC) poly-Si. The p-channel poly-Si TFT exhibited a field-effect mobility of 101 cm/sup 2//V/spl middot/s and a minimum leakage current of <1.0/spl times/10/sup -12/ A//spl mu/m at V/sub ds/=-10 V. The MICC poly-Si TFT performance changes little by either gate or hot-carrier bias stress. The better stability appears to be due to the smooth surface of MICC poly-Si, which is /spl sim/2 nm that is much smaller than that (13 nm) of a laser-annealed poly-Si.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

A p-channel poly-Si/Si1-xGex/Si sandwichedconductivity modulated thin-film transistor

A p-channel poly-Si/Si_1-xGe_x/Si sandwiched conductivity modulated thin-film transistor (CMTFT) is proposed and demonstrated in this paper for the first time. This structure uses a poly-Si/Si_1-xGe_x/Si sandwiched structure as the active layer to avoid the poor interface between the gate oxide and the poly-Si_1-xGe_x material. Also an offset region placed between the channel and the drain is used to reduce the leakage current. Furthermore, the concept of conductivity modulation in the offset region is used to provide high on-state current. Results show that this structure provides high on-state current as well as low leakage current as compared to that of conventional offset drain TFTs. The on-state current of the structure is 1.3-3 orders of magnitude higher than that of a conventional offset drain TFT at a gate voltage of -24 V and drain voltage ranging from -15 to -5 V while maintaining comparable leakage current     

Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer

Submicron-meter poly-Si tunneling-effect thin-film transistor (TFT) devices with a thinned channel layer have been investigated. With reducing the gate length to be shorter than 1 μm, the poly-Si TFT device with conventional MOSFET structure is considerably degraded. The tunneling field-effect transistor (TFET) structure can be employed to alleviate the short channel effect, thus largely suppressing the off-state leakage. However, for a poly-Si channel layer of 100 nm thickness, the TFET structure causes a small on-state current, which may not provide well sufficient driving current. By reducing the channel layer thickness to be 20 nm, the on-state current for the TFET structure can be largely increased, due to the enhanced bending of energy band for a thinned channel layer. As a result, for the TFET poly-Si TFTs at a gate bias of 5 V and a drain bias of 3 V, a 20-nm channel layer leads to an on-state current of about 1 order larger than that by a 100-nm channel layer, while still keeping an off-state leakage smaller than 0.1 pA/μm. Accordingly, the submicron-meter TFET poly-Si TFT devices with a thinned channel layer would show good feasibility for implementing high packing density of poly-Si TFT devices.     

Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With ${hbox{Pr}}_{2}{hbox{O}}_{3}$ Gate Dielectric

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k Pr₂O₃ as gate dielectric is investigated for the first time. Using the Pr₂O₃ gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr₂O₃/poly-Si interface to improve the device electrical properties. The Pr₂O₃ TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr₂O₃ TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr₂O₃ TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr₂O₃ TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.     

干法刻蚀工艺对TFT-LCD Flicker改善的研究

为了对TFT-LCD中的闪烁不良进行改善,本文通过研究TFT-LCD中干法刻蚀(Nplus Etch)对TFT特性的影响,以此对刻蚀条件(Power、Gas)进行优化,达到降低Photo-Ioff的目的。实验结果表明,当干法刻蚀主工艺条件为:Source/Bias=4k/5k、Press=90mT、SF6/O2=1.1k/3kml/min,AT Step条件为:Source/Bias=2k/2k、Press=100mT、SF6/O2=3k/3kmL/min时,Photo-Ioff由量产最初的58.15降至20.52,闪烁由15%~30%降至10%以下。干法刻蚀工艺条件的优化对TFT特性以及闪烁有明显改善效果。     

Poly-Si TFT push-pull analogue buffer for integrated data driversof poly-Si TFT-LCDs

A new push-pull analogue buffer for the integrated data driver circuit of polycrystalline silicon (poly-Si) thin-film transistor liquid crystal displays (TFT-LCDs) is proposed. The proposed push-pull analogue buffer is composed of a complementary source follower output stage, a capacitor, and three analogue switches. It has high immunity to the variation of poly-Si TFT characteristics and low power consumption     

TFT-LCD制程对低频横纹色差的影响及研究

LC配向的均一性在LCD中是必不可少的,光配向制程是通过施加紫外偏振光照射在IPS(In-Plane Switch)LCD中形成液晶配向沟槽的一种技术,然而紫外光照射的同时会损伤TFT器件,使非晶硅层产生光生载流子,电子发生迁移,导致TFT漏电流从而影响图像品质,产生横纹色差。在低频时,栅极开关时间延长,相邻扫描线之间容易发生混充电现象,部分充电截止的像素重新充电,从而使横纹色差变严重。本文从制程和电性调整方面对低频横纹色差进行了研究,结果表明:(1)紫外光照射后进行烘烤,可以有效降低漏电流,高温度(240℃)+长时间(4 200s)改善低频横纹色差效果佳(比例:0.00%);(2)延长Out Enable(4.8μs)+降低V_(gh)(18V)+提高GOA(Gate On Array)电路中电压V_(SS_Q)(-7.5V),改善低频横纹色差效果佳(比例:0.00%)。     

Inverted Staggered Poly-Si Thin-Film Transistor With Planarized SOG Gate Insulator

In this letter, we have studied the inverted staggered thin-film transistor (TFT) using a spin-on-glass (SOG) gate insulator and a low-temperature polycrystalline silicon (poly-Si) by Ni-mediated crystallization of amorphous silicon. The p-channel poly-Si TFT exhibited a field-effect mobility of 48.2 cm²/V ldr s, a threshold voltage of -4.2 V, a gate-voltage swing of 1.2 V/dec, and a minimum off-current of < 4 times 10^-13A/ mum at V_ds = -0.1 V. Therefore, the gate planarization technology by SOG can be applicable to low-cost large-area poly-Si active-matrix displays.     

A High-Performance Polysilicon Thin-Film Transistor Built on a Trenched Body

In this paper, a high-performance polysilicon thin-film transistor (poly-Si TFT) with a trenched body is proposed, fabricated, and studied. This new trenched TFT can be easily produced by filling and etch-back technology without destroying the channel film quality. The addition of the body trench is found to reduce the off-state leakage current by 70% on average, because the trench induces a carrier scattering effect in the poly-Si grain-boundary traps, thereby affecting the leakage path. Although the off-state current is substantially reduced, the on-state current is comparable with that of a conventional TFT. Our multiple-trenched-body TFT is also shown to improve the breakdown voltage by 11%.