Effects of ionizing radiation on n-channel MOSFET's fabricated in zone-melting-recrystallized Si films on SiO2

We have investigated the effects of irradiation with 1.5 MeV electrons on the electrical characteristics of n-channel MOSFET's fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates. With a -15 V bias applied to the Si substrate during irradiation and device operation, the subthreshold leakage current remains below 0.2 pA/µm (channel width) for ionizing doses up to 10⁶rad(Si). The negative substrate bias also reduces the shift of threshold voltage to less than 0.3 V for devices with 50 nm-thick gate oxide.     

Radiation-hardened silicon-on-insulator complementary junction field-effect transistors

The effects of total-dose radiation have been investigated for complementary junction field-effect transistors fabricated in zone-melting recrystallized Si films on SiO2-coated Si substrates. With a - 5-V bias applied to the Si substrate during irradiation and device operation, both n- and p-channel devices show low threshold-voltage shift (<-0.09 and <-0.12 V, respectively), low leakage currents (<- 1- and <3-pA/µm channel width, respectively) and small transconductance degradation (<15 percent) for total doses up to 10⁸rad (Si).     

Radiation-hardened silicon-on-insulator junction field-effect transistors fabricated by a self-aligned process

A self-aligned process has been developed for fabricating JFET's in zone-melting-recrystallized (ZMR) Si films on SiO2-coated Si substrates. This process has been used to fabricate n-JFET's exhibiting transconductance values up to 63 mS/mm. For 228 devices within an area of about 4 × 4 cm², the mean threshold voltage is 578 mV and the standard deviation is 22 mV. With a -15-V bias applied to the Si substrate during irradiation and device operation, the devices show low threshold voltage shift (< -75 mV) and small transconductance degradation (∼30 percent) for exposure to total-dose radiation of 10⁸rad(Si).     

A dc and microwave comparison of GaAs MESFET's on GaAs and Si substrates

In order to assess GaAs on Si technology, we have made a performance comparison of GaAs MESFET's grown and fabricated on Si and GaAs substrates under identical conditions and report the first microwave results. The GaAs MESFET's on Si with 1.2-µm gate length (290-µm width) exhibited transconductances (gm) of 180 mS/mm with good saturation and pinchoff whereas their counterparts on GaAs substrates exhibited gmof 170 mS/mm. A current gain cut-off frequency of 13.5 GHz was obtained, which compares with 12.9 GHz observed in similar-geometry GaAs MESFET's on GaAs substrates. The other circuit parameters determined from S-parameter measurements up to 18 GHz showed that whether the substrate is Si or GaAs does not seem to make a difference. Additionally, the microwave performance of these devices was about the same as that obtained in devices with identical geometry fabricated at Tektronix on GaAs substrates. The side-gating effect has also been measured in both types of devices with less than 10-percent decrease in drain current when 5 V is applied to a pad situated 5 µm away from the source. The magnitude of the sidegating effect was identical to within experimental determination for all side-gate biases in the studied range of 0 to -5 V. The light sensitivity of this effect was also very small with a change in drain current of less that 1 percent between dark and light conditions for a side gate bias of -5 V and a spacing of 5 µm. Carrier saturation velocity depth profiles showed that for both MESFET's on GaAs and Si substrates, the velocity was constant at 1.5 × 10⁷cm/s to within 100-150 Å of the active layer-buffer layer interface.     

Electrical and material quality ofSi1-xGex/Si p-N heterojunctions produced bylimited reaction processing

Si_1-xGe_x/Si p-N heterojunctions prepared by a chemical vapor deposition technique, limited reaction processing (LRP) were characterized using DC electrical measurements, transmission electron microscopy (TEM), and X-ray topography. Heterojunctions with Si _1-xGe_x layer thickness ranging from 52 to 295 nm and a constant Ge fraction of 23% were fabricated to study the effect of increasing the number of misfit dislocations on the device characteristics. Devices with the thinnest layers (⩽120 nm) display forward characteristics with ideality factors of 1.01 and reverse leakage current densities of less than 4 nA/cm for a 5-V reverse bias. These thin-layer devices have dislocation spacings greater than 10 μm. Devices utilizing Si_1-xGe_x layers thicker than 200 nm have forward characteristics which clearly display the presence of recombination currents, and reverse leakage current densities greater than 290 nA/cm² at -5 V. The dislocation spacing in these devices is less than 1 μm. Ideal characteristics were found at room temperature in devices known to contain dislocations     

High-speed photoconductive switch based on low-temperature GaAs transferred on SiO/sub 2/-Si substrate

In this letter, we report high-speed photoconductive switches based on low-temperature (LT) grown GaAs on Si substrate. Epitaxially grown LT GaAs was separated from its substrate, transferred on an SiO/sub 2/-coated Si substrate and integrated with a transmission line. The 10/spl times/20-/spl mu/m/sup 2/ switches exhibit high breakdown voltage and low dark currents (<10/sup -7/ A at 100 V). The photoresponse at 810 nm shows electrical transients with /spl sim/0.55-ps full-width at half-maximum and /spl sim/0.37-ps decay time, both independent on the bias voltage up to the tested limit of 120 V. The photoresponse amplitude increases up to /spl sim/0.7 V with increased bias and the signal bandwith is /spl sim/500 GHz. The freestanding LT GaAs switches are best suited for ultrafast optoelectronic testing since they can be placed at virtually any point on the test circuit.     

Dark-Current Suppression in Metal–Germanium–Metal Photodetectors Through Dopant-Segregation in NiGe—Schottky Barrier

We demonstrate, for the first time, the application of dopant-segregation (DS) technique in metal-germanium- metal photodetectors for dark-current suppression and high-speed performance. Low defect density and surface smooth epi-Ge (~300 nm) layer was selectively grown on patterned Si substrate using two-step epi-growth at 400degC/600degC combined with a thin (~10 nm) low-temperature Si/Si_0.8 Ge_0.2 buffer layer. NiGe with DS effectively modulates the Schottky barrier height and suppresses dark current to ~10 ^-7 A at -1 V bias (width/spacing: 30/2.5 mum). Under normal incidence illumination at 1.55 mum, the devices show photoresponsivity of 0.12 A/W. The 3 dB bandwidth under - 1 V bias is up to 6 GHz.     

Low-noise back-illuminated AlxGa1-xN-basedp-i-n solar-blind ultraviolet photodetectors

We report the growth, fabrication and characterization of Al_0.4Ga_0.6N-Al_0.6Ga_0.4N back-illuminated, solar-blind p-i-n photodiodes. The peak responsivity of the photodiodes is 27 and 79 mA/W at λ≈280 nm for bias voltages of 0 V and -60 V, respectively, with a UV-to-visible rejection ratio of more than three decades (at 400 nm). These devices exhibit very low dark current densities (~5 nA/cm² at -10 V). At low frequencies, the noise exhibits a 1/f-type behavior. The noise power density is S₀≈5×10^-25 A²/Hz at -12.7 V and the detectivity (D*) at 0 V is estimated to be in the range of 4×10¹¹-5×10¹³ cm·Hz^1/2 /W. Time-domain pulse response measurements in a front-illumination configuration indicate that the devices are RC-time limited and show a strong spatial dependence with respect to the position of the incident excitation, which is mainly due to the high resistivity of the p-type Al_0.4Ga_0.6 N layer     

Optimised n-channel Si/SiGe HFETs design for VTH shift immunity

This paper reports on the effects of backgating on the sub-threshold characteristics of Si:SiGe n-channel heterojunction field effect transistors. The layer structure is optimised for small sub-threshold slope and negligible threshold voltage shift as a function of substrate bias. MEDICI simulations were carried out to minimize the body effect observed in the DC measurements of MOS-gated n-channel Si/SiGe HFETs. By doping profile engineering, we achieve virtually body effect free devices with a threshold voltage shift of 400 μV for a substrate bias changes of −2 V while maintaining a sub-threshold current slope near the theoretical limit.     

A 630-mS/mm GaAs MESFET with Au/WSiN refractory metal gate

GaAs MESFET's with a gate length as low as 0.2 μm have been successfully fabricated with Au/WSiN refractory metal gate n⁺-self-aligned ion-implantation technology. A very thin channel layer with high carrier concentration was realized with 10-keV ion implantation of Si and rapid thermal annealing. Low-energy implantation of the n⁺-contact regions was examined to reduce substrate leakage current. The 0.2-μm gate-length devices exhibited a maximum transconductance of 630 mS/mm and an intrinsic transconductance of 920 mS/mm at a threshold voltage of -0.14 V     

Si-gate CMOS devices on a Si/CaF2/Si structure

Si-gate CMOS inverter chains and 1/8 dynamic frequency dividers have been fabricated on a Si/CaF2/Si structure. A high-quality heteroepitaxial Si/CaF2/Si structure was formed by successive molecular-beam epitaxy of CaF2and Si. Transistors have been fabricated with an improved CMOS process that prevents crystal degradation during the fabrication process as much as possible. The maximum effective mobilities are about 570 and 240 cm²/V . s for n-channel and p-channel transistors, respectively. The inverter chain with an effective channel length of 2.0 µm has a delay time per gate of 360 ps. A maximum operating frequency of 300 MHz is obtained in the divider with an effective channel length of 2.5µm at a supply voltage of 5 V. These results indicate that the Si/CaF2/Si structure has potential for the fabrication of high-speed silicon-on-insulator devices.     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

AlGaN/GaN Metal–Oxide–Semiconductor High-Electron Mobility Transistors Using Oxide Insulator Grown by Photoelectrochemical Oxidation Method

A photoelectrochemical oxidation method was used to directly grow oxide layer on AlGaN surface. The annealed oxide layer exhibited beta-Ga₂O₃ and alpha-Al₂O₃ crystalline phases. Using a photoassisted capacitance-voltage method, a low average interface-state density of 5.1 times 10¹¹ cm^-2. eV^-1 was estimated. The directly grown oxide layer was used as gate insulator for AlGaN/GaN MOS high-electron mobility transistors (MOS-HEMTs). The threshold voltage of MOS-HEMT devices is -5 V. The gate leakage currents are 50 and 2 pA at forward gate bias of VGS = 10 V and reverse gate bias of V_GS = -10 V, respectively. The maximum value of g_m is 50 mS/mm of VGs biased at -2.09 V.     

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.     

High current p/p+-diamond Schottky diode

Epitaxial p-type Schottky diodes have been fabricated on p⁺ -substrate. While the activation energy of the epitaxial layer conductivity is 390 meV, that of the substrate is only 50 meV. At forward bias the substrate conductivity dominates above 150°C, leading for a 5×10^-5 cm² area contact to a series resistance of 14 Ω at 150°C reducing to 8 Ω at 500°C. To our knowledge, this is the lowest series resistance reported so far for a diamond Schottky diode enabling extremely high current densities of 10³ A/cm and a current rectification ratio at ±2 V of 10⁵ making these diodes already attractive as high temperature rectifiers     

Metamorphic InAlAs/InGaAs enhancement mode HEMTs on GaAs substrates

In_0.5Al_0.5As/In_0.5Ga_0.5 As HEMTs have been grown metamorphically on GaAs substrates oriented 6° off (100) toward (111)A using a graded InAlAs buffer. The devices are enhancement mode and show good dc and RF performance. The 0.6-μm gate length devices have saturation currents of 262 mA/mm at a gate bias of 0.7 V and a peak transconductance of 647 mS/mm. The 0.6 μm×3 mm devices tested on-wafer have output powers up to 30 mW/mm and 46% power-added-efficiency (PAE) at 1 V drain bias and 850 MHz. When biased and matched for best efficiency performance, this same device has up to 68% PAE at V_d=1 V     

Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.     

High-speed performance of Si/Si1-xGexheterojunction bipolar transistors

A theoretical investigation of Si/Si_1-xGe_x heterojunction bipolar transistors (HBTs) undertaken in an attempt to determine their speed potential is discussed. The analysis is based on a compact transistor model, and devices with self-aligned geometry, including both extrinsic and intrinsic parameters, are considered. For an emitter area of 1×5 μm², an f_t of over 75 GHz and f_max of over 35 GHz were computed at a collector current density of 1×10 ⁵ A/cm² and V_CB of 5 V     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

Threshold voltage uniformity and characterization of microwaveperformance for GaAs/AlGaAs high electron-mobility transistors grown onSi substrates

We report on DC and microwave characteristics for high electron-mobility transistors (HEMT's) grown on Si substrates by metal-organic chemical vapor deposition (MOCVD). Threshold voltage (V _th) distribution in a 3-in wafer shows standard deviation of V_th (σV_th) of 36 mV with V_th of -2.41 V for depletion mode HEMT's/Si and σV_th of 31 mV with V_th of 0.01 V for enhancement mode, respectively. The evaluation of V_th in a 1.95×1.9 mm² area shows high uniformity for as-grown HEMT's/Si with σV_th of 9 mV for V_th of -0.10 V, which is comparable to that for HEMT's/GaAs. Comparing the V_th distribution pattern in the area with that for annealed HEMT's/Si, it is indicated that the high uniformity of V_th is obtained irrelevant of a number of the dislocations existing in the GaAs/Si. From microwave characteristic evaluation for HEMT's with a middle-(10~50 Ω·cm) and a high-(2000~6000 Ω·cm) resistivity Si substrate using a new equivalent circuit model, it is demonstrated that HEMT's/Si have the disadvantage for parasitic capacitances and resistances originated not from the substrate resistivity but from a conductive layer at the Si-GaAs interface. The parasitic parameters, especially the capacitances, can be overcome by the reduction of electrode areas for bonding pads and by the insertion of a dielectric layer under the electrode, which bring high cut-off frequency (f_T) and maximum frequency of operation (f_max) of 24 GHz for a gate length of 0.8 (μm). These results indicate that HEMT's/Si are sufficiently applicable for IC's and discrete devices and have a potential to be substituted for HEMT's/GaAs