Toward Robust Speech Recognition and Understanding

The principal cause of speech recognition errors is a mismatch between trained acoustic/language models and input speech due to the limited amount of training data in comparison with the vast variation of speech. It is crucial to establish methods that are robust against voice variation due to individuality, the physical and psychological condition of the speaker, telephone sets, microphones, network characteristics, additive background noise, speaking styles, and other aspects. This paper overviews robust architecture and modeling techniques for speech recognition and understanding. The topics include acoustic and language modeling for spontaneous speech recognition, unsupervised adaptation of acoustic and language models, robust architecture for spoken dialogue systems, multi-modal speech recognition, and speech summarization. This paper also discusses the most important research problems to be solved in order to achieve ultimate robust speech recognition and understanding systems. Dr. Sadaoki Furui is currently a Professor at Tokyo Institute of Technology, Department of Computer Science. He is engaged in a wide range of research on speech analysis, speech recognition, speaker recognition, speech synthesis, and multimodal human-computer interaction and has authored or coauthored over 450 published articles. From 1978 to 1979, he served on the staff of the Acoustics Research Department of Bell Laboratories, Murray Hill, New Jersey, as a visiting researcher working on speaker verification. He is a Fellow of the IEEE, the Acoustical Society of America and the Institute of Electronics, Information and Communication Engineers of Japan (IEICE). He was President of the Acoustical Society of Japan (ASJ) from 2001 to 2003 and the Permanent Council for International Conferences on Spoken Language Processing (PC-ICSLP) from 2000 to 2004. He is currently President of the International Speech Communication Association (ISCA). He was a Board of Governor of the IEEE Signal Processing Society from 2001 to 2003. He has served on the IEEE Technical Committees on Speech and MMSP and on numerous IEEE conference organizing committees. He has served as Editor-in-Chief of both Journal of Speech Communication and the Transaction of the IEICE. He is an Editorial Board member of Speech Communication, the Journal of Computer Speech and Language, and the Journal of Digital Signal Processing. He has received the Yonezawa Prize and the Paper Awards from the IEICE (1975, 88, 93, 2003), and the Sato Paper Award from the ASJ (1985, 87). He has received the Senior Award from the IEEE ASSP Society (1989) and the Achievement Award from the Minister of Science and Technology, Japan (1989). He has received the Technical Achievement Award and the Book Award from the IEICE (2003, 1990). He has also received the Mira Paul Memorial Award from the AFECT, India (2001). In 1993 he served as an IEEE SPS Distinguished Lecturer. He is the author of “Digital Speech Processing, Synthesis, and Recognition” (Marcel Dekker, 1989, revised, 2000) in English, “Digital Speech Processing” (Tokai University Press, 1985) in Japanese, “Acoustics and Speech Processing” (Kindai-Kagaku-Sha, 1992) in Japanese, and “Speech Information Processing” (Morikita, 1998) in Japanese. He edited “Advances in Speech Signal Processing” (Marcel Dekker, 1992) jointly with Dr. M.M. Sondhi. He has translated into Japanese “Fundamentals of Speech Recognition,” authored by Drs. L.R. Rabiner and B.-H. Juang (NTT Advanced Technology, 1995) and “Vector Quantization and Signal Compression,” authored by Drs. A. Gersho and R. M. Gray (Corona-sha, 1998).     

Blind Stochastic Feature Transformation for Channel Robust Speaker Verification

To improve the reliability of telephone-based speaker verification systems, channel compensation is indispensable. However, it is also important to ensure that the channel compensation algorithms in these systems surpress channel variations and enhance interspeaker distinction. This paper addresses this problem by a blind feature-based transformation approach in which the transformation parameters are determined online without any a priori knowledge of channel characteristics. Specifically, a composite statistical model formed by the fusion of a speaker model and a background model is used to represent the characteristics of enrollment speech. Based on the difference between the claimant's speech and the composite model, a stochastic matching type of approach is proposed to transform the claimant's speech to a region close to the enrollment speech. Therefore, the algorithm can estimate the transformation online without the necessity of detecting the handset types. Experimental results based on the 2001 NIST evaluation set show that the proposed transformation approach achieves significant improvement in both equal error rate and minimum detection cost as compared to cepstral mean subtraction and Znorm. Kwok-Kwong Yiu received a BEng (Hons) degree in 1992 and an MPhil degree in 2000 from the Department of Electronic and Information Engineering, The Hong Kong Polytechnic University. He was a Research Associate at the same institute from 2000 to 2001. He is currently a PhD student and his supervisor is Dr. M.W. Mak. His research interests include speaker verification, neural networks, and channel compensation. Man-Wai Makreceived a BEng (Hons) degree in Electronic Engineering from Newcastle Upon Tyne Polytechnic in 1989 and a PhD degree in Electronic Engineering from the University of Northumbria at Newcastle in 1993. He was a Research Assistant at the University of Northmubria at Newcastle, from 1990 to 1993. He joined the Department of Electronic Engineering at the Hong Kong Polytechnic University as a Lecturer in 1993 and as an Assistant Professor in 1995. Since 1995, Dr. Mak has been an executive committee member of the IEEE Hong Kong Section Computer Chapter. He is currently the chairman of the IEEE Hong Kong Section Computer Chapter. Dr. Mak's research interests include speaker recognition and neural networks. Ming-Cheung Cheung received a BSc (Hons) degree in Information Technology from The Hong Kong Polytechnic University in 2002. Since November 2002, he has been an MPhil student at the Department of Electronic and Information Engineering of The Hong Kong Polytechnic University. His research interests include pattern recognition, neural networks, and fusion techniques for multimodal biometric authentication. Sun-Yuan Kung received his Ph.D. Degree in Electrical Engineering from Stanford University. In 1974, he was an Associate Engineer of Amdahl Corporation, Sunnyvale, CA. From 1977 to 1987, he was a Professor of Electrical Engineering-Systems, the University of Southern California. Since 1987, he has been a Professor of Electrical Engineering, Princeton University. Since 1990, he has served as an Editor-In-Chief of Journal of VLSI Signal Processing Systems. He served as a founding member and General Chairman of various international conferences, including IEEE Workshops on VLSI Signal Processing in 1982 and 1986 (L.A.), International Conference on Application Specific Array Processors in 1990 (Princeton) and 1991 (Barcelona), and IEEE Workshops on Neural Networks and Signal Processing in 1991 (Princeton), 1992 (Copenhagen) and 1998 (Cambridge, UK), the First IEEE Workshops on Multimedia Signal Processing in 1997 (Princeton), and International Computer Symposium in 1998 (Tainan).Dr. Kung is a Fellow of IEEE. He was the recipient of 1992 IEEE Signal Processing Society's Technical Achievement Award for his contributions on “parallel processing and neural network algorithms for signal processing”. He was appointed as an IEEE-SP Distinguished Lecturer in 1994. He received 1996 IEEE Signal Processing Society's Best Paper Award. He was a recipient of the IEEE Third Millennium Medal in 2000. He has authored more than 300 technical publications, including three books “VLSI Array Processors”, (Prentice Hall, 1988) (with Russian and Chinese translations), “Digital Neural Networks”, Prentice Hall, 1993, and “Principal Component Neural Networks”, John Wiley, 1996.     

Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters

There are many applications in which particle filters outperform traditional signal processing algorithms. Some of these applications include tracking, joint detection and estimation in wireless communication, and computer vision. However, particle filters are not used in practice for these applications mainly because they cannot satisfy real-time requirements. This paper presents an efficient resampling architecture for parallel particle filtering. The proposed architecture is flexible such that it supports various modes of parallel resampling operations with up to four processing elements. The resampling algorithm is developed in order to compensate for possible error caused by finite precision quantization in the resampling step. Communication between the processing elements after resampling is identified as an implementation bottleneck, and therefore, concurrent buffering is incorporated in order to speed up communication of particles among processing elements. The flexible resampling mechanism is implemented in 0.35 μ m CMOS process and its complexity and performance are analyzed. Sangjin Hong received the B.S and M.S degrees in EECS from the University of California, Berkeley. He received his Ph.D in EECS from the University of Michigan, Ann Arbor. He is currently with the department of Electrical and Computer Engineering at State University of New York, Stony Brook. Before joining SUNY, he has worked at Ford Aerospace Corp. Computer Systems Division as a systems engineer. He also worked at Samsung Electronics in Korea as a technical consultant. His current research interests are in the areas of low power VLSI design of multimedia wireless communications and digital signal processing systems, reconfigurable SoC design and optimization, VLSI signal processing, and low-complexity digital circuits. Prof. Hong served on numerous Technical Program Committees for IEEE conferences. Prof. Hong is a Senior Member of IEEE. Shu-Shin Chin was born in Kaohsiung, Taiwan, ROC, in 1974. He received his M.S. and Ph.D degrees in electrical and computer engineering from Stony Brook University – State University of New York in 1999 and 2004, respectively. His research interests include low-power digital circuits, and coarse-grained reconfigurable architectures for high-performance DSP systems. Miodrag Bolić received the B.S. and M.S. degrees in electrical engineering from the University of Belgrade, Yugoslavia, in 1996 and 2001, respectively, and his Ph.D. degree in electrical engineering from Stony Brook University, NY, USA. He is currently with the School of Information Technology and Engineering at the University of Ottawa, Canada. From 1996 to 2000 he was Research Associate with the Institute of Nuclear Science Vinĉa, Yugoslavia. From 2001 to 2004 he worked part-time at Symbol Technologies Inc., NY, USA. His research is related to VLSI architectures for digital signal processing and signal processing in wireless communications and tracking. Petar M. Djurić received his B.S. and M.S. degrees in electrical engineering from the University of Belgrade, in 1981 and 1986, respectively, and his Ph.D. degree in electrical engineering from the University of Rhode Island, in 1990. From 1981 to 1986 he was Research Associate with the Institute of Nuclear Sciences, Vinĉa, Belgrade. Since 1990 he has been with Stony Brook University, where he is Professor in the Department of Electrical and Computer Engineering. He works in the area of statistical signal processing, and his primary interests are in the theory of modeling, detection, estimation, and time series analysis and its application to a wide variety of disciplines including wireless communications and bio-medicine. Prof. Djurić has served on numerous Technical Committees for the IEEE and SPIE and has been invited to lecture at universities in the US and overseas. He is the Area Editor of Special Issues of the Signal Processing Magazine, the Treasurer of the IEEE Signal Processing Conference Board, and Associate Editor of the IEEE Transactions on Signal Processing. He is also the Chair elect of the IEEE Signal Processing Society Committee on Signal Processing—Theory and Methods, and an Editorial Board member of Digital Signal Processing, the EURASIP Journal on Applied Signal Processing and the EURASIP Journal on Wireless Communications and Networking. Prof. Djurić is a Member of the American Statistical Association and the International Society for Bayesian Analysis.     

Cross-layer modeling of adaptive wireless links for QoS support in heterogeneous wired-wireless networks

Future wired-wireless multimedia networks require diverse quality-of-service (QoS) support. To this end, it is essential to rely on QoS metrics pertinent to wireless links. In this paper, we develop a cross-layer model for adaptive wireless links, which enables derivation of the desired QoS metrics analytically from the typical wireless parameters across the hardware-radio layer, the physical layer and the data link layer. We illustrate the advantages of our model: generality, simplicity, scalability and backward compatibility. Finally, we outline its applications to power control, TCP, UDP and bandwidth scheduling in wireless networks. The work by Q. Liu and G. B. Giannakis are prepared through collaborative participation in the Communications and Networks Consortium sponsored by the U.S. Army Research Laboratory under the Collaborative Technology Alliance Program, Cooperative Agreement DAAD19-01-2-0011. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon. The work by S. Zhou is supported by UConn Research Foundation internal grant 445157. Qingwen Liu (S’04) received the B.S. degree in electrical engineering and information science in 2001, from the University of Science and Technology of China (USTC). He received the M.S. degree in electrical engineering in 2003, from the University of Minnesota (UMN). He currently pursues his Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Minnesota (UMN). His research interests lie in the areas of communications, signal processing, and networking, with emphasis on cross-layer analysis and design, quality of service support for multimedia applications over wired-wireless networks, and resource allocation. Shengli Zhou (M’03) received the B.S. degree in 1995 and the M.Sc. degree in 1998, from the University of Science and Technology of China (USTC), both in electrical engineering and information science. He received his Ph.D. degree in electrical engineering from the University of Minnesota, 2002, and joined the Department of Electrical and Computer Engineering at the University of Connecticut, 2003. His research interests lie in the areas of communications and signal processing, including channel estimation and equalization, multi-user and multi-carrier communications, space time coding, adaptive modulation, and cross-layer designs. He serves as an associate editor for IEEE Transactions on Wireless Communications since Feb. 2005. G. B. Giannakis (Fellow’97) received his Diploma in Electrical Engineering from the National Technical University of Athens, Greece, 1981. From September 1982 to July 1986 he was with the University of Southern California (USC), where he received his MSc. in Electrical Engineering, 1983, MSc. in Mathematics, 1986, and Ph.D. in Electrical Engineering, 1986. After lecturing for one year at USC, he joined the University of Virginia in 1987, where he became a professor of Electrical Engineering in 1997. Since 1999 he has been a professor with the Department of Electrical and Computer Engineering at the University of Minnesota, where he now holds an ADC Chair in Wireless Telecommunications. His general interests span the areas of communications and signal processing, estimation and detection theory, time-series analysis, and system identification -- subjects on which he has published more than 200 journal papers, 350 conference papers and two edited books. Current research focuses on transmitter and receiver diversity techniques for single- and multi-user fading communication channels, complex-field and space-time coding, multicarrier, ultra-wide band wireless communication systems, cross-layer designs and sensor networks. G. B. Giannakis is the (co-) recipient of six paper awards from the IEEE Signal Processing (SP) and Communications Societies (1992, 1998, 2000, 2001, 2003, 2004). He also received the SP Society’s Technical Achievement Award in 2000. He served as Editor in Chief for the IEEE SP Letters, as Associate Editor for the IEEE Trans. on Signal Proc. and the IEEE SP Letters, as secretary of the SP Conference Board, as member of the SP Publications Board, as member and vice-chair of the Statistical Signal and Array Processing Technical Committee, as chair of the SP for Communications Technical Committee and as a member of the IEEE Fellows Election Committee. He has also served as a member of the IEEE-SP Society’s Board of Governors, the Editorial Board for the Proceedings of the IEEE and the steering committee of the IEEE Trans. on Wireless Communications.     

CMOS image sensors for sensor networks

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 μm CMOS process. The imagers embed an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low power operation. This characteristics allow the sensor to operate in different lighting conditions and for years on the sensor network node power budget. Eugenio Culurciello (S’97–M’99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from Johns Hopkins University, Baltimore, MD. In July 2004 he joined the department of Electrical Engineering at Yale University, where he is currently an assistant professor. He founded and instrumented the E-Lab laboratory in 2004. His research interest is in analog and mixed-mode integrated circuits for biomedical applications, sensors and networks, biological sensors, Silicon on Insulator design and bio-inspired systems. Andreas G. Andreou received his Ph.D. in electrical engineering and computer science in 1986 from Johns Hopkins University. Between 1986 and 1989 he held post-doctoral fellow and associate research scientist positions in the Electrical and Computer engineering department while also a member of the professional staff at the Johns Hopkins Applied Physics Laboratory. Andreou became an assistant professor of Electrical and Computer engineering in 1989, associate professor in 1993 and professor in 1996. He is also a professor of Computer Science and of the Whitaker Biomedical Engineering Institute and director of the Institute’s Fabrication and Lithography Facility in Clark Hall. He is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Between 2001 and 2003 he was the founding director of the ABET accredited undergraduate Computer Engineering program. In 1996 and 1997 he was a visiting professor of the computation and neural systems program at the California Institute of Technology. In 1989 and 1991 he was awarded the R.W. Hart Prize for his work on mixed analog/digital integrated circuits for space applications. He is the recipient of the 1995 and 1997 Myril B. Reed Best Paper Award and the 2000 IEEE Circuits and Systems Society, Darlington Best Paper Award. During the summer of 2001 he was a visiting professor in the department of systems engineering and machine intelligence at Tohoku University. In 2006, Prof. Andreou was elected as an IEEE Fellow and a distinguished lecturer of the IEEE EDS society. Andreou’s research interests include sensors, micropower electronics, heterogeneous microsystems, and information processing in biological systems. He is a co-editor of the IEEE Press book: Low-Voltage/Low-Power Integrated Circuits and Systems, 1998 (translated in Japanese) and the Kluwer Academic Publishers book: Adaptive Resonance Theory Microchips, 1998. He is an associate editor of IEEE Transactions on Circuits and Systems I.     

Interactive Content-aware Video Streaming System with Fine Granularity Scalability

Video streaming with varying transmission bandwidth is becoming increasingly important. In this paper, an interactive video streaming system is proposed. Fine Granularity Scalability (FGS) is applied to be the streaming video format. The computational complexity of FGS coding is analyzed to explore an efficient FGS implementation. A new transmission model is proposed for the realization of a content-aware video streaming. At encoder side, the current MPEG-4 FGS coding flow is reordered such that the picture-level maximum can be acquired in advance and bit-plane data can be dynamically adapted. With these proposed hardware-oriented optimization approaches, a hardwired FGS block-level processing core is proposed to achieve a cost-effective solution to FGS implementation. The streaming server can adaptively decide quality-enhanced region by selective enhancement according to both object information from encoding side and user-defined region from receiver side. From the simulation results, it’s demonstrated that the proposed approach can provide better quality in users’ interest regions with no bit-rate or complexity overhead. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S., M.S., and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998, 2000, and 2005, respectively. He serves as senior engineer in SoC Solutions Dept., Vivotek Inc. now. His research interests include video coding algorithms and VLSI architectures for image/video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia coding standard and digital consumer devices. His research interests include video coding, video processing and VLSI design. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics and Optoelectronics Research Laboratories in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Models for Architectural Power and Power Grid Noise Analysis on Data Bus

The transition activity on a data bus is a time series that determines power consumption on this data bus. The average values of power consumption and power grid voltage drop are proportional to average value of transition activity, i.e., transition probability. The fluctuation of power grid voltage drop appears as noise on power grid and its strength is determined by the second order statistics of transition activity, i.e., variance, auto-correlation function or power spectrum. In this paper, for the first time, simple accurate models for estimating variance and power spectrum of transition activity are proposed. The proposed models are based on linearly modeling spatial-time correlation of bit-level transition activity and result in low computational complexity but very good estimation accuracy. In addition, the dual bit type (DBT) [1, 2] model for estimating average transition activity was further developed. The previous DBT model was made complete with the equation derived in this paper for computing transition probability beyond breakpoint BP ₁. Besides DSP computational architecture and algorithm designs, the proposed simple models are of great significance for power grid noise decoupling and chip floor-planning. Lijun Gao (S’99–M’01) received B.E. and M.E. degrees in Communication & Electronic Systems from Tsinghua University, Beijing, China, in 1986 and 1988, respectively. He received his PhD degree in Elecrical & Computer Engineering from University of Minnesota, Minneapolis, USA, in 2001. He is also an MS degree candidate in Computer & Information Science at University of Minnesota, Minneapolis. Dr. Gao is currently with Medtronic Inc., Minneapolis, MN, and working on DSP design for pacemaker. From 2001 to 2003, he was with Bermai Inc., Minnetonka, MN and working on the design of wireless LAN (802.11a/11b) chipsets. In 2001, he worked in the R & D division of GlobeSpan Semiconductor Inc., Red Bank, NJ. From 1988 to 1991, he was a faculty member with Tsinghua University, Beijing, China. From 1991 to 1996, he was a R & D engineer with the Institute of Software, Chinese Academy of Science, Beijing, China. For the period of 1991 to 1993, he was a visiting R & D engineer at Onflo Computer Co. Hong Kong. Dr. Gao received the Science & Technology awards from the National Education Council, China, in 1994 for his contribution to radar signal processing while he was at Tsinghua University, and from the ministry of Electronic Industry, China, in 1995 for his contribution to the CJK Ideograph Unification in ISO 10646 (Unicode). His current reserach interest includes the algorithm/architecture/ circuit for VLSI design, the computational aspects of digital signal processing (DSP) and programmable DSP processor. Specifically, his focus is on the deep-submicron VLSI design, power estimation/low power design, computer arithmetic, finite field arithmetic, error control coding, cryptography, adaptive filters, equalization, beamformer, special-purpose processors and FPGA/reconfigurable computing. Keshab K. Parhi (S’85-M’88–SM’91-F’96) Keshab K. Parhi received his B.Tech., MSEE, and Ph.D. degrees from the Indian Institute of Technology, Kharagpur, the University of Pennsylvania, Philadelphia, and the University of California at Berkeley, in 1982, 1984, and 1988, respectively. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor in the Department of Electrical and Computer Engineering. His research addresses VLSI architecture design and implementation of physical layer aspects of broadband communications systems. He is currently working on error control coders and cryptography architectures, high-speed transceivers, ultra wideband systems, quantum error control coders and quantum cryptography. He has published over 350 papers, has authored the text book VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999). Dr. Parhi is the recipient of numerous awards including the 2004 F.E. Terman award by the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W.R.G. Baker prize paper award, and a Golden Jubilee award from the IEEE Circuits and Systems Society in 1999. He has served on the editorial boards of the IEEE TRANSACTIONS ON CAS, CAS-II, VLSI Systems, Signal Processing, Signal Processing Letters, and currently serves on editorial board of the IEEE Signal Processing Magazine, and is the curent Editor-in-Chief of the IEEE Trans. on Circuits and Systems–I (2004–2005 term). He has served as technical program cochair of the 1995 IEEE VLSI Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996–1998. He currently serves on the Board of Governors of the IEEE Circuits and Systems Society. He was elected a Fellow of IEEE in 1996.     

Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper

There were several modulation and coding proposals for 10GBASE-T (10 Gigabit Ethernet over copper) systems. One of these is based on a 10-level pulse amplitude modulation (PAM-10) combined with a 4D (four-dimensional) 8-state trellis code similar to the one in 1000BASE-T (1000 Megabit Ethernet over copper). The trellis code can be used in a conventional manner as in 1000BASE-T, but the corresponding decoder with a long critical path needs to operate at 833 MHz. It is difficult to meet the critical path requirements of such a decoder. To solve the problem, two interleaved trellis coded modulation schemes are proposed in this paper. The inherent decoding speed requirements can be relaxed by factors of 4 and 2, respectively. Due to intersymbol interference (ISI), the branch metric units in the decoders corresponding to the two interleaved modulation schemes are much more complicated than those in the conventional decoder. Thus this paper also considers the problem of complexity reduction of the decoders for the two proposed interleaved modulation schemes, and presents two novel complexity reduction schemes. Simulation results show that the error-rate performances of the two proposed interleaved schemes are quite close to that of the conventional scheme. It is also shown that the performance loss due to complexity reduction is negligible. This research was supported in part by the National Science Foundation by the grant number CCF-0429979. Yongru Gu received M.S. degree from Duke University, Durham, NC in 2001. Currently, he is working toward the Ph.D. degree at the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis. His research interests lie in high-speed low-power VLSI implementation of digital signal precessing and communication systems. Keshab K. Parhi (S'85-M'88-SM'91-F'96) received his B.Tech., MSEE, and Ph.D. degrees from the Indian Institute of Technology, Kharagpur, the University of Pennsylvania, Philadelphia, and the University of California at Berkeley, in 1982, 1984, and 1988, respectively. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor in the Department of Electrical and Computer Engineering. His research addresses VLSI architecture design and implementation of physical layer aspects of broadband communications systems. He is currently working on error control coders and cryptography architectures, high-speed transceivers, and ultra wideband systems. He has published over 400 papers, has authored the text book VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999). Dr. Parhi is the recipient of numerous awards including the 2004 F.E. Terman award by the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W.R.G. Baker prize paper award, and a Golden Jubilee award from the IEEE Circuits and Systems Society in 1999. He has served on the editorial boards of the IEEE TRANSACTIONS ON CAS, CAS-II, VLSI Systems, Signal Processing, Signal Processing Letters, and Signal Processing Magazine, and currently serves as the Editor-in-Chief of the IEEE Trans. on Circuits and Systems - I (2004–2005 term), and serves on the Editorial Board of the Journal of VLSI Signal Processing. He has served as technical program cochair of the 1995 IEEE VLSI Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996–1998.     

Implementation of a Wireless Multimedia DSP Chip for Mobile Applications

This paper presents the implementation of a wireless multimedia DSP chip for mobile applications. The implemented DSP chip supports communication instructions for Viterbi, timing synchronization, etc. as well as multimedia instructions. The DSP can handle variable length data and perform four MACs in a cycle. The proposed DSP employs parallel processing techniques, such as SIMD, vector processing, DSP schemes and adopts low power features for wireless applications. The implemented DSP chip includes test circuits and various peripherals, such as DMA, bus arbitration, timer, etc. This chip has been modeled by Verilog HDL and implemented using the 0.35 m HCB60 library. The total gate count excluding memory is about 170,000 gates and the clock frequency is 100 MHz.Junghoo Lee received the B.S. degree in electronic engineering from Ajou University, Suwon, Korea in 2002. He is currently working toward the Ph.D. degree with School of Electrical and Computer Engineering, Ajou University. His main research interests include SOC design and application-specific DSP chip design.Myung H. Sunwoo received the B.S. degree in electronic engineering from the Sogang University in 1980, the M.S. degree in electrical and electronics from the Korea Advanced Institute of Science and Technology in 1982, and the Ph.D. degree in electrical and computer engineering from the University of Texas at Austin in 1990.He worked for Electronics and Telecommunications Research Institute (ETRI) in Daejeon, Korea from 1982 to 1985 and Digital Signal Processor Operations, Motorola, Austin, TX from 1990 to 1992. Since 1992, he has been a Professor with the School of Electrical and Computer Engineering, Ajou University in Suwon, Korea. In 2000, he was a Visiting Professor in the Department of Electrical and Computer Engineering, the University of California, Davis, CA. He is the Director of the National Research Laboratory sponsored by the Ministry of Science and Technology. His research interests include VLSI architectures, SOC design for multimedia and communications, and application-specific DSP architectures.Dr. Sunwoo has published more than 120 papers in international transactions/journals and conferences and also has 28 patents including five U.S. patents. He served as a Technical Program Chair of the IEEE Workshop on Signal Processing Systems (SIPS) in 2003 and a member of the technical program committee of various international conferences. He has received a number of research awards from the Ministry of Commerce, Industry and Energy, Samsung Electronics, and professional foundations. He served as an Associate Editor for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2002–2003) and as a Guest Editor for the Journal of VLSI Signal Processing (Kluwer, 2004). Currently, He is a Senior Member of IEEE and a Chair of the IEEE CAS Society of the Seoul Chapter.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

Auction-Based Spectrum Sharing

We study auction mechanisms for sharing spectrum among a group of users, subject to a constraint on the interference temperature at a measurement point. The users access the channel using spread spectrum signaling and so interfere with each other. Each user receives a utility that is a function of the received signal-to-interference plus noise ratio. We propose two auction mechanisms for allocating the received power. The first is an auction in which users are charged for received SINR, which, when combined with logarithmic utilities, leads to a weighted max-min fair SINR allocation. The second is an auction in which users are charged for power, which maximizes the total utility when the bandwidth is large enough and the receivers are co-located. Both auction mechanisms are shown to be socially optimal for a limiting “large system” with co-located receivers, where bandwidth, power and the number of users are increased in fixed proportion. We also formulate an iterative and distributed bid updating algorithm, and specify conditions under which this algorithm converges globally to the Nash equilibrium of the auction. This work was supported by the Northwestern-Motorola Center for Communications and by NSF CAREER award CCR-0238382. This paper was presented in part at the 2nd Workshop on Modeling and Optimization in Mobile, Ad Hoc, and Wireless Networks (WiOpt’04), Cambridge, UK, March 24–26, 2004, and the 42nd Annual Allerton Conference on Communication, Control and Computing, Monticello, IL, USA, September 29 - October 1, 2004. Jianwei Huang received the B.E. degree in Radio Engineering from Southeast University, Nanjing, China in 2000, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Northwestern University, Evanston, IL in 2003 and 2005, respectively. He is currently a Postdoc Research Association in the Department of Electrical Engineering, Prinston university, NJ. In 2004 and 2005, he also worked in the Mathematics of Communication Networks Group at Motorola, Arlington Heights, IL USA as a software engineer. His current research interests lie in the areas of wireless and wireline communications networks, with emphases on resource allocation, network pricing, dynamic spectrum sharing, mobile ad hoc and sensor networks, stochastics and non-convex optimizations. Dr. Huang is the receipt of a 2001 Walter P. Murphy Fellowship at Northwestern University, and a 1999 Chinese National Excellent Student Award. Randall A. Berry received the B.S. degree in Electrical Engineering from the University of Missouri-Rolla in 1993 and the M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 1996 and 2000 respectively. He is currently an assistant professor in the Department of Electrical Engineering and Computer Science at Northwestern University. In 1998 he was on the technical staff at MIT Lincoln Laboratory in the Advanced Networks Group. His primary research interests include wireless communication, data networks, and information theory. He is the recipient of a 2003 NSF CAREER award. Michael L. Honig received the B.S. degree in electrical engineering from Stanford University in 1977, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1978 and 1981, respectively. He subsequently joined Bell Laboratories in Holmdel, NJ, where he worked on local area networks and voiceband data transmission. In 1983 he joined the Systems Principles Research Division at Bellcore, where he worked on Digital Subscriber Lines and wireless communications. Since the Fall of 1994, he has been with Northwestern University where he is a Professor in the Electrical Engineering and Computer Science Department. He has held visiting scholar positions at the Naval Research Laboratory (San Diego), the University of California, Berkeley, the University of Sydney, and Princeton University. He has also worked as a free-lance trombonist. Dr. Honig has served as an editor for the IEEE Transactions on Information Theory (1998-2000) and the IEEE Transactions on Communications (1990-1995), and was a guest editor for the European Transactions on Telecommunications and Wireless Personal Communications. He has also served as a member of the Digital Signal Processing Technical Committee for the IEEE Signal Processing Society, and as a member of the Board of Governors for the Information Theory Society (1997-2002). He is the co-recipient of the 2002 IEEE Communications Society and Information Theory Society Joint Paper Award, and is a Fellow of IEEE.     

Platform-Based MPEG-4 SOC Design for Video Communications

An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented for compromise between compression performance and design cost. The proposed data reuse scheme reduces required memory access bandwidth. For texture coding path, an interleaving DCT/IDCT scheduling with substructure sharing technique is proposed. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352×288) frames per second. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981-1986), and an Associate Professor (1986-1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT & T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001--2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

A Low-Power Multithreaded Processor for Software Defined Radio

Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications. Michael Schulte received a B.S. degree in Electrical Engineering from the University of Wisconsin-Madison in 1991, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Texas at Austin in 1992 and 1996, respectively. From 1996 to 2002, he was an assistant and associate professor at Lehigh University, where he directed the Computer Architecture and Arithmetic Research Laboratory. He is currently an assistant professor at the University of Wisconsin-Madison, where he leads the Madison Embedded Systems and Architectures Group. His research interests include high-performance embedded processors, computer architecture, domain-specific systems, computer arithmetic, and wireless systems. He is a senior member of the IEEE and the IEEE Computer Society, and an associate editor for the IEEE Transactions on Computers and the Journal of VLSI Signal Processing. John Glossner is CTO & Executive Vice President at Sandbridge Technologies. Prior to co-founding Sandbridge, John managed the Advanced DSP Technology group, Broadband Transmission Systems group, and was Access Aggregation Business Development manager at IBM’s T.J. Watson Research Center. Prior to IBM, John managed the software effort in Lucent/Motorola’s Starcore DSP design center. John received a Ph.D. in Computer Architecture from TU Delft in the Netherlands for his work on a Multithreaded Java processor with DSP capability. He also received an M.S. degree in Engineering Management and an M.S.E.E. from NTU. John also holds a B.S.E.E. degree from Penn State. John has more than 60 publications and 12 issued patents. Dr. Sanjay Jinturkar is the Director of Software at Sandbridge and manages the systems software and communications software groups. Previously, he managed the software tools group at StarCore. He has a Ph.D in Computer Science from University of Virginia and holds 20 publications and 4 patents. Mayan Moudgill obtained a Ph.D. in Computer Science from Cornell University in 1994, after which he joined IBM at the Thomas J. Watson Research Center. He worked on a variety of computer architecture and compiler related projects, including the VLIW research compiler, Linux ports for the 40x series embedded processors and simulators for the Power 4. In 2001, he co-founded Sandbridge Technologies, a start-up that is developing digital signal processors targeted at 3G wireless phones. Suman Mamidi is a graduate student in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. He received his M.S. degree from the University of Wisconsin-Madison in December, 2003 and is currently working towards his PhD. His research interests include low-power processors, hardware accelerators, multithreaded processors, reconfigurable hardware, and embedded systems. Stamatis Vassiliadis was born in Manolates, Samos, Greece, in 1951. He is currently a Chair Professor in the Electrical Engineering, Mathematics, and Computer Science (EEMCS) department of Delft University of Technology (TU Delft), The Netherlands. He previously served in the Electrical and Computer Engineering faculties of Cornell University, Ithaca, NY and the State University of New York (S.U.N.Y.), Binghamton, NY. For a decade, he worked with IBM, where he was involved in a number of advanced research and development projects. He received numerous awards for his work, including 24 publication awards, 15 invention awards, and an outstanding innovation award for engineering/scientific hardware design. His 73 USA patents rank him as the top all time IBM inventor. Dr. Vassiliadis is an ACM fellow, an IEEE fellow and a member of the Royal Netherlands Academy of Arts and Sciences (KNAW).     

Implementation of a Multi-band Pulsed-OFDM Transceiver

A multi-band orthogonal frequency division multiplexing (OFDM) ultra wideband (UWB) system is being considered for the IEEE 802.15.3a wireless personal area networks. An enhancement to this system, named pulsed-OFDM, has been proposed to reduce the complexity and power consumption of the transceiver without sacrificing performance. In this paper, we describe a detailed implementation of a pulsed-OFDM transceiver. The main focus of the paper is designing each section with maximum power saving and minimum complexity. Specially we design each section such that each part of the pulsed-OFDM transceiver has less or equal complexity and power consumption than the corresponding part in the original multi-band OFDM transceiver. Different options to implement encoder and decoder as well as modulator and demodulator (Inverse Fast Fourier Transform and Fast Fourier Transform) are examined. We also present the simulation results to choose appropriate resolution for analog-to-digital and digital-to-analog converters (ADC and DAC). Finally we investigate the effect of fixed point arithmetic in calculating FFTs and required resolution using simulation results. Ebrahim Saberinia received his BS and MS degrees both in Electrical Engineering from Sharif University of Technology, Tehran, Iran in 1996 and 1998 respectively, and PhD degree in Electrical and Computer Engineering from the University of Minnesota, Minneapolis in 2004. Currently he is an assistant professor at the Department of Electrical and Computer Engineering, University of Nevada, Las Vegas. His research interests includes: wireless communications, signal processing and wireless networks. His current research activities include ultra wideband communications and wireless personal area networks. Kai-Chuan Chang received his BS degrees in Electrical Engineering and Mathematics with Summa Cum Laude in 2000 from University of Minnesota, Minneapolis. He is the recipient of the University of Minnesota graduate school fellowship in 2000. He obtained his MS in Electrical Engineering in 2002 from University of Minnesota. He is currently working on his PhD degree in the area of VLSI implementation of UWB OFDM systems at University of Minnesota, Minneapolis. Gerald E. Sobelman received a B.S. in physics, summa cum laude, from the University of California, Los Angeles in 1974. He was awarded M.A. and Ph.D. degrees in physics from Harvard University in 1976 and 1979, respectively. He has held positions at The Rockefeller University, Sperry Corporation and Control Data Corporations. Since 1986, he has been a faculty member at the University of Minnesota. His current research interests are in the areas of VLSI and SoC design for applications in communications, signal processing, coding and cryptography. He has published more than 60 research papers, is a co-author of one book and holds 10 U.S. patents. He has been a member of the program committees for IEEE ISCAS and SOCC and has served as an Associate Editor for IEEE Signal Processing Letters. Ahmed H. Tewfik (Fellow IEEE) received his B.Sc. degree from Cairo University, Cairo Egypt, in 1982 and his M.Sc., E.E. and Sc.D. degrees from the Massachusetts Institute of Technology, Cambridge, MA, in 1984, 1985 and 1987 respectively. Dr. Tewfik has worked at Alphatech, Inc., Burlington, MA in 1987. He is the E. F. Johnson professor of Electronic Communications with the department of Electrical Engineering at the University of Minnesota. He served as a consultant to MTS Systems, Inc., Eden Prairie, MN, Emerson-Rosemount, Inc., Eden Prairie, MN, CyberNova, Milipitas, CA, Macrovision, Santa Clara, CA, Visionaire Technology, Fremont, CA and Ipsos, New York. He worked with Texas Instruments and Computing Devices International. From August 1997 to August 2001, he was the President and CEO of Cognicity, Inc., an entertainment marketing software tools publisher that he co-founded, on partial leave of absence from the University of Minnesota. His current research interests are in programmable wireless networks, genomics and proteomics, healthcare safety and datanomic and pervasive computing and storage. Prof. Tewfik is a Fellow of the IEEE. He was a Distinguished Lecturer of the IEEE Signal Processing Society in 1997–1999. He received the IEEE third Millennium award in 2000. He was invited to be a principal lecturer at the 1995 IEEE EMBS summer school. He was awarded the E. F. Johnson professorship of Electronic Communications in 1993, a Taylor faculty development award from the Taylor foundation in 1992 and an NSF research initiation award in 1990. He delivered plenary lectures at several IEEE and non-IEEE meetings, including the 1994 IEEE Int. Conf. on Acoust. Speech and Signal Proc. (ICASSP’94), the 1999 IEEE-EURASIP Workshop on Nonlinear Signal and Image Processing, the 1999 IEEE Turkish Signal Processing Conference (SIU 99), the 1^st IEEE International Symposium on Signal Processing and Information Theory (2001), SSGRR2002w International Conference on Advances in Infrastructure for Electronic Business, Science, and Education on the Internet, the 2003 European Union COST meeting and the 10^th IEEE International Conference on Electronics, Circuits and Systems. He gave invited tutorials on ultrawideband communications at the 2003 Fall IEEE Vehicular Technology Conference, watermarking at the 1998 IEEE International Conference on Image Processing and wavelets at the 1994 IEEE workshop on Time-Frequency and Time-Scale Analysis. He was selected to be the first Editor-in-Chief of the IEEE Signal Processing Letters from 1993 to 1999. He is a past associate editor of the IEEE Trans. on Signal Proc., was a guest editor of three special issue of that journal on wavelets and their applications and watermarking and a guest editor of a special issue of the IEEE Trans. on Multimedia on multimedia databases. He also served as the president of the Minnesota chapters of the IEEE signal processing and communications societies for the past 3 years.     

Designing an Embedded Video Processing Camera Using a 16-bit Microprocessor for a Surveillance System

This paper describes the design and implementation of a hybrid intelligent surveillance system that consists of an embedded system and a personal computer (PC)-based system. The embedded system performs some of the image processing tasks and sends the processed data to the PC. The PC tracks persons and recognizes two-person interactions by using a grayscale side view image sequence captured by a stationary camera. Based on our previous research, we explored the optimum division of tasks between the embedded system and the PC, simulated the embedded system using dataflow models in Ptolemy, and prototyped the embedded system in real-time hardware and software using a 16-bit CISC microprocessor. This embedded system processes one 320 × 240 frame in 89 ms, which yields one-third of the rate of 30 Hz video system. In addition, the real-time embedded system prototype uses 5.7 K bytes of program memory, 854 K bytes of internal data memory and 2 M bytes external DRAM. Koichi Sato is a Ph.D. student in the Department of Electrical and Computer Engineering at The University of Texas at Austin. He earned his B.S. in University of Tokyo, Japan in 1993. He worked for Automotive Development Center in Mitsubishi Electric Corporation where he was involved in lane and automobile recognition in vehicle video processing products such as automatic cruise control and drowsiness detection systems. He enrolled in the current University at 1998 and received an M.S in 2000. In his Master's thesis he worked on human tracking and human interaction recognition. His current work includes velocity extraction using the TSV transform, object tracking, and 3D object reconstruction. Brian L. Evans is a tenured Associate Professor in the Department of Electrical and Computer Engineering at The University of Texas at Austin. His research and teaching efforts are in embedded real-time signal and image processing systems. In signal processing, his research group is focused on the design and real-time software implementation of ADSL and VDSL transceivers, for high-speed Internet access. In image processing, his group is focused on the design and real-time software implementation of high-quality halftoning for desktop printers, smart image acquisition for digital still cameras, and 3-D sonar imaging systems. In signal and image processing, Dr. Evans has published over 100 refereed conference and journal papers. Dr. Evans is the primary architect of the Signals and Systems Pack for Mathematica, which has been on the market since October 1995. He was a key contributor to UC Berkeley's Ptolemy Classic electronic design automation environment for embedded systems, which has been successfully commercialized by Agilent and Cadence. His BSEECS (1987) degree is from the Rose-Hulman Institute of Technology, and his MSEE (1988) and PhDEE (1993) degrees are from the Georgia Institute of Technology. From 1993 to 1996, he was a post-doctoral researcher in the Ptolemy project at UC Berkeley. He is a member of the Design and Implementation of Signal Processing Systems Technical Committee of the IEEE Signal Processing Society, and a Senior Member of the IEEE. He is the recipient of a 1997 National Science Foundation CAREER Award. J.K. Aggarwal has served on the faculty of The University of Texas at Austin College of Engineering since 1964 and is currently Cullen Professor of Electrical and Computer Engineering and Director of the Computer and Vision Research Center. His research interests include computer vision and pattern recognition focusing on human motion. A Fellow of IEEE since 1976 and IAPR since 1998, he received the Senior Research Award of the American Society of Engineering Education in 1992, the 1996 Technical Achievement Award of the IEEE Computer Society and the graduate teaching award at The University of Texas at Austin in 1992. He has served as Chairman of the IEEE Computer Society Technical Committee on Pattern Analysis and Machine Intelligence (1987--1989); Director of the NATO Advanced Research Workshop on Multisensor Fusion for Computer Vision, Grenoble, France (1989); Chairman of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition (1993), and President of the International Association for Pattern Recognition (1992--1994). He is a Life Fellow of IEEE and Golden Core member of IEEE Computer Society. He has authored and edited a number of books, chapters, proceedings of conferences, and papers.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Complex Infomax: Convergence and Approximation of Infomax with Complex Nonlinearities

Independent component analysis (ICA) for separating complex-valued sources is needed for convolutive source-separation in the frequency domain, or for performing source separation on complex-valued data, such as functional magnetic resonance imaging or radar data. Previous complex Infomax approaches that use nonlinear functions in the updates have proposed using bounded (and hence non-analytic) nonlinearities. In this paper, we propose using an analytic (and hence unbounded) complex nonlinearity for Infomax for processing complex-valued sources. We show by simulation examples that using an analytic nonlinearity for processing complex data has a number of advantages. First, when compared to split-complex approaches (i.e., approaches that split the real and imaginary data into separate channels), the shape of the performance surface is improved resulting in better convergence characteristics. We also show that using an analytic complex-valued function for the nonlinearity is more effective in generating the higher order statistics required to establish independence when compared to complex nonlinear functions, i.e., functions that are ℂ → ℂ This work was supported in part by the National Science Foundation Career Award, NSF NCR-9703161 (to TA) and the National Institutes of Health 1 R01 EB 000840-01 (to VC). Vince Calhoun received a bachelor’s degree in Electrical Engineering from the University of Kansas, Lawrence, Kansas, in 1991, master’s degrees in Biomedical Engineering and Information Systems from Johns Hopkins University, Baltimore, in 1993 and 1996, respectively, and the Ph.D. degree in electrical engineering from the University of Maryland Baltimore County, Baltimore, in 2002. He worked as a Senior Research Engineer in Psychiatric Neuro-Imaging at Johns Hopkins from 1993 until 2002. He is currently the Director of the Medical Image Analysis Laboratory and an associate adjunct professor at Yale University. He is associate editor of the IEEE signal processing letters and on the editorial board for the Journal of Human Brain Mapping. Dr. Calhoun is a member of the IEEE, the American Scientific Affiliation, the Organization for Human Brain Mapping, and the International Society for Magnetic Resonance in Medicine. He has organized workshops for human brain mapping (HBM), the society of biological psychiatry (SOBP), and the international conference of independent component analysis and blind source separation (ICA). He is currently serving on the IEEE Machine Learning for Signal Processing (MLSP) Technical Committee and was the general chair for MLSP 2005 in Mystic, CT. He works primarily with magnetic resonance imaging (functional imaging, diffusion tensor imaging, and structural imaging) and electroencephalography (EEG) data and is the author of more than 70 refereed articles in journals and conference proceedings in the areas of image processing, data fusion, adaptive signal processing, neural networks, statistical signal processing, and pattern recognition. Tülay Adalı received the B.S. degree from Middle East Technical University, Ankara, Turkey, in 1987 and the M.S. and Ph.D. degrees from North Carolina State University, Raleigh, in 1988 and 1992 respectively, all in electrical engineering. In 1992, she joined the Department of Electrical Engineering at the University of Maryland Baltimore County, Baltimore, where she currently is a professor. She has worked in the organization of a number of international conference and workshops including the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) and the IEEE International Workshop on Machine Learning for Signal Processing (MLSP). She was the general co-chair for the NNSP workshops 2001-2003. She is the past chair and a current member of the IEEE Machine Learning for Signal Processing Technical Committee and is serving on the IEEE Signal Processing Society conference board. She is an associate editor for the IEEE Transactions on Signal Processing and the Journal of VLSI Signal Processing Systems. She has also guest-edited a number of special issues for the IEEE Transactions on Neural Networks and the VLSI Signal Processing Systems on biomedical, multimedia, and data mining applications of neural networks. She has authored or co-authored more than 175 refereed publications in the areas of statistical signal processing, neural computation, adaptive signal processing, biomedical data analysis, bioinformatics, and communications. Dr. Adalı is the recipient of a 1997 National Science Foundation CAREER Award.     

Localized algorithms for coverage boundary detection in wireless sensor networks

Connected coverage, which reflects how well a target field is monitored under the base station, is the most important performance metric used to measure the quality of surveillance that wireless sensor networks (WSNs) can provide. To facilitate the measurement of this metric, we propose two novel algorithms for individual sensor nodes to identify whether they are on the coverage boundary, i.e., the boundary of a coverage hole or network partition. Our algorithms are based on two novel computational geometric techniques called localized Voronoi and neighbor embracing polygons. Compared to previous work, our algorithms can be applied to WSNs of arbitrary topologies. The algorithms are fully distributed in the sense that only the minimal position information of one-hop neighbors and a limited number of simple local computations are needed, and thus are of high scalability and energy efficiency. We show the correctness and efficiency of our algorithms by theoretical proofs and extensive simulations. Chi Zhang received the B.E. and M.E. degrees in Electrical Engineering from Huazhong University of Science and Technology, Wuhan, China, in July 1999 and January 2002, respectively. Since September 2004, he has been working towards the Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Florida, Gainesville, Florida, USA. His research interests are network and distributed system security, wireless networking, and mobile computing, with emphasis on mobile ad hoc networks, wireless sensor networks, wireless mesh networks, and heterogeneous wired/wireless networks. Yanchao Zhang received the B.E. degree in computer communications from Nanjing University of Posts and Telecommunications, Nanjing, China, in July 1999, the M.E. degree in computer applications from Beijing University of Posts and Telecommunications, Beijing, China, in April 2002, and the Ph.D. degree in electrical and computer engineering from the University of Florida, Gainesville, in August 2006. Since September 2006, he has been an Assistant Professor in the Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark. His research interest include wireless and Internet security, wireless networking, and mobile computing. He is a member of the IEEE and ACM. Yuguang Fang received the BS and MS degrees in Mathematics from Qufu Normal University, Qufu, Shandong, China, in 1984 and 1987, respectively, a Ph.D. degree in Systems and Control Engineering from Department of Systems, Control and Industrial Engineering at Case Western Reserve University, Cleveland, Ohio, in January 1994, and a Ph.D. degree in Electrical Engineering from Department of Electrical and Computer Engineering at Boston University, Massachusetts, in May 1997. From 1987 to 1988, he held research and teaching position in both Department of Mathematics and the Institute of Automation at Qufu Normal University. From September 1989 to December 1993, he was a teaching/research assistant in Department of Systems, Control and Industrial Engineering at Case Western Reserve University, where he held a research associate position from January 1994 to May 1994. He held a post-doctoral position in Department of Electrical and Computer Engineering at Boston University from June 1994 to August 1995. From September 1995 to May 1997, he was a research assistant in Department of Electrical and Computer Engineering at Boston University. From June 1997 to July 1998, he was a Visiting Assistant Professor in Department of Electrical Engineering at the University of Texas at Dallas. From July 1998 to May 2000, he was an Assistant Professor in the Department of Electrical and Computer Engineering at New Jersey Institute of Technology, Newark, New Jersey. In May 2000, he joined the Department of Electrical and Computer Engineering at University of Florida, Gainesville, Florida, where he got early promotion to Associate Professor with tenure in August 2003, and to Full Professor in August 2005. His research interests span many areas including wireless networks, mobile computing, mobile communications, wireless security, automatic control, and neural networks. He has published over one hundred and fifty (150) papers in refereed professional journals and conferences. He received the National Science Foundation Faculty Early Career Award in 2001 and the Office of Naval Research Young Investigator Award in 2002. He also received the 2001 CAST Academic Award. He is listed in Marquis Who’s Who in Science and Engineering, Who’s Who in America and Who’s Who in World. Dr. Fang has actively engaged in many professional activities. He is a senior member of the IEEE and a member of the ACM. He is an Editor for IEEE Transactions on Communications, an Editor for IEEE Transactions on Wireless Communications, an Editor for IEEE Transactions on Mobile Computing, an Editor for ACM Wireless Networks, and an Editor for IEEE Wireless Communications. He was an Editor for IEEE Journal on Selected Areas in Communications:Wireless Communications Series, an Area Editor for ACM Mobile Computing and Communications Review, an Editor for Wiley International Journal on Wireless Communications and Mobile Computing, and Feature Editor for Scanning the Literature in IEEE Personal Communications. He has also actively involved with many professional conferences such as ACM MobiCom’02 (Committee Co-Chair for Student Travel Award), MobiCom’01, IEEE INFOCOM’06, INFOCOM’05 (Vice-Chair for Technical Program Committee), INFOCOM’04, INFOCOM’03, INFOCOM’00, INFOCOM’98, IEEE WCNC’04, WCNC’02, WCNC’00 Technical Program Vice-Chair), WCNC’99, IEEE Globecom’04 (Symposium Co-Chair), Globecom’02, and International Conference on Computer Communications and Networking (IC3N) (Technical Program Vice-Chair).     

Iterative Decoding of Orthogonal Space-Time Coded CPM Systems

We present an iterative decoding/demodulation technique for an orthogonal space-time coded continuous-phase modulation (OST-CPM) system. A low-complexity soft input and soft output (SISO) demodulator is developed based on the bidirectional soft output Viterbi algorithm (BSOVA) for the multiple antennas CPM systems. By taking advantage of the orthogonal structure, the complexity of extrinsic information extraction can be significantly reduced at each iteration.Shengli Fu received the B.S. and M.S. degree in telecommunication engineering from Beijing University of Posts and Telecommunications, Beijing, China, in 1994 and 1997, respectively. In 2000, he enrolled at the Wright State University, Dayton, OH, where he received the M.S. degree in Computer Engineering. He currently pursues his Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Delaware.His research interests include information and coding theory, MIMO wireless communication systems, and acoustic and visual signal processing.Genyuan Wang received B.Sc and MS. degrees in Mathematics from the Shanxi Normal University, Xian, China, in 1985 and 1988, respectively, and his Ph.D. degree in Electrical Engineering from Xidian University, Xian China, in 1998.From July, 1988 to September 1994, he worked at Shanxi Normal University as an Assistant Professor and then an Associate Professor. From September 1994 to May 1998, he worked at Xidian University as a research assistant. Currently, he is Post-Doctoral Fellow at Department of Electrical and Computer Engineering, University of Delaware. His research interests are radar imaging and radar signal processing, adaptive filter, OFDM system, channel equalization and space-time coding.Xiang-Gen Xia (M97,S00) received his B.S. degree in mathematics from Nanjing Normal University, Nanjing, China, and his M.S. degree in mathematics from Nankai University, Tianjin, China, and his Ph.D. degree in Electrical Engineering from the University of Southern California, Los Angeles, in 1983, 1986, and 1992, respectively.He was a Senior/Research Staff Member at Hughes Research Laboratories, Malibu, California, during 1995--1996. In September 1996, he joined the Department of Electrical and Computer Engineering, University of Delaware, Newark, Delaware, where he is a Professor. He was a Visiting Professor at the Chinese University of Hong Kong during 2002–2003. Before 1995, he held visiting positions in a few institutions. His current research interests include space-time coding, MIMO and OFDM systems, and SAR and ISAR imaging. Dr. Xia has over 100 refereed journal articles published, and 6 U.S. patents awarded. He is the author of the book Modulated Coding for Intersymbol Interference Channels (New York, Marcel Dekker, 2000).Dr. Xia received the National Science Foundation (NSF) Faculty Early Career Development (CAREER) Program Award in 1997, the Office of Naval Research (ONR) Young Investigator Award in 1998, and the Outstanding Overseas Young Investigator Award from the National Nature Science Foundation of China in 2001. He also received the Outstanding Junior Faculty Award of the Engineering School of the University of Delaware in 2001. He is currently an Associate Editor of the IEEE Transactions on Mobile Computing, the IEEE Signal Processing Letters, the IEEE Transactions on Signal Processing, the International Journal of Signal Processing, and the EURASIP Journal of Applied Signal Processing. He was a guest editor of Space-Time Coding and Its Applications in the EURASIP Journal of Applied Signal Processing in 2002. He is also a Member of the Signal Processing for Communications Technical Committee and the Sensor Array and Multichannel (SAM) Technical Committee in the IEEE Signal Processing Society.