Static Performance of 20 A, 1200 V 4H-SiC Power MOSFETs at Temperatures of −187°C to 300°C

Silicon carbide (4H-SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) have been attracting tremendous attention for high-power applications at a wide range of operating temperatures, owing to their normally-off characteristics, high-speed switching operation, avalanche capability, and low on-resistance. To optimize performance of 4H-SiC MOSFETs for various applications at different temperatures, it is important to understand the mechanisms of temperature dependence of the key parameters, such as on-resistance, threshold voltage, and metal–oxide–semiconductor (MOS) channel mobility. We report on the temperature dependence of the on-resistance of 20 A, 1200 V 4H-SiC power MOSFETs for temperatures ranging from −187°C to 300°C. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependences of the total on-resistance in different temperature regimes have been observed. Due to the poor MOS channel mobility and the low free carrier concentration in the inversion channel of the 4H-SiC MOSFET, the MOS channel resistance is the dominant part of the total on-resistance. This was also found to be true in a 4H-SiC long-channel lateral MOSFET.     

具有应变沟道及EOT 1.2nm高性能栅长22nm CMOS器件

深入研究了亚30nm CMOS关键工艺技术，特别是提出了一种新的低成本的提高空穴迁移率的技术--Ge预非晶化S/D延伸区诱生沟道应变技术，它使栅长90nm pMOS空穴有效迁移率在0.6MV/cm电场下提高32%. 而且空穴有效迁移率的改善，随器件特征尺寸缩小而增强. 利用零阶劳厄线衍射的大角度会聚束电子衍射分析表明，在沟道区相应的压应变为-3.6%. 在集成技术优化的基础上，研制成功了高性能栅长22nm应变沟道CMOS器件及栅长27nm CMOS 32分频器电路（其中分别嵌入了57级/201级环形振荡器）, EOT为1.2nm,具有Ni自对准硅化物.     

Investigation of the Interfaces in Ni-FUSI/Hf-Based/Si and Ni-FUSI/SiO<Subscript>2</Subscript>/Si Stacks by Physical and Electrical Characterization Techniques

The combination of full Ni silicidation (Ni-FUSI) gate electrodes and hafnium-based high-k gate dielectrics is one of the most promising replacements for poly-Si/SiO₂/Si gate stacks for the future complementary metal–oxide–semiconductor (CMOS) sub-45-nm technology node. The key challenges to successfully adopting the Ni-FUSI/high-k dielectric/Si gate stack for advanced CMOS technology are mostly due to the interfacial properties. The origins of the electrical and physical characteristics of the Ni-FUSI/dielectric oxide interface and dielectric oxide/bulk interface were studied in detail. We found that Ni-FUSI undergoes a phase transformation during silicide formation, which depends more on annealing temperature than on the underlying gate dielectric material. The correlations of Ni–Si phase transformations with their electrical and physical changes were established by sheet resistance measurements, x-ray diffraction (XRD), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) analyses. The leakage current density–voltage (J–V) and capacitance–voltage (C–V) measurement techniques were employed to study the dielectric oxide/Si interface. The effects of the postdeposition annealing (PDA) treatment on the interface charges of dielectric oxides were studied. We found that the PDA can effectively reduce the trapping density and leakage current and eliminate hysteresis in the C–V curves. In addition, the changes in chemical bonding features at HfO₂/Si and HfSiO/Si interfaces due to PDA treatment were evaluated by XPS measurements. XPS analysis provides a better interpretation of the electrical outcomes. As a result, HfSiO films exhibited superior performance in terms of thermal stability and electrical characteristics.     

Analysis of the parasitic S/D resistance in multiple-gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

Nonvolatile Metal–Oxide–Semiconductor Capacitors with Ru-RuOx Composite Nanodots Embedded in Atomic-Layer-Deposited Al2O3 Films

Growth of Ru-RuO _x composite nanodots (RONs) on atomic-layer-deposited Al₂O₃ films has been investigated using magnetic sputtering of a Ru target followed by postdeposition annealing. RONs with a density as high as ~2 × 10¹² cm⁻² were obtained together with good uniformity. Subsequently, metal–oxide–semiconductor capacitors with RONs embedded in Al₂O₃ films have been electrically characterized for different configurations of tunneling layers (T)/blocking layers (B), and the underlying mechanisms of charge storage are discussed. For a 6-nm T/22-nm B device, a memory window of 3.7 V is achieved for a ±7 V programing/erasing voltage for 0.1 ms, and superior charge retention of more than 80% is achieved after 10 years.     

Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high-κ II–VI tunnel insulator stack and self-assembled GeO _x -cladded Ge quantum dots as the charge storage units. A Si₃N₄ layer was used as the control gate insulator. Capacitance–voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.     

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.     

Anomalous narrow width effect in p-channel metal–oxide–semiconductor surface channel transistors using shallow trench isolation technology

For PMOS (p-channel metal–oxide–semiconductor) transistors isolated by shallow trench isolation (STI) technology, reverse narrow width effect (RNWE) was observed for large gate lengths such that the magnitude of the threshold voltage becomes smaller when the channel width decreases. However, PMOS transistors with small gate lengths show up a strong anomalous narrow width effect such that the magnitude of the threshold voltage becomes larger when the channel width decreases. We attribute such an anomalous narrow width effect to an enhancement of phosphorus and arsenic transient enhanced diffusion (TED) due to Si interstitials generated by the deep boron source/drain (S/D) implant towards the gate/STI edge.     

A novel partial-SOI LDMOSFET (>800 V) with n-type floating buried layer in substrate

In this paper, a novel high voltage lateral double diffused metal–oxide–semiconductor (LDMOS) field effect transistor based on partial silicon-on-insulator (PSOI) technology is proposed and investigated based on the numerical simulations. The structure is characterized by an n-type floating buried layer (NFBL) in the substrate under the silicon window near the drain. The buried layer in the substrate modulates the lateral and vertical electric field, which results in the electric field of the drift region distributed uniformly. Therefore, the breakdown voltage (BV) of the device is significantly improved. The influences of the key parameters on device performance of the proposed structure are discussed. Moreover, the self-heating effect (SHE) is greatly alleviated duo to the silicon window helps thermal conduction to the substrate, which improved the reliability of device application.     

Device Design of High–Speed Source–Heterojunction–MOS Transistors (SHOTs): Optimization of Source Band Offset and Graded Heterojunction

We have studied the device design of 15-nm highspeed n-channel source-heterojunction-MOS transistors (SHOTs) utilizing high-velocity electron injection from the source into the channel region and using the conduction-band-offset energy between the source and the channel regions. The band-offset energy near the source region and the length of the graded heterojunction are key parameters for realizing high-speed operation of SHOTs. A 2D device simulator indicates that the enhancement in transconductance G_m in SHOTs on an SOI substrate over conventional SOI-MOSFETs without source-heterojunction structures strongly depends on the source conduction-band-offset value DeltaE_c and the length of graded-heterojunction structures L_H in SHOTs. Moreover, the G_m enhancement of SHOTs is affected by the drain and the gate biases. We have shown that, with fully optimized DeltaE_c and L_H values, the G_m enhancement of SHOT due to high-velocity electron injection can be achieved in a whole range of drain bias. The optimized SHOT is quite promising for high-speed CMOS devices in the 10-nm regime.     

32nm CMOS工艺技术挑战

根据国际半导体技术发展蓝图(international technology roadmap for semiconductor,ITRS),CMOS技术将于2009年进入32nm技术节点.然而,在CMOS逻辑器件从45nm向32nm节点按比例缩小的过程中却遇到了很多难题.为了跨越尺寸缩小所带来的这些障碍,要求把最先进的工艺技术整合到产品制造过程中.文中总结并讨论了可能被引入到32nm节点的新的技术应用,涉及如下几个方面:浸入式光刻的延伸技术、迁移率增强衬底技术、金属栅/高介电常数栅介质(metal/high-k,MHK)栅结构、超浅结(ultra-shallow junction,USJ)以及其他应变增强工程的方法,包括应力邻近效应(stress proximity effect,SPT)、双重应力衬里技术(dualstress liner,DSL)、应变记忆技术(stress memorization technique,SMT)、STI和PMD的高深宽比工艺(high aspect ratio process,HARP)、采用选择外延生长(selective epitaxial growth,SEG)的嵌入SiGe(pFET)和SiC(nFET)源漏技术、中端(middle of line,MOL)和后端工艺(back-end of line,BEOL)中的金属化以及超低k介质(ultra low-k,ULK)集成等问题.     

32nm CMOS工艺技术挑战

根据国际半导体技术发展蓝图（international technology roadmap for semiconductor, ITRS) , CMOS技术将于2009年进入32nm技术节点. 然而,在CMOS逻辑器件从45nm向32nm节点按比例缩小的过程中却遇到了很多难题. 为了跨越尺寸缩小所带来的这些障碍,要求把最先进的工艺技术整合到产品制造过程中. 文中总结并讨论了可能被引入到32nm节点的新的技术应用,涉及如下几个方面：浸入式光刻的延伸技术、迁移率增强衬底技术、金属栅/高介电常数栅介质（metal/high-k, MHK）栅结构、超浅结（ultra-shallow junction, USJ）以及其他应变增强工程的方法,包括应力邻近效应（stress proximity effect, SPT) 、双重应力衬里技术（dual stress liner, DSL) 、应变记忆技术（stress memorization technique, SMT) 、STI和PMD的高深宽比工艺（high aspect ratio process, HARP) 、采用选择外延生长（selective epitaxial growth, SEG）的嵌入SiGe (pFET）和SiC (nFET）源漏技术、中端（middle of line, MOL）和后端工艺（back-end of line, BEOL）中的金属化以及超低k介质（ultra low-k, ULK）集成等问题.     

MOS Characteristics of C-Face 4H-SiC

Metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated on the carbon face of 4H-SiC were characterized following different postoxidation annealing methods used to passivate the oxide–semiconductor (O–S) interface. Of the various processes studied, sequential postoxidation annealing in NO followed by atomic hydrogen gave the lowest interface trap density (D _it). Direct oxidation/passivation in NO yielded somewhat better I–V characteristics, though all passivation ambients produced approximately the same breakdown field strength. n-Channel MOSFETs showed high channel mobility at low field, which is likely caused by the presence of mobile ions at the O–S interface. Comparisons with the silicon face are presented for interface trap density, oxide breakdown field, and channel mobility. These comparisons suggest that the carbon face does not offer significant performance advantages.     

Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node

In this paper, we review different CMOS technologies used at CEA-LETI to improve hole and electron velocity for the 32 nm technology node Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs. The orientation, the strain and the material of the channel are the key parameters that have been tuned and optimized. Tensile strained SOI (sSOI) for nMOS and compressive Ge for pMOS are found to be promising channels for CMOS integration. They provide a 2 times (7.5 times) mobility improvement for electrons (holes), giving rise to well-balanced drain currents for n and pMOS. They also allow a tuning of the threshold voltage. The gate length and width scalabity of these technologies are also addressed. In particular, we detail the excellent performance of strained Si_0.6Ge_0.4 and sSOI down to 30 nm gate length. We also discuss the specifics of short channel transport in these channels: the role of the carrier mobility, the limiting scattering phenomena and the ballistic transport.     

Mobility enhancement techniques for Ge and GeSn MOSFETs

The performance enhancement of conventional Si MOSFETs through device scaling is becoming increasingly difficult.The application of high mobility channel materials is one of the most promising solutions to overcome the bottleneck.The Ge and GeSn channels attract a lot of interest as the alternative channel materials,not only because of the high carrier mobility but also the superior compatibility with typical Si CMOS technology.In this paper,the recent progress of high mobility Ge and GeSn MOSFETs has been investigated,providing feasible approaches to improve the performance of Ge and GeSn devices for future CMOS technologies.     

Design of monostable–bistable transition logic element using the BiCMOS-based negative differential resistance circuit

The monostable–bistable transition logic element (MOBILE) is a promising application for negative differential resistance (NDR) circuit. Previously reported MOBILE is constructed by resonant tunneling diode (RTD) that is implemented by the molecular beam epitaxy (MBE) process. However in this paper, we first propose a NDR circuit composed of standard Si-based metal–oxide–semiconductor field-effect transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). Then we demonstrate the inverter, NAND, and NOR gate operations using this MOS–HBT–NDR-based MOBILE circuit. The great advantage of this NDR-based application is that we can implement it using the standard SiGe BiCMOS process without the need for the MBE system.     

A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and helium

In this paper a novel device named as SDOV MOSFET is proposed for the first time. This structure features localized void layers under the source and drain regions. The short channel effects of this device can be improved due to the SOI-like source/drain structure. In addition, without the dielectric layer under the channel region, this device can avoid some weaknesses of UTB SOI devices caused by the thin silicon film and the underlying buried oxide, such as mobility degradation, film thickness fluctuation and self-heating effect. Based on self-aligned hydrogen and helium co-implantation technology, the new device can be fabricated by a process compatible with the standard CMOS process. The SDOV MOSFETs with 50 nm gate length are experimentally demonstrated for verification.     

High performance low temperature metal-induced unilaterallycrystallized polycrystalline silicon thin film transistors forsystem-on-panel applications

Thin film transistors (TFTs) with low-temperature processed metal-induced laterally crystallized (MILC) channels and self-aligned metal-induction crystallized (MIC) source and drain regions have been demonstrated recently as potential devices for realizing electronics on large-area, inexpensive glass panels. While these TFTs are better than their solid-phase crystallized counterparts in many device performance measures, they suffer from higher off-state leakage current and early drain breakdown. A new technology is proposed, employing metal-induced-unilateral crystallization (MIUC), which results in the removal from the edges of and within the channel region all major grain boundaries transverse to the drain current flow. Compared to the conventional “bilateral” MILC TFTs, the new MIUC devices are shown to have higher field-effect mobility, significantly reduced leakage current, better immunity to early drain breakdown, and much improved spatial uniformity of the device parameters. Thus they are particularly suitable for realizing low temperature CMOS systems on inexpensive glass panels     

Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping

Graded doping profile in the channel of vertical sub-100-nm nMOSFETs was investigated in this study. Conventional single-step ion implantation was used to form the asymmetric graded doping profile in the channel. No large-angle-tilt implant is needed. The device processing is compatible with conventional CMOS technology. In a graded-channel-doping device, with the higher doping near the source, drain induced barrier lowering (DIBL) and the off-state leakage current are reduced significantly. The graded doped channel also has a lower longitudinal electric field near the drain. Therefore, hot-carrier related reliability is improved substantially with this type of device structure.