The metal-nitride-oxide-silicon (MNOS) transistor—Characteristics and applications

Recent advances in silicon nitride deposition techniques have led to the emergence of the metal-nitride-oxide-silicon (MNOS) integrated circuit technology as an alternative and supplement to the existing MOS technology. Applications of MNOS field-effect transistors have been proposed for both logic circuits (as an alternative to MOS transistors) and nonvolatile memory arrays This paper reviews the characteristics and applications of MNOS transistors. It presents a unified approach to the characterization of both stable and variable turn-on voltage MNOS transistors. The analysis is based on an extensive investigation of charge transport and storage in MNOS structures. The different modes of transistor operation are described and analyzed in terms of the physical parameters of the two-layer dielectric structure. Understanding of the physical mechanisms underlying transistor operation is applied to the optimization of transistor structure and performance for different digital integrated circuit applications. The feasibility of these applications is demonstrated by fabrication of a nonvolatile semiconductor storage array and a nonvolatile flip-flop.     

Electrical and charge storage characteristics of the tantalum oxide-silicon dioxide device

The electrical characteristics of the tantalum oxide-silicon dioxide double-dielectric structure are described. The MTOS structure (metal-tantalum oxide-silicon dioxide-silicon) is similar to the MNOS double dielectric which is used as a nonvolatile memory element except tantalum oxide (Ta2O5) is used to replace the silicon nitride as the second dielectric. Capacitance voltage measurements show a negative QSSwith magnitudes smaller than those in compatable MNOS devices. Conduction characteristics of both anodic and thermally grown Ta2O5have been studied and both have been found to follow a Poole-Frenkel mechanism. The memory characteristics of the MTOS have been investigated and preliminary data are presented. Where MNOS data are available, the MTOS characteristics have been compared with those of the MNOS structure. It is shown that the threshold voltage of the MTOS device can be shifted using lower gate voltages than are needed for a comparable MNOS device. It thus appears that the MTOS device has some decided potential advantages over the MNOS structure as a nonvolatile memory element.     

Novel solid-state imaging devices with inherent MNOS memory gate

A novel solid-state imaging device with an inherent MNOS memory gate is proposed and writing and reading characteristics are discussed. To improve the writing of the low light inputs, a bias charge in addition to the signal charge is transferred into the MNOS memory Capacitor from a photodiode. Both enhanced writing and a Wide dynamic range are obtained under the following optimum bias condition: a preset photodiode voltage of 5 V, a memory pulse voltage of 35 V amplitude, and a 1-10 µs duration. Moreover, it was found that the stored charge signal could be nondestructively read from drain output under bias light, provided the drain voltage VDwas biased higher than the Surface potenteal φMGin the depletion layer below the memory gate. If VD< φMG, however, incoming light signals are detected regardless of shifts in the flat-band voltage optically induced during the Writing process. Finally, the reproduced images of readout and incoming light signals are demonstrated using a 5 × 5 2-D array.     

MNOS LSI memory device data retention measurements and projections

The retention characteristics of an MNOS LSI memory device are interpreted from the properties of its basic MNOS transistor. A technique is developed for measuring and predicting retention properties of large quantity device lots. A production lot test method for determining the 10 000-h data retention properties of LSI memory devices is proposed. Also included in the paper are measured failure rates, identifying the retention failures and reliability for a specific LSI memory device.     

New two-terminal C-MNOS memory cells

New two-terminal nonvolatile memory cells are proposed, in which an n-channel MNOS transistor is functionally integrated with a p-channel MNOS or MOS transistor. The operational principle of both types of the cells is substantially based on the Λ (lambda)-shaped I-V Characteristic of complementary FET's. The most valuable feature of the new cells is the unipolar pulse operation of the simple diode-matrix array which can be used in a RAM mode by the use of selective writing and erasing as well as in an electrically alterable PROM mode.     

A new MNOS memory element—the tunnel diode

MNOS (Metal-Nitride-Oxide-Silicon) memory devices commercially available today consist of transistor arrays where each device represents a memory bit. Typical devices have densities greater than 8 K bits and are generally manufactured on epitaxial based processes for isolation. The state of each bit is determined by its threshold voltage and is sensed by interpreting if the transistor is in the “off” or “on” condition. A new MNOS memory element is described where detection of junction tunnelling current is used as the sense mechanism. Substrate forms the “third” terminal and the element has the possibility of being the basis of a dense array. The technique can be developed in p or n channel and can be used as an add-on to volatile random access memories.     

MNOS density parameters

Some aspects of the feasibility of the MNOS technology for the realization of large read/write memory systems are examined. Contemporary and near term density parameters for volume, weight, and power are presented. Achievable memory cells and die sizes are examined. The impact of nonvolatility on system reliability is explained. Packaging density forchip assemblies and memory systems is reviewed. Finally, the parameters and reliability of a 10⁹bit MNOS memory are described.     

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm², a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10⁴write/erase cycles.     

Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 /spl mu/m and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180/spl mu/m2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of /spl plusmn/1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10/sup 4/ write/erase cycles.     

Memory modes of ferroelectric field effect transistors

Effects of traps on the memory characteristics of ferroelectric field effect transistors with the metat-ferroelectric-insulator-semiconductor structure were theoretically analyzed. Various modes of operation, i.e. the polarization-limited mode, trap-limited mode, critical field-limited mode, MNOS mode and probability-limited mode, were derived depending on the device parameters. Experimental devices with gate insulator BaTiO₃ or PLZT were fabricated by using thin film SnO₂ and thin film Te. The memory characteristics of these devices were interpreted in terms of the trap-limited mode and MNOS mode, respectively.     

Nonvolatile semiconductor memory devices

An attempt is made to survey and assess the nonvolatile semiconductor memory devices including charge-storage devices and FET's with ferroelectric gate insulators. The charge-storage devices are further divided into two groups: 1) charges-trapping devices such as the MNOS and the MAOS, and 2) floating-gate devices such as the FAMOS and the DDC. Approaches for achieving virtual nonvolatility in otherwise volatile semiconductor memories are briefly disscused. Novel structures which provide nonvolatility as well as the theoretical limit of memory array density are also explored.     

The influence of nitride thickness variations on the switching speed of MNOS memory transistors

The influence of nitride thickness variations on the switching speed of MNOS memory transistors is examined. The switching time constant is calculated as a function of the nitride thickness using a model of modified Fowler-Nordheim injection. The calculated characteristics compare well with measured characteristics and show a strong dependence on the nitride thickness.     

Nonvolatile static read/write memory cell using CMNOS structure

A new type of nonvolatile static read/write memory cell constructed with three MOS transistors and one MNOS transistor is proposed. The MNOS transistor and one of the MOS transistors involved are complementary combined to offer binary states in the Λ-shapedI-Vcurve for memory operation under normal power supply. Upon power failure, the MNOS transistor acts as a back-up element for nonvolatility. The new cell is characterized by advantageous features such as small cell size, simple peripheral circuit, operation with a unipolar power supply and low standby power consumption.     

A model of write-inhibition in dynamic injection MNOS

Dynamic Injection MNOS (DIMNOS) memory devices feature high-speed writing, 5-V drain voltage, and MNOS backup one-transistor-type dynamic RAM's. They are written on MNOS, like conventional one-transistor-type dynamic RAM's, when high writing voltage is applied to the MNOS gate. In experiments with DIMNOS, the threshold-voltage shift (Delta V_{th}) of MNOS in the writing mode does not depend very much on temperature;Delta V_{th}in the write-inhibited mode depends hardly at all on temperature; andDelta V_{th}in the write-inhibited mode decreases under the condition that the product of the number of attempts and pulsewidth is constant when he pulsewidth is longer than 10^-4s. The proposed model in the write-inhibited mode means that weak avalanche occurs due to field concentration between the control transistor and MNOS memory region. As a result, hot electrons are injected between the ultrathin SiO2and Si3N4films of MNOS. This model is supported by the above mentioned experimental results in the write-inhibited mode.     

Test results on an MNOS memory array

The NCR 2050 MNOS memory chip, developed under Air Force contract for frequency-preset applications in communications equipment, has been tested and evaluated. Results on retentivity, writing characteristics, pattern sensitivity, and endurance are presented.     

Endurance of thin-oxide nonvolatile MNOS memory transistors

A discussion of the factors which determine the endurance of thin-oxide MNOS memory transistors is presented. Si-SiO2interface states are influential in the early stages of erase/write cycling, while charge movement into the nitride controls the long term cycling characteristics. Other important variables include the method of preparation of the thin-oxide region, its composition, dielectric properties and thickness; the high density of spatially localized traps near the nitride-oxide interface; the low conductivity Si3N4dielectric, and electric field strengths. Optimizing these variables permits MNOS memory transistors to be operated with high endurance, reliably to beyond 10¹⁰erase/write cycles with ±20-V, 100-µs pulses and demonstrate a minimum 2-V memory window at 2900 h retention time.     

Estimation of insulation layer conductance in MNOS structure

A method for estimating the conductance of each insulation layer of MNOS devices is described. In this method, the conductance values can be independently estimated using the frequency dependence of the capacitance and conductance versus gate voltage characteristics. The frequency dependence in the accumulation region can be explained by an equivalent circuit which considers the substrate resistance and the conductance of each insulation layer. It was found that the conduction processes in nitride and oxide layers are dominated by Frenkel-Poole emission and direct tunnelling emission, respectively, and that the degradation of retention characteristics of MNOS memory devices with erase/write cycles is caused by increased nitride conductance     

MNOS/CCD nonvolatile analog memory

MNOS storage sites have been integrated with an n-channel CCD to produce a nonvolatile memory capable of storing sampled analog signals. Analog signals, sampled at the CCD input, are stored as trapped charge in the MNOS dielectric and may be replicated nondestructively after four days of storage with a linear dynamic range of 33 dB.     

Memory traps in MNOS diodes measured by thermally stimulated current

Thermally stimulated current was measured to determine trap distribution and charging and discharging mechanisms in a Metal-Nitride-Oxide-Semiconductor (MNOS) diode with 16 Å oxide thickness. By changing gate voltage, heating rate and the initial flat-band voltage, the memory traps near the nitride-oxide interface were separated from the others. The general formula was derived for the thermally stimulated current in an MNOS diode and was applied to obtain the trap distribution as well as effective emission time constants. The results indicate that the memory traps are distributed 50 Å deep into the nitride film from the nitride-oxide interface. The energy level lies at around 2·55 eV from the bottom of the nitride conduction band. The charging and discharging mechanism is the cascade connection of tunneling and thermal excitation or trapping. The obtained trap distribution and the charge transfer mechanism are successful for interpreting the write-in and retention characteristics.     

Fully decoded MNOS storage arrays in ESFI MOS technology

The operation of MNOS memory transistors realized in thin epitaxial silicon films on insulators (ESFI) is described for writing, erasing, and reading, and their behavior is explained by means of the so-called storage characteristics. From exploratory matrices with 2/spl times/2 elements the expected data of a 4-kbit chip are estimated.