A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI

A 300-MHz 16-b fixed-point digital signal processor (DSP) core LSI has been developed for video signal processing. In order to achieve high performance, the DSP core LSI employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design. The DSP core LSI, which was fabricated with 0.5-μm BICMOS and triple-level-metallization technology, has a 3.9 mm×4.6 mm area, and contains about 57K transistors. It consumes 2 W at a 300-MHz clock frequency with a 3.3-V power supply. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively     

70-MHz 2-μm CMOS bit-level systolic array median filter

An algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by operation on three interleaved independent sequences for a total of 75 samples, is presented as a demonstration of the concept. The throughput relevant to one sequence is 1/3 for this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2-μm CMOS technology have been successfully tested at a clock frequency over 70 MHz     

A 0.8-μm CMOS technology for high-performance ASIC memory andchannelless gate array

A 0.8-μm polycide-gate, double-layer-metal CMOS technology is described. Nominal device gate lengths down to 0.8 (±0.2) μm are used for both n- and p-channel transistors. Compact isolation, 175-A gate oxide grown in dry/wet/dry ambient, shallow-junction halo-implanted lightly doped drain n and p devices, TiN contact barrier, and a planarized double-layer-metal process are all integrated and demonstrated with a 0.8-μm full-CMOS 16K SRAM (static random-access memory) circuit. The device process integrity, design margins, performance, reliability, product yield and speed enhancement are all discussed in detail     

A 70-MHz 32-b microprocessor with 1.0-μm BiCMOS macrocelllibrary

A custom 529 K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm² die. Employing BiCMOS macrocells, a 32-b execution unit, extensible ROM, RAM, a PLL (phase-locked loop) clock generator with bipolar drivers, and sense circuits, and a peak performance of 70 MIPS (million instructions per second) are achieved. Power consumption is 2.1 W at 40 MHz     

A 0.25-μm CMOS 0.9-V 100-MHz DSP core

This paper describes a 0.25-μm CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-μm CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs     

A 10-b 40-MHz 0.8-μm CMOS current-output D/A converter

A 10-b binary-weighted D/A digital-to-analog converter based on current division is presented. The effective resolution bandwidth is 5 MHz at a maximum clock frequency of 40 MHz. The circuit is integrated in a 0.8-μm double-metal CMOS technology and the chip area is 0.4 mm². This particular converter was realized by constructing the bit currents through a careful combination of unit current sources and by limiting the driving voltage on the gates of the current switches     

A 1.2-μm BiCMOS sample-and-hold circuit with aconstant-impedance, slew-enhanced sampling gate

A new sampling gate circuit, with dual outputs functioning alternately in the track and hold modes, is integrated in an open-loop sample-and-hold circuit architecture achieving greater than 450-MHz small-signal input bandwidth and 100-MHz maximum sample rate. The sampling gate also incorporates slew enhancement techniques to achieve (+430 V/μs, -510 V/μs) slew rate and features a `built-in' buffer to maintain constant input impedance for both the track and hold modes, simplifying design of the front-end input buffer. Special on-chip clock generation circuits are used to minimize sampled pedestal (+4 mV). Power dissipation is less than 300 mW, including output driver. Measured harmonics are 58 dB down for a 2 V_p-p 20-MHz sine wave sampled at 100 MHz     

A low power 8-tap digital FIR filter for PRML read channels

This paper presents a low power 8-tap digital Fourier infrared (FIR) filter for partial response signalling with maximum likelihood (PRML) disk-drive read channels. Enhancements on power consumption and speed are achieved by adopting the row compression scheme with a proposed conditional carry selection method. The 8-tap digital FIR filter is fabricated by 0.8µm CMOS technology and occupies by 3.9mm × 1.5mm. The experimental results show that the FIR filter operates up to 180MHz and dissipates 1.4mW MHz^?1 with 3.7V power supply. It is proved that 20% power reduction is readily attainable with the proposed scheme.     

0.5-μm 2 M-transistor BiPNMOS channelless gate array

A channelless gate array has been realized using 0.5-μm BiCMOS technology integrating more than two million transistors on a 14-mm×14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to form the BiPNMOS gate. The gate is suitable for 3.3-V supply and achieves 230-ps gate delay for a two-input NAND with full-swing output. Added small-size MOS transistors in the BiPNMOS basic cell can also be used for memory macros effectively. A test chip with four memory macros-a high-speed RAM, a high-density RAM, a ROM, and a CAM macro-was fabricated. The high-speed memory macros utilize bipolar transistors in bipolar middle buffers and in sense amplifiers. The high-speed RAM macro achieves an access time of 2.7 ns at 16-kb capacity. The high-density RAM macro is rather slow but the memory cell occupies only a half of the BiPNMOS basic cell using a single-port memory cell     

Level-shifted 0.5-μm BiCMOS circuits

A circuit concept, level shifting, is presented for scaled BiCMOS circuits. A full-swing, ground-level-shifted (FS-GLS) BiCMOS circuit has shown approximately 1.6× speed improvement over a conventional partial-swing BiCMOS circuit, and a 4× better driving capability over a CMOS circuit at 3.3 V. With a high-performance p-n-p device, simulations show that the level-shifted complementary BiCMOS can provide further speed leverage over the BiCMOS circuit with n-p-n only     

A 0.8-μm BiCMOS ATM switch on an 800 Mb/s asynchronous bufferedbanyan network

An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8-μm BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical)     

A BiCMOS low-distortion 8-MHz low-pass filter

An 8-MHz seventh-degree elliptic-function low-pass filter is described, demonstrating an approach to low-distortion antialias filtering for high-definition video applications. The filter's performance goals are achieved through the use of circuit design principles that capitalize on the strengths of BiCMOS technology. The integrator circuits composing the filter consist of a new wideband low-distortion transconductor circuit and a unique BiCMOS Miller-stage circuit. Integrator time constants are determined by stable RC products, enabling a simplified filter calibration scheme that is insensitive to temperature-induced variations and requires no phaselock circuits. The prototype filter IC, consisting of seven integrators assembled in an active-ladder configuration, was fabricated in a 10-V, 2-μm 2.5-GHz BiCMOS technology that also features thin-film resistors and polysilicon-plate capacitors. Measured results from the calibrated filter show passband flatness of 0.2 dB, with aberrations of less than ±1 dB over a 100°C temperature range. Stopband attenuation meets its designed goal of 60 dB. Driven by 7-V_pp, differential input signals, the filter exhibits less than -72-dBc third-order intermodulation distortion products at 1 MHz. For 5-V_pp inputs at 4 MHz, third-order intermodulation spurs remain below -65 dBc     

A 2-μm BiCMOS process utilizing selective epitaxy

A 2-μm BiCMOS process designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar structure with an estimated cutoff frequency of 5 GHz and nonoptimized vertical p-n-p structure into a 2-μm CMOS process with a poly-to-n⁺ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps and with no change to the critical process parameters which determine the performance of the MOS transistors     

A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP)ULSI

The first single-chip 64-b vector-pipelined processor (VPP) ULSI is described. It executes vector operations indispensable to high-speed scientific computation. The VPP ULSI attains a 200-MFLOPS peak performance at a 100-MHz clock frequency. This extremely high performance is made possible by the integration on the VPP of a 64-b five-stage pipelined adder/shifter, a 64-b five-stage pipelined multiplier/divider/logic operation unit, and a 40-kb register file. Various new high-speed circuit techniques have been also developed for 100-MHz operations. The chip, which was fabricated with a 0.8-μm BiCMOS and triple-layer metallization process technology, has a 17.2-mm×17.3-mm area and contains about 693 K transistors. It consumes 13.2 W at a 100-MHz clock frequency with a single 5-V power supply     

A high performance 0.35-μm 3.3-V BiCMOS technology optimized forproduct porting from a 0.6-μm 3.3-V BiCMOS technology

A 0.35-μm logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-μm 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-μm 3.3-V BiCMOS design to a 0.35-μm design is described. The silicon results are described     

A CMOS 0.8-μm transistor-only 1.63-MHz switched-current bandpassΣΔ modulator for AM signal A/D conversion

This paper presents a CMOS 0.8-μm switched-current (SI) fourth-order bandpass ΣΔ modulator (BP-ΣΔM) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z^-1 →-z^-2) to a 1-bit second-order low-pass ΣΔ modulator (LP-ΣΔM). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz     

A 200-MHz seventh-order equiripple continuous-time filter by designof nonlinearity suppression in 0.25-μm CMOS process

Seventh-order equiripple filter with cutoff frequency of 200 MHz is developed in CMOS 0.25-μm process. A new design method has been adopted to obtain enough accuracy and linearity in high-frequency operation. Optimal device sizes are determined, which maximize the accuracy. The most suitable filter configuration is determined, which suppresses the influence of the nonlinearity of the transconductors over the linearity of the filter. Experimental results satisfied group delay variation of ±5% and achieved total harmonic distortion of less than 1% for 800 mV_ppd differential input     

A low-noise, 900-MHz VCO in 0.6-μm CMOS

This paper describes a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6-μm CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. The measured results of the phase noise are -101 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 600-kHz offset from the carrier frequency. This value is comparable to that of LC-based integrated oscillators. The oscillator consumes 10 mA from a 3.0-V power supply. A prototype frequency synthesizer with the VCO is also implemented in the same technology, and the measured phase noise of the synthesizer is -113 dSc/Hz at 100-kHz offset     

A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bitmicroprocessor

A 0.25-μm, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm² silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in high speed dynamic circuits without body contact. C-V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test     

A 250-MHz wave pipelined adder in 2-μm CMOS

Wave pipelining (also known as maximal rate pipelining) is a timing methodology used in digital systems to increase the number of effective pipelined stages without increasing the number of physical registers in the system. Using this technique, new data are applied to the inputs of a combinational block before the previous outputs are available, thus effectively pipelining the combinational logic. Achieving a high degree of wave pipelining in CMOS technology requires careful study of delay balancing technique involving circuit design, layout method, and testing structure. A 16-b parallel adder, utilizing wave pipelining is implemented with MOSIS 2-μm technology and test results of fabricated devices show more than nine times speedup over nonpipelined operation