一种Ku波段宽调谐范围高输出功率的InGaP/GaAs HBT VCO

本文介绍了一种采用InGaP/GaAs HBT工艺实现的全集成应用于Ku波段的压控振荡器(VCO)。该VCO采用Colpitts结构,以达到宽调谐范围,并且该VCO取得了较高的输出射频功率。测试结果表明：该VCO的振荡频率为12.82 GHz～14.97 GHz,调谐范围为15.47%,输出射频功率为0.31 dBm～6.46 dBm,在载频13.9 GHz处相位噪声为-94.9 dBc/Hz@1 MHz。在5 V单电源直流偏置下该VCO的功耗为52.75 mW,其芯片尺寸为0.81 mm×0.78 mm。最后,本文对VCO的品质因数FOM指标进行了讨论。     

嵌入式自动聚焦模组技术现状及展望

综述了手机自动聚焦模组技术国内外研究现状,对模组主要部件镜头、图像传感器、致动器的发展历程做出较详细的阐述,同时概括了在手机中实现自动聚焦驱动控制的工程应用方法,并提出了手机聚焦模组的发展前景与展望,如液体透镜、液晶镜头以及基于MEMS的自动聚焦技术的应用发展。     

基于LTCC技术的Ku波段四通道T/R组件研制

基于相控阵雷达的应用需求,利用LTCC多层基板技术,研制了Ku波段四通道T/R组件。该组件通过三维布局实现了组件的小型化和轻量化,同时也保证了射频、电源和控制的信号完整性。通过微带线变换带状线的优化设计,实现了良好的传输性能,提高了四通道信号间的隔离度。腔体内部做了隔墙设计,避免四通道的信号干扰,保证一致性。最终研制实现的小型化Ku波段四通道T/R组件,尺寸仅为70 mm×37.8 mm×11.5 mm,质量约53 g,组件接收增益大于25 dB,噪声系数小于4 dB,发射功率大于16 W。该T/R组件四通道一致性好,性能稳定,具有较好的应用价值。     

Design method and material technologies for passives in printed circuit Board Embedded circuits

The integration of passive components into the printed circuit board (PCB) as embedded passives integrated circuits (emPIC) results in a higher power density of power converters. To achieve a highly automated, low cost, integral manufacturing, the devices are constructed layer wise. Materials and processes necessary for the manufacturing of such circuits are described in this publication. Especially for magnetic components like inductors and transformers the design of such thin components is challenge. Because of the high aspect ratio, traditionally used models lead to a high calculation effort or use nonappropriate approximations. This contribution presents an analytic approach for the design. The model considers the magnetic flux distribution in the core and in the winding area and therefore allows a precise calculation of the inductivity as well as the losses in the device and their distribution. It is very well suited for a parametric analysis and thus for the synthesis of thin planar magnetic components. Material technologies for the construction of the capacitive layers and the magnetic cores are investigated. A ferrite polymer compound is adapted to be compatible with the PCB laminating process. Accordingly a 60-W offline converter was designed and fabricated using the new technology. Its transformer is entirely integrated in the PCB as well as 11 capacitors. Standard PCB lamination processes are used for the layerwise integration of the components. The circuit needs an area of the size of a credit card with a PCB thickness of 4 mm. Up to 82% efficiency could be demonstrated.     

基于90nmCMOS工艺的低功耗宽带压控振荡器设计

A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET(IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range(FTR) of 18.4%and a phase noise of –101.38 d Bc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185d Bc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

Application of PVD silver for integrated microwave passives in silicon technology

High quality broadband passives are needed to implement MMIC/MIC in silicon. This paper discusses potential benefits of silver metallization to boost the performance of the integrated passive components. Silver is chosen because this metal offers the highest possible electrical conductivity at room temperature. A PVD process was used for silver deposition because this technique meets the requirements of high purity and surface quality. Electromigration, electrochemical migration and agglomeration are not expected to be a problem in silver microwave passives due to the coarse dimensions and low operating current densities encountered in these structures. Ag and Cu coplanar waveguides on silicon substrates were designed, fabricated and tested. Silver waveguides showed a 2–3 dB/cm improvement in attenuation over copper devices at 40 GHz.     

Ku波段高增益8通道T/R组件设计与实现

利用低温共烧陶瓷(LTCC)高集成化设计优势,设计并实现了一款Ku波段高增益8通道T/R组件。该组件通过双向放大器的合理运用,有效提高了组件的收发增益,同时利用液态金属材料的特性,将硅铝壳体与铝合金散热齿进行有机结合,大大提高了组件在连续波发射工作模式下的热量传导能力,保证了组件小体积下工作的可靠性。最终设计实现的Ku波段高增益8通道T/R组件,体积仅84 mm×48 mm×6 mm,质量约60 g,发射功率增益大于45 dB,发射输出功率大于1 W,接收增益大于29 dB,接收噪声系数小于3.5 dB。该组件8个通道收发性能一致性好,性能稳定,具有良好的工程实用价值。     

用于TFT-LCD驱动芯片的内置DRAM设计

TFT-LCD驱动芯片中需要较大容量的内置存储器,相对于静态存储电路而言,动态存储电路节省了芯片的面积,有利于芯片成本的降低.文章讨论了用于TFT-LCD驱动芯片内置DRAM的分块设计方法,结合芯片物理特点将其分为左右对称两块.采用改进的3-T结构DRAM存储阵列,省去了伪存储单元,节省了面积,降低了功耗.优化了DRAM的刷新电路,省略了判断信号与RAS和CAS先后顺序的仲裁电路.结合芯片本身的特点设计了行、列译码电路.对于芯片的仿真,采用了模拟验证和形式验证相结合的前端设计验证方法,同时又采用了结构化抽取寄生参数和建立关键路径的后仿真.     

A new technology for high-power IC

The paper describes a new fabrication technology for a monolithic high-power linear IC. It is based on a novel process for controlling the epitaxial growth of single crystal regions and very fine polycrystalline regions on an IC substrate essentially in accordance with the specified mapping of the IC pattern. Polycrystalline regions are used in areas of isolation and collector lead paths which must be diffused deeply, and contribute to the most important characteristics required for the high-power IC, i.e., higher breakdown voltage and lower saturation resistance. A power capability far beyond any known in this field has been achieved. A typical example of the output power rating for an IC designed for use in a low-frequency SEPP-type power amplifier is 20-watts rms continuous service, and the total harmonic distortion content is less than 8 percent at 1 kHz at 40-volts source voltage.     

集成芯片的可测性设计技术

主要介绍了三种可测性设计（DFT）技术,分别是：扫描设计（Scan Design）、边界扫描设计（Boundary Scan Design）和内建自测试设计（BIST）。对于这三种设计技术,分别介绍了其原理和设计过程。     

柔性基板模块封装技术

针对柔性基板模块封装过程中存在的材料选择、叠层方式以及层间干涉等关键问题,提出了采用热应力分析进行材料筛选,通过3D结构叠层以及夹具隔离支撑措施,实现满足电磁兼容、热传导及振动要求的模块整体封装.这些方法和技术可用在适应性要求高的异形空间.     

A design technique for a 60 GHz-bandwidth distributed basebandamplifier IC module

A DC-60 GHz, 9 dB distributed amplifier IC module is fabricated with 0.15 μm InAlAs-InGaAs low-noise HEMTs with 155 GHz f_T and 234 GHz f_max. The device is mounted in a metal package with 1.8 mm coaxial cable signal interfaces. The package is specially designed using three-dimensional electromagnetic field analyses, resulting in very flat frequency characteristics of the module within 1.5 dB gain ripples over the entire bandwidth. A multichip module loaded with two amplifier ICs in cascade is also fabricated, and operates at a 17.5 dB gain from 60 kHz to 48 GHz. The 1 dB gain compression output power is about 5 dBm for both modules. The noise figure of the single-chip module is approximately 4 dB over a 10-40 GHz frequency range     

TFT-LCD驱动控制芯片内置SRAM的自测试设计

针对单片集成TFT-LCD驱动控制芯片内置SRAM的特点,提出了一种将内建自测试与机台测试相结合的SRAM测试方案.测试向量由机台提供,测试过程中启动内部自测试电路.在SRAM的读出寄存器和写入寄存器之间建立一条通路,测试向量通过这条通路在SRAM单元之间传递,形成了一个长的移位链,读出数据送给比较器检测.与传统自测试结构相比,该方案面积开销小,灵活性高.     

RFID中嵌入式EEPROM的超低功耗设计

基于SMIC 0．35μm嵌入式EEPROM工艺实现了一款256byte的超低功耗EEPROMIP核。典型情况下．读电流为40μA，页编程电流为250μA，特别适合RFID（Radio Frequency Identiffcation）标签芯片的应用。针对芯片中各种功耗的来源进行了详细的分析，并给出了相应的实现方法。     

PDP驱动器IC的最新技术动向

在TV市场中,正在迅速进行薄型化是众所周知的事实。相对于中小型TV采用LCD;在大型TV中,由于PDP(等离子体显示板)的画质性能、寿命,以及电耗的改善,不断巩固着稳固的地位。尤其是地面数字广播的开播诱发出TV换新的巨大需求,大型TV市场的扩大在意料之中,预料PDP的需要还将以空前的步伐增长。但就PDP的价格而言,并未便宜下来,还希望有相当大的降低,在决定其成本的主要构件中,不像通常谁都看得见的玻璃屏板,置于后面的半导体电路元件所占比重不可轻视。特别是由高压信号直接驱动屏板的众多驱动器IC,因其使用数量之多,可说是极为重要的…     

Constant-current circuit-biasing technology for GaAs FET IC

A new constant-current biasing technology has been proposed, analyzed, and applied to GaAs FET IC's using n-channel depletion-mode FET's. Current-mirror (CM) type current-sink (CS) circuits were proposed as a new building-block circuit. The monolithic prototype samples were fabricated, and the CM characteristics were observed experimentally. The CS currents were insensitive to the V_th-variation over 0.4 V, and the temperature coefficient became as small as -0.04%/°C. Moreover, this circuit was resistant to the sidegating effect. The circuit was successfully applied to a GaAs lightwave communication IC, and good stability against temperature variation was demonstrated     

New interconnection technology for enhanced module efficiency

In order to enhance solar modular efficiency, an innovative interconnection method for solar cells has been developed. The solar cells are two-dimensionally interconnected to a large-area, shingle-roof patterned solar cell array. Test samples were fabricated using silicon solar cells with conventional cell structures. Packing densities over 96% and module efficiencies of 17.3% and 13.4% (AM 1.5, 100 mW/cm² ) were obtained for single-crystalline and polycrystalline silicon solar cells, respectively     

IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors

Fault tolerant design is a technique emerging in Integrated Circuits (ICs) to deal with the increasing error susceptibility (Soft Errors, Single Event Upsets, (SEUs)) caused by e.g. alpha particles. A side effect of these methods is that they also compensate for manufacturing defects, thereby increasing the yield and lowering the production cost in certain conditions. In this paper, it is shown that increasing the IC area (by applying fault tolerant design techniques for SEUs) leads to a synergistic advantage under certain conditions: lower production costs because of a better yield. To guide designers in deciding when the fault tolerant techniques are beneficial, break-even points between fault tolerant and regular designs are presented as function of IC area, fault tolerant overhead and defect density.