High-speed NMOS circuits for ROM-accumulator and multiplier type digital filters

Using a standard 6 /spl mu/m NMOS silicon-gate process, circuit techniques are described for the full integration of high-speed ROM-accumulator and multiplier type digital filters. The ROM-accumulator structure is integrated using a new two-clock four-phase technique which can be used both for ROM and accumulator. An operating speed of 20 Mbits/s is measured. The circuit shows that an eighth-order filter on a 20 mm/SUP 2/ chip, dissipating only 400 mW at 10 Mbits/s is feasible. Using a 4-clock 4-phase technique a 4-bit serial-parallel multiplier is presented featuring 20 Mbits/s operation into a 15 pF load. Power dissipation is 7 mW/cell. Cell area is 0.2 mm/SUP 2/.     

Improving multiplier design by using improved column compressiontree and optimized final adder in CMOS technology

In this paper we discuss improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile. Different architectures of the column compressors and the use of carry propagate adders which take advantage of the speed of the carry signal are considered. The column compressors configuration is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival time of the signals originating from the multiplier tree. This results in more compact wiring and balanced delays yielding a faster multiplier     

Analog CMOS building blocks for custom and semicustom applications

Standard analog building blocks developed for use in custom and semicustom LSI and VLSI designs are described. The analog blocks are built using a digital CMOS process modified to include high-value resistors and voltage independent capacitors. Designs for operational amplifiers, programmable voltage sources, comparators, bandgap voltage references, unit resistors, capacitors, and n-p-n devices are discussed. Performance characteristics including unity-gain bandwidth, output drive, output impedance, and common mode range are reviewed. MOS noise data, subthreshold operation, and device matching are analyzed. Layout guidelines are proposed as well as applications and limitations of the analog building blocks.     

Clock multiplier using digital CMOS standard cells for high-speeddigital communication systems

The authors propose and evaluate the performance of a 2^N times clock multiplier that controls memory components for high-speed data communications. To improve the reliability of the circuit, a symmetric circuit structure is used, while to verify circuit operation by means of a simple method, an MVU estimator is found from simulation data. The proposed circuit can provide clock rates, which are usually required in the multiple phase shift keying (MPSK) or multiple quadrature amplitude modulation (MQAM) modulation schemes, of 2 to 2^N times that of the input clock     

Negabinary carry-look-ahead adder and fast multiplier

A carry-look-ahead negabinary adder is proposed in the letter. It is shown that these adders make the design of a fast negabinary multiplier feasible.     

A portable clock multiplier generator using digital CMOS standardcells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps     

MuDSPDEMO-demonstration package for multirate digital signalprocessing

This column describes an educational software package designed to support a graduate course on multirate digital signal processing. The program is implemented in MATLAB and uses a graphical user interface to integrate numeric computation and effective scientific visualization     

CMOS multiplier for grounded capacitors

A CMOS circuit suited particularly to magnifying the value of a grounded unit capacitor is presented. The multiplication factor is achieved through the gain of current mirrors and its maximum value is limited solely by power consumption constraints. Solutions are then developed to reduce power dissipation, to enable the detection of small unit capacitances, and to enlarge the operating frequency bandwidth     

A high-speed multiplier using a redundant binary adder tree

A 16-bit /spl times/ 16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described. This multiplier has been fabricated on an LSI chip using a standard n-E/D MOS process technology with a 2.7-/spl mu/m design rule. This multiplier is characterized by use of a binary tree of redundant binary adders. In the new algorithm, n-bit multiplication is performed in a time proportional to log/SUB 2/ n and the physical design of the multiplier is constructed of a regular cellular array. This new algorithm has been proposed by N. Takagi et al. (1982, 1983). The 16-bit/spl times/16-bit multiplier chip size is 5.8 /spl times/ 6.3 mm/SUP 2/ using the new layout for a binary adder tree. The chip contains about 10600 transistors, and the longest logic path includes 46 gates. The multiplication time was measured as 120 ns. It is estimated that a 32-bit /spl times/ 32-bit multiplication time is about 140 ns.     

A fast final adder for a 54-bit parallel multiplier for DSP application

A novel redundant binary-to-natural binary converter circuit is proposed which is used in the final addition stage of parallel multipliers. Use of this circuit in the final adder stage proves to be 17% faster than carry-look-ahead implementation. We used this algorithm in such a way that no redundant binary adder is required in compressing partial product rows. Only the natural 4:2 compressor circuits are used.     

A circuit implementation of a single-bit CMOS adder

In this article, a circuit implementation of a single-bit CMOS adder with enhanced performance is presented. The adder circuit consists of separate circuits operating in-parallel for obtaining the output sum and carry signals. The carry circuit signal is not used to form the sum signal. The sum signal circuit is a sequential connection of two XOR cells. The circuit operability is confirmed by the results of circuit simulation using Cadence Design Systems’ software.     

Reconfigurable pipelined 2-D convolvers for fast digital signalprocessing

In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal- and image-processing functions is an important part of every digital signal processor (DSP) developer's toolset. In general, such a library provides high-level interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work. Complex signal transformations then become function calls, e.g., C-callable functions. Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP's, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming. Therefore, the exploration of the 2-D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors. Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed. In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated. However, the proposed concept is not limited to a particular processor     

Four-quadrant CMOS analogue multiplier for artificial neuralnetworks

A four-quadrant CMO analogue multiplier is presented. The proposed multiplier has large dynamic input range, good linearity and can provide either a differential output current or voltage. These properties make the multiplier very suitable for use in the implementation of artificial neural networks     

The Khoros software development environment for image and signalprocessing

Data flow visual language systems allow users to graphically create a block diagram of their applications and interactively control input, output, and system variables. Khoros is an integrated software development environment for information processing and visualization. It is particularly attractive for image processing because of its rich collection of tools for image and digital signal processing. This paper presents a general overview of Khoros with emphasis on its image processing and DSP tools. Various examples are presented and the future direction of Khoros is discussed.     

CMOS four-quadrant analogue multiplier for RF applications

A CMOS four-quadrant multiplier consisting of four MOS transistors operating in the saturation region is introduced. The circuit exploits the quadratic relation between the current and voltage of the MOS transistor in saturation. Simulation results show that, for a supply voltage of 1.2 V multiplication can be performed at a frequency of 1.8 GHz, achieving better performances than a recently proposed similar architecture     

Configurable logic for digital communications: some signalprocessing perspectives

For the past two decades software programmable digital signal processors and ASICs have provided hardware solutions for signal processing system designers. A new option has become available: field programmable gate arrays. FPGA-based DSP platforms allow the designer to realize a data path that exactly matches the required processing, while at the same time maintaining the flexibility of a software approach. This article presents an overview of some FPGA DSP applications. Several filter designs are presented, and the use of CORDIC arithmetic for constructing an FPGA carrier recovery loop is outlined. In addition to presenting design examples that can be realized using present-generation devices and tools, we take a brief look at how the dynamic reconfiguration aspect of certain FPGAs could be exploited in future-generation communication technologies