共查询到20条相似文献,搜索用时 31 毫秒
1.
Kernhof J. Selzer M. Beunder M.A. Hoefflinger B. Laquai B. Schindler I. 《Solid-State Circuits, IEEE Journal of》1990,25(2):396-402
In a semicustom design environment with unified transistor geometries, logic circuit optimization is achieved using an efficient physical circuit implementation. In particular, the semicustom realization of domino logic is demonstrated with a standard-cell and a multiplier design which are used to support the implementation of such a dynamic logic design style on a gate forest, which has a higher n count than p count. The mixture of complementary and dynamic logic allows the designer to improve the critical-path delay and to reduce the size of the layout. The domino standard-cell architecture supports multiple-output configurations and additional internal precharge. The operation time for a mixed static/dynamic multiplier is approximately 30% higher than that of the static version based on a carry select adder. This difference mainly affects the critical delay of the sign-extension path of the parallel adder array 相似文献
2.
Fadavi-Ardekani J. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1993,1(2):120-125
The architecture of a design method for an M -bit by N -bit Booth encoded parallel multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is explained. The final step of adding two N ±M -1-bit numbers is done by an optimal carry select adder stage. The algorithm for optimal partitioning of the N ±M -1-bit adder is also presented 相似文献
3.
An improved systolic architecture for two-dimensional infinite-impulse response (IIR) and finite-impulse-response (FIR) digital filters is presented. Comparisons with recently published work are made. When compared with the architecture of M.A. Sid-Ahmed (1989), a substantial reduction in the number of delay elements is observed. This reduction is of the order of 102 for a 2-D IIR filter and equals N +1 for an N th-order 2-D FIR filter. The clock period has been made independent of the order of the filter. The speed-up factor is the maximum achievable and is independent of the filter order. Comparison with the work of S. Sunder et al. (1990) shows an improvement in the latency of the systolic array, which has been reduced from 1 to 0. A reduction of N +1 delay elements has been achieved for the FIR filter. An error analysis for the architecture is made 相似文献
4.
The authors believe that special-purpose architectures for digital signal processing (DSP) real-time applications will use closely coupled processing elements as array processor modules to implement the various portions of the new algorithms, and several such modules will cooperate in a pipelined manner to implement complete algorithms. Such an architecture, based upon systolic modules, for the MUSIC algorithm is presented. The architecture is suitable for VLSI implementation. The throughput of the pipelined approach is O (N ), whereas the sequential approach is O (N 3) 相似文献
5.
A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Hardware cost is minimized by sharing resistor strings, bias circuitry and clock generation circuitry over the array. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismatches across the array. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology is used. An experimental chip was implemented in 1-μm CMOS and 8-b resolution at a sample rate of 85 megasamples per second (MS/s) was obtained. Signal-to-noise plus distortion (S /(N +D )) was 41 dB for an input sinusoid of 40 MHz 相似文献
6.
An architecture for high-performance/small-area multipliers for usein digital filtering applications
Kwentus A.Y. Hing-Tsun Hung Willson A.N. Jr. 《Solid-State Circuits, IEEE Journal of》1994,29(2):117-121
A multiplier architecture and encoding scheme well suited for programmable digital filtering applications is described. The multiplier's partial product recoding scheme uses only simple multiplexers and takes advantage of a RAM that stores filter coefficients. We use an optimized 20-transistor full-adder cell in the carry-save adder array, and a carry-select vector-merge adder produces the final output. An integrated circuit comprising an ll-b by ll-b multiplier using second-order recoding has been fabricated in 2-μm CMOS technology. It operates in 22 ns and its core occupies 1.53 mm2. Also, an ll-b by 16-b multiplier using third-order recoding has been fabricated through MOSIS in 1.2-μm CMOS technology. Its core occupies 0.9 mm2 and it operates in 19 ns 相似文献
7.
A custom FM stereo decoder IC which uses switched-capacitor and linear filters, linear MOS and bipolar circuitry, and digital MOS circuitry to eliminate the requirements for accurate external components and external adjustments is described. The IC includes a combined analog/digital VCO and PLL, a switched-capacitor sine-wave multiplier, and a switched-capacitor pilot detector and cancellation stage. An output S /N ratio greater than 80 dB and output distortion less than 0.1% have been achieved. The part is 26000 mils2 and is implemented in a 3 μm n-well CMOS process containing poly-to-poly capacitors, n-p-n's, and ion-implanted poly resistors 相似文献
8.
Modular, area-efficient VLSI architectures for computing the arithmetic Fourier transform (AFT) are proposed. By suitable design of PEs and I/O sequencing, nonuniform data dependencies in the AFT computation which require nonequidistant inputs and assignment of Mobius function values are resolved. The proposed design employs 2N +1 PEs to compute 2N +1 Fourier coefficients. Each PE has an adder and a fixed amount of local storage, and one PE has a multiplier. I/O with the host is performed using a fixed number of channels. This results in simple PE organization, compared with those needed in known DFT/FFT architectures. The design achieves O (N ) speedup. It uses significantly fewer PEs than designs in the literature and supports real-time applications by allowing continuous sequential input. It can be extended to achieve linear speedup in a fixed size array with 2p +1 PEs, 1⩽p ⩽N 相似文献
9.
A second-order multibit ΣΔ (sigma-delta) analog-to-digital converter (ADC) with a 4-b internal quantizer is described. It uses a simple and fast digital correction scheme. A correlated-double-sampling (CDS) fully differential integrator was used, in which the op amp needed only a low slew rate and moderate bandwidth for a sampling rate of 5.25 MHz. A second-order modulator was fabricated in the standard MOSIS p-well 2-μm CMOS process. The excellent measured linearity and high S /(N +D ) ratio (95 dB with an oversampling ratio of only 128) of the corrected converter verified the practical advantages of the proposed architecture 相似文献
10.
Sul C. McLeod R.D. Pedrycz W. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1993,1(2):224-228
A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree is generated by successive formation of hierarchical modules. For N processing elements (PEs) on the wafer, reconfiguration time is O (log N ). The propagation delay is bounded by Θ(log N ) and is independent of the number of faulty PEs. Faults in the switching network as well as faulty processing elements are tolerated 相似文献
11.
Abu-Khater I.S. Bellaouar A. Elmasry M.I. 《Solid-State Circuits, IEEE Journal of》1996,31(10):1535-1546
In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-μm CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16×16)-b multiplier using the Booth algorithm, a (6×6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6×6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS 相似文献
12.
This paper presents a novel variable-latency multiplier architecture, suitable for implementation as a self-timed multiplier core or as a fully synchronous multicycle multiplier core. The architecture combines a second-order Booth algorithm with a split carry save array pipelined organization, incorporating multiple row skipping and completion-predicting carry-select dual adder. The paper reports the architecture and logic design, CMOS circuit design and performance evaluation. In 0.35 μm CMOS, the expected sustainable cycle time for a 32-bit synchronous implementation is 2.25 ns. Instruction level simulations estimate 54% single-cycle and 46% two-cycle operations in SPEC95 execution. Using the same CMOS process, the 32-bit asynchronous implementation is expected to reach an average 1.76 ns throughput and 3.48 ns latency in SPEC95 execution 相似文献
13.
A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8×8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz 相似文献
14.
Gin Yee Sechen C. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2000,8(4):425-430
Clock-delayed (CD) domino is a self-timed dynamic logic family developed to provide single-rail gates with inverting or noninverting outputs. CD domino is a complete logic family and is as easy to design with as static CMOS circuits from a logic design and synthesis perspective. Design tools developed for static CMOS are used as part of a methodology for automating the design of CD domino circuits. The methodology and CD domino's characteristics are demonstrated in the design of a 32-b carry look-ahead adder. The adder was fabricated with MOSIS's 0.8-μm CMOS process with scalable CMOS design rules that allow a 1.0-μm drawn gate length. Measurements of the adder show a worst case addition of 2.1 ns. The CD domino adder is 1.6× faster than a dual-rail domino adder designed with the same cell library and technology 相似文献
15.
Ohkubo N. Suzuki M. Shinbo T. Yamanaka T. Shimizu A. Sasaki K. Nakagome Y. 《Solid-State Circuits, IEEE Journal of》1995,30(3):251-257
A 54×54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 μm CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54×54-b multiplier is 3.77×3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply 相似文献
16.
A pipelined multiplier-accumulator using a high-speed, low-powerstatic and dynamic full adder design
Shyh-Jye Jou Chang-Yu Chen En-Chung Yang Chau-Chin Su 《Solid-State Circuits, IEEE Journal of》1997,32(1):114-118
This paper proposes a new pipelined full-adder circuit structure for the implementation of pipelined arithmetic modules. With both static and dynamic structures, it has the advantages of high operational speed, smallest transistor count, and the low power/speed ratio. The adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In this MAC, a special pipelined structure is designed to reduce the latency. The MAC is fabricated in a 0.8-μm single-poly-double-metal CMOS process. The post-layout simulation shows that the pipelined 1-b full adder can work up to 350 MHz with a 3 V power supply. The whole MAC chip that contains 4200 transistors is measured to operate a 125 MHz using 3.3 V power supply 相似文献
17.
纳米电子器件RTD与CMOS电路结合,这种新型电路不仅保持了CMOS动态电路的所有优点,而且在工作速度、功耗、集成度以及电路噪声免疫性方面都得到了不同程度的改善和提高。文中对数字电路中比较典型的可编程逻辑门、全加器电路进行了设计与模拟,并在此基础上对4×4阵列纳米流水线乘法器进行了结构设计。同时讨论了在目前硅基RTD器件较低的PVCR值情况下实现相应电路的可行性。 相似文献
18.
Jun Rim Choi Lak Hyun Jang Seong Wook Jung Jin Ho Choi 《Solid-State Circuits, IEEE Journal of》1997,32(3):468-476
A compact 10-b, 288-tap finite impulse response (FIR) filter is designed by adopting structured architecture that employs an optimized partial product tree compression method. The new scheme is based on the addition of equally weighted partial products resulted from 288 multiplications of the filter coefficients and the inputs. The 288 multiplication and 287 addition operations are decomposed to add 1440 partial products and the sign extension operations are manipulated independently to ensure the operation at 72 MHz, the internal clock frequency generated by the integrated phase-locked loop (PLL) clock multiplier. In addition to the optimized transmission gate full adder, modified carry save compression circuits such as 4:2 and 5:5:2 compressors are used to perform decomposed partial product addition. This structured approach enables cascade design that requires more than 288-tap FIR filtering. The completed 288-tap FIR fitter core occupies 5.36×7.29 mm2 of silicon area that consists of 371732 transistors in 0.6-μm triple-metal CMOS technology, and it consumes only 0.8 W of average power at 3.3 V 相似文献
19.
20.
Suzuki K. Yamashina M. Nakayama T. Izumikawa M. Nomura M. Igura H. Heiuchi H. Goto J. Inoue T. Koseki Y. Abiko H. Okabe E. One A. Yano Y. Yamada H. 《Solid-State Circuits, IEEE Journal of》1994,29(12):1464-1473
A 500 MHz, 32 bit RISC microprocessor has been experimentally developed using an 8-stage pipelined architecture and high-speed circuits, including a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns register file, a double-stage binary look-ahead carry (BLC) adder circuit, and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly developed circuit-integrating techniques include a stacked power-line structure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable termination resistors, a small-skew clock distribution method, and a clock synchronization circuit which provides small-skew clock among LSI chips. About 200000 transistors are integrated into a 7.90 mm×8.84 mm die area with 0.4 μm CMOS fabrication technology. Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage 相似文献