Design and characterization of submicron BiCMOS compatiblehigh-voltage NMOS and PMOS devices

This paper investigates the feasibility of integrating high-voltage blocking capability into a state-of-the-art submicron BiCMOS process using existing processing steps. High-voltage MOS devices fully compatible with an existing 5 V, 0.8 μm BiCMOS process have been designed and studied through extensive two-dimensional (2-D) process and device simulations. The device layout parameters in proposed high-voltage NMOS (HV-NMOS) and high-voltage PMOS (HV-PMOS) devices are optimized to achieve highest performance possible in terms of breakdown voltage and specific on-resistance with the constraints of full process compatibility. The optimized HV-NMOS and HV-PMOS devices using minimized unit-cell pitches of 7.8 and 7.3 μm achieved breakdown voltages of 129 V and specific on-resistances of 0.9 and 11.5 mn cm², respectively. Due to their full compatibility with the existing process the high-voltage MOS devices presented in this paper can be implemented without increasing manufacturing cost. The integration of the high-voltage blocking capability into the submicron BiCMOS process can expand its application field to include high-voltage input and output (I/O) functions on the same chip with high-speed analog and high-density digital signal processing circuitry     

A study of NMOS behavior under ESD stress: simulation and characterization

A full-scale simulation-aided ESD design methodology was used to design a group of NMOS ESD protection units. Silicon results match the simulation data quite well. Both simulation and measurement data show good ESD performance uniformity across NMOS poly finger length and finger number in ladder structures in a large range. Optimal layout pattern for ladder structures was obtained with the aid of simulation.     

Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25 μm CMOS technology

This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25 μm/5 V CMOS technology. Breakdown voltages of 20 V for n-channel device with a specific on resistance of 1.06 mΩ cm² and −20 V for p-channel device with a specific on resistance of 2.83 mΩ cm² have been achieved without any modification of existing standard CMOS process.     

小尺寸NMOS和PMOS SEU敏感性对比分析

使用软件模拟的方法对NMOS和PMOS的单粒子翻转(SEU)特性进行份真,通过在阱内外碰撞的两种情况下对小尺寸NMOS和PMOS的SEU敏感性进行对比可知,对于深亚微米阶段相同工艺的器件,在阱外碰撞时,NMOS一定比PMOS对SEU敏感;但对于阱内碰撞,NMOS和PMOS对SEU的敏感性要视具体情况而定.     

A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications

In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm². Post layout simulations show better performance compared with other reported techniques.     

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Since hot carrier effects can pose a potential limit to device scaling, hot-carrier-induced device degradation has been one of the major concerns in modern device technology. Currently, there is a great interest in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation. Also, low-temperature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS devices. Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degradation were done at room temperature and little has been done at low temperature. In this work, hot-carrier-induced device degradation is characterized from 77 K to room temperature for both NMOS and PMOS devices with the emphasis on low-temperature behavior of hot carrier degradation. For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature. It is also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature. For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Hot carrier stressing on PMOS devices at low temperature appears to induce hole generation and substantial interface state creation upon annealing unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures     

Punchthrough behavior in short channel NMOS and PMOS 6H-siliconcarbide transistors at elevated temperatures

An experimental investigation of the effects of high temperature on short channel NMOS and PMOS transistors in 6H-SiC is reported. Punchthrough characteristics are presented and examined at room temperature and 300°C. The punchthrough current increases dramatically for scaled PMOS transistors at high temperature while the temperature dependence of electrical characteristics for short channel NMOS is small. The results presented in this paper also provide insight into design criteria for short channel silicon carbide (SiC) devices intended for operation at elevated temperatures     

Benchmark of power packaging for DC/DC and AC/DC converters

This paper presents the first reported final results of a benchmarking project "StatPEP" which investigated the Status of Power Electronic Packaging used in commercial DC/DC and AC/DC switch mode power supplies. The methodology of the project is first described. Some of the salient results of a comprehensive benchmarking of DC/DC converters (rated power of 100 W) and AC/DC converters (rated power up to 576 W) are presented. Examples for figures-of-merit are presented. The results of the investigation are presented in a generic form, which does not identify individual products. A comparison of the performance of the units shows that the measured power density of the AC/DC units is approximately 10% that of the DC/DC while the thermal density based on footprint is 50%. Also the switching frequency of the AC/DC is 50% that of the DC/DC. Some of the reasons for these differences are discussed     

CMOS RF amplifier and mixer circuits utilizing complementary Characteristics of parallel combined NMOS and PMOS devices

Design and chip fabrication results for complementary RF circuit topologies that utilize the complementary RF characteristics of both NMOS and PMOS field-effect-transistor devices combined in parallel way are reported, which can inherently provide single-ended differential signal-processing capability, requiring neither baluns, nor differential signal generating/combining circuits. The proposed complementary CMOS parallel push-pull (CCPP) amplifier gives an order of magnitude improvement in IP/sub 2/ than an NMOS common-source amplifier and single-balanced CCPP resistive mixer, which functions effectively as a double-balanced one, provides more than an order of magnitude better linearity in IP/sub 2/, and similar order of magnitude better local oscillator (LO)-IF and LO-RF isolations than NMOS counterparts.     

Quasi current resonant DC link AC/AC converter

A new quasi current resonant DC link (QCRDCL) topology has been developed in this paper. Although prototype current resonant DC link topologies for AC/AC power conversion have had such problems as irregular high current peaks, uncontrollable pulse width, etc., this new topology enables the AC/AC conversion system to have the properties wherein the current peak is limited and the pulse width is adjustable. The system begins to assume an adjustable-width flat-topped current shape, whereby the system becomes particularly suitable for high power application. With control of the pulse width a very fine load current regulation can be obtained. In this system, an open loop PWM control has been adopted and almost the same quality of output waveforms as the conventional current source inverter has been achieved     

Mechanisms for hot-carrier-induced degradation inreoxidized-nitrided-oxide n-MOSFET's under combined AC/DC stressing

Hot-carrier-induced degradation behavior of reoxidized-nitrided-oxide (RNO) n-MOSFETs under combined AC/DC stressing was extensively studied and compared with conventional-oxide (OX) MOSFETs. A degradation mechanism is proposed in which trapped holes in stressed gate oxide are neutralized by an ensuing hot-electron injection, leaving lots of neutral electron traps in the gate oxide, with no significant generation of interface states. The degradation behavior of threshold voltage, subthreshold gate-voltage swing, and charge-pumping current during a series of AC/DC stressing supports this proposed mechanism. RNO device degradation during AC stressing arises mainly from the charge trapping in gate oxide rather than the generation of interface states due to the hardening of the Si-SiO₂ interface by nitridation/reoxidation steps     

Fretting in copper-to-copper contacts under AC and DC currentconditions

The effect of fretting on the contact resistance behavior of copper-to-copper wire-plate combinations under AC and DC current carrying conditions was investigated. The fretting conditions were as follows: frequency 1 Hz, slip amplitude 100 μm and load 400 g (4N). The current level in both AC and DC conditions was 50 mA. In addition to contact resistance measurements, SEM and EDX were used to examine the surface damage in the fretted contact zones. The results indicate that the overall contact resistance behavior of copper-to-copper wire-plate couples subjected to the same fretting conditions but under AC and DC currents was practically the same. The characteristic feature of the samples under AC current conditions is a pronounced distortion of the waveforms of the contact voltage. The results of SEM surface analysis of the contact zones indicates that the surface damage resulting from fretting under AC current conditions was different from that under DC current conditions     

基于DC/AC逆变电源交/直流侧传导EMI噪声机理建模

针对DC/AC逆变电源交/直流侧的传导EMI噪声机理特性,提出直流侧噪声源内阻抗建模方法,理论分析了不同工作模式下交流侧的传导EMI噪声共模/差模噪声传输机理模型和控制参数影响下的噪声建模方法,最后对DC/AC逆变器直流侧噪声源内阻抗进行了提取实验,利用仿真分析控制参数对交流侧传导EMI噪声的影响,该研究内容为DC/AC逆变电源传导EMI问题的解决提供了一定的理论与实践参考。     

Lifetime prediction for PMOS and NMOS devices based on a degradation model for ate- ias- tress

The degradation behaviour of PMOS and NMOS devices after Gate-Bias-stress (GB-stress) was investigated. The observed saturation current decrease of p-channel devices after GB-stress is due to field-induced generation of interface states. The decrease of saturation current of n-channel devices after GB-stress can be interpreted by trapped electrons, which are tunneling from the substrate into the gate oxide. Based on the experimental lifetime results at stress conditions extrapolation models were formulated which allow the determination of lifetime after GB-stress both for n- and p-channel devices at real operation conditions.     

Hot-carrier-induced MOSFET degradation under AC stress

The effects of gate and drain voltage waveforms on the hot-carrier-induced MOSFET degradation are studied. Drain votage transients have little effect on the degradation rate. Only the falling edge of the gate pulse in the presence of a high drain voltage enhances the degradation rate. For devices in typical inverter circuits, dc stress results together with the substrate current waveform can predict the degradation rate under ac stress for a wide range of rise and delay times.     

Advanced Integrated Bidirectional AC/DC and DC/DC Converter for Plug-In Hybrid Electric Vehicles

Hybrid electric vehicle (HEV) technology provides an effective solution for achieving higher fuel economy, better performance, and lower emissions, compared with conventional vehicles. Plug-in HEVs (PHEVs) are HEVs with plug-in capabilities and provide a more all-electric range; hence, PHEVs improve fuel economy and reduce emissions even more. PHEVs have a battery pack of high energy density and can run solely on electric power for a given range. The battery pack can be recharged by a neighborhood outlet. In this paper, a novel integrated bidirectional AC/DC charger and DC/DC converter (henceforth, the integrated converter) for PHEVs and hybrid/plug-in-hybrid conversions is proposed. The integrated converter is able to function as an AC/DC battery charger and to transfer electrical energy between the battery pack and the high-voltage bus of the electric traction system. It is shown that the integrated converter has a reduced number of high-current inductors and current transducers and has provided fault-current tolerance in PHEV conversion.     

Synthesis of input-rectifierless AC/DC converters

This paper discusses the basic construction procedure and topological possibilities of creating AC/DC converters out of simple DC/DC converters. It is shown that two separately controlled DC/DC converters are sufficient for producing a regulated DC output and shaping the input current, from an AC voltage source, without the need for input rectifiers. Some design constraints are discussed, emanating from the limitation of the conversion ratios that can be achieved by particular DC/DC converters. Selected topologies are verified experimentally. This kind of rectifierless converter find applications in airborne power supplies where zero-crossing distortions are significant because of the inevitable phase-lead effect of the input rectifier bridge.     

Single-cycle resonant converters: a new group of quasi-resonantconverters suitable for high-performance DC/DC and AC/AC conversionapplications

A novel resonant switch and a family of zero-current and zero-voltage mixed-mode switching quasi-resonant converters (QRCs) called single-cycle resonant converters (SCRCs) are proposed to improve the performance of the conventional QRCs. The SCRCs, which include two active switches operated with zero-current switching (ZCS) and zero-voltage switching (ZVS), respectively, show very simple operation and ease of control and analysis, and they overcome the limited load range characteristics of the conventional ZCS QRCs. The SCRCs can be applied even for a high-frequency AC chopper by replacing unidirectional switches with bidirectional ones. Steady-state operation and characteristics of the buck-type SCRCs are analyzed and compared with those of the buck-type full-wave QRC (FW-QRC). Experimental results at a a 200 kHz, 1 kW level are shown to verify the operational principle and characteristics