Microwave noise performance of AlGaN-GaN HEMTs with small DC power dissipation

We report low microwave noise performance of discrete AlGaN-GaN HEMTs at DC power dissipation comparable to that of GaAs-based low-noise FETs. At 1-V source-drain (SD) bias and DC power dissipation of 97 mW/mm, minimum noise figures (NF/sub min/) of 0.75 dB at 10 GHz and 1.5 dB at 20 GHz were achieved, respectively. A device breakdown voltage of 40 V was observed. Both the low microwave noise performance at small DC power level and high breakdown voltage was obtained with a shorter SD spacing of 1.5 /spl mu/m in 0.15-/spl mu/m gate length GaN HEMTs. By comparison, NF/sub min/ with 2 /spl mu/m SD spacing was 0.2 dB greater at 10 GHz.     

Temperature Effect on $Ku$-Band Current-Reused Common-Gate LNA in 0.13-$mu{hbox{m}}$ CMOS Technology

This paper presents the temperature effect on a Ku-band NMOS common-gate low-noise amplifier (CG-LNA). The temperature characteristics of an NMOS transistor and spiral inductors are obtained over the temperature range from 253 to 393 K. These results show that the optimal bias condition minimizes the transconductance and drain current temperature variations. Based on these results, a current-reused CG-LNA with good temperature performance is designed. At ambient temperatures, the CG-LNA has a measured power gain of 10.3 dB and a noise figure (NF) of 4.3 dB at 15.2 GHz, while consuming 4.5 mA from a 1.3-V power supply. When the temperature varies from 253 to 393 K, the CG-LNA has a power gain variation of 3 dB, NF variation of 2 dB , and dc power consumption variation of 11.9%. This paper is the first to report the temperature effect on Ku-band CG-LNAs.     

0.2μm GaAs PHEMT3.1~10.6GHz宽带低噪声放大器设计

采用OMMIC公司提供的0.2μm GaAs PHEMT工艺(fT=60 GHz)设计并实现了一种适用于宽带无线通信系统接收前端的低噪声放大器。在3.1~10.6 GHz的频带内测试结果如下:最高增益为13 dB;增益波动<2dB;输入回波损耗S11<-11 dB;输出回波损耗S22<-16 dB;噪声系数NF<3.9 dB。5 V电源供电,功耗为120mW。芯片面积为0.5 mm×0.9 mm。与近期公开发表的宽带低噪声放大器测试结果相比较,本电路结构具有芯片面积小、工作带宽大、噪声系数低的优点。     

100-GHz cooled amplifier residual PM and AM noise measurements, noise figure, and jitter calculations

We report the first definitive PM and AM noise measurements at 100 GHz of indium phosphide (InP) amplifiers operating at 5 K, 77 K, and room temperature. Amplifier gain ranged from +7 to +30 dB, depending on input RF power levels and operating bias current and gate voltages. The measurement system, calibration procedure, and amplifier configuration are described along with strategies for reducing the measurement system noise floor in order to accurately make these measurements. We compute amplifier noise figure with an ideal oscillator signal applied and, based on the PM noise measurements, obtain NF=0.8 dB, or a noise temperature of 59 K. Measurement uncertainty is estimated at /spl plusmn/0.3 dB. Results show that the use of the amplifier with an ideal 100-GHz reference oscillator would set a lower limit on rms clock jitter of 44.2 fs in a 20-ps sampling interval if the power into the amplifier were -31.6 dBm. For comparison, clock jitter is 16 fs with a commercial room-temperature amplifier operating in saturation with an input power of -6.4 dBm.     

A sub-mW 2.9-dB noise figure Inductor-less low noise amplifier for wireless sensor network applications

In this paper, a low power differential inductor-less Common Gate Low Noise Amplifier (CG-LNA) is presented for Wireless Sensor Network (WSN) applications. New Shunt feedback is employed with noise cancellation and Dual Capacitive Cross Coupling (DCCC) techniques to improve the performance of common gate structures in terms of gain, Noise Figure (NF) and power consumption. The shunt feedback path boosts the input conductance of the LNA in current reuse scheme. Both shunt feedback and current reuse bring power dissipation down considerably. In addition, the positive feedback is utilized to cancel the thermal noise of the input transistor. The proposed LNA is designed and simulated in 0.18 µm TSMC CMOS technology. Post layout Simulation results indicate a voltage gain of 16.5 dB with −3 dB bandwidth of 100 MHz–3 GHz. Also third order Input Intercept Point (IIP3) is equal to + 1 dBm. The minimum NF is 2.8 dB and the value of NF at 2.4 GHz is 2.9 dB. S11 is better than −13 dB in whole frequency range. The core LNA consumes 985 µW from a 1.8 V DC voltage supply.     

Proposal of low-noise amplifier utilizing resonant tunnelingtransistors

A low-noise amplifier utilizing the negative input resistance of resonant tunneling transistors (RTT's) is proposed. Expected features of the RTT amplifiers are: 1) negligible effect of noise sources at the output, owing to their large power gain; 2) flat variation of noise figure (NF) versus frequency, due to white spectra of noise sources at the input; and 3) a high maximum oscillation frequency (f_max) (over several 100 GHz), Based on simulated DC characteristics, over 500 GHz f_max and 0.3 dB NF at 100 GHz are predicted for optimized AlGaAs/GaAs/AlGaAs resonant tunneling diodes (RTD's). In an RTT formed by coupling an FET to an optimized RTD, 0.55 dB minimum noise figure and 26 dB associated gain are predicted at 100 GHz. Also, a 1/w² spectrum of the input noise resistance is predicted at low frequencies     

宽带W波段低噪声放大器的设计与制作

基于未来低功耗毫米波接收前端的应用,采用InP HEMT工艺实现了一种W波段宽带低噪声放大器.该放大器采用边缘耦合线用于级间的隔离,扇形短截线用于RF旁路,偏置网络采用薄膜电阻和扇形短截线以保持放大器的稳定性.采用3 mm噪声测试系统对单片进行在片测试.测试结果显示在80～102 GHz,噪声系数小于5 dB,相关增益大于19 dB.五级电路的栅、漏分别连在一起方便使用,芯片面积3.6 mm×1.7 mm,功耗30 mW.     

12~18 GHz GaAs MMIC低噪声放大器设计

采用GaAs工艺设计了一个12~18 GHz毫米波单片集成电路(MMIC)低噪声放大器(LNA)。采用三级单电源供电放大结构,运用最小噪声匹配设计、共轭匹配技术和负反馈结构,同时满足了噪声系数、增益平坦度和输出功率等要求。仿真表明：在12~18 GHz的工作频带内,噪声系数为1.15~1.41 dB,增益为27.9~29.1 dB,输出1 dB压缩点达到15 dBm,输入、输出电压驻波比(VSWR)系数小于1.72。     

A Cool, Sub-0.2 dB Noise Figure GaN HEMT Power Amplifier With 2-Watt Output Power

This paper reports on a S-, C-band low-noise power amplifier (LNPA) which achieves a sub-0.2 dB noise figure (NF) over a multi-octave band and a saturated output power (Psat) of 2 W at a cool temperature of -30degC . The GaN MMIC is based on a 0.2 mum AlGaN/GaN-SiC HEMT technology with an f_T ~ 75 GHz. At a cool temperature of -30degC and a power bias of 15 V-400 mA, the MMIC achieves 0.25-0.45 dB average NF over a 2-8 GHz band and a linear P_1dB of 32.8 dBm ( ~ 2 W) with 25% power-added efficiency (PAE). At a medium bias of 12 V-200 mA, the amplifier achieves 0.1-0.2 dB average NF across the same band and a P_1dB of 32.2 dBm (1.66 W) with 35% PAE. The corresponding saturated output power is greater than 2 W. At a low noise bias of 5 V-200 mA, a remarkable 0.05-0.15 dB average NF is achieved with a P_1dB > 24 dBm and PAE ~ 33%. These results are believed to be the lowest NF ever reported for a multi-octave fully matched MMIC amplifier capable of > 2 W of output power.     

Capacitor Cross-Coupled Fully-differential CMOS Folded Cascode LNAs with Ultra Low Power Consumption

This paper proposes a fully-differential folded cascode low noise amplifier (LNA) for 5.5 GHz receiver in 180 nm CMOS technology. By improving folded cascode with an additional inductance connected at the gate of CG stage to cancel parasitic capacitance and then employing capacitor cross-coupled technique as a negative feedback in the proposed LNA, the performance of the LNA can be improved significantly in terms of gain (S21) and noise figure (NF) compared with the conventional fold cascode LNA. Furthermore, the DC power consumption of the LNA is further reduced with forward body bias topology. The measurements show the proposed LNA achieves 16.5 dB power gain, a NF of 1.53 dB, good input/output matching with the S11 and S22 are less than \(-\) 15 dB. And the operating voltage is only 0.5 V with ultra-low power consumption of 0.89 mW.     

一种新的射频CMOS混频器结构

提出了一种低电压高增益CMOS下变频混频器的新结构.这个结构避免了堆叠晶体管,因此可以在低电压下工作.在LO信号的频率为1.452GHz,RF信号频率为1.45GHz的情况下,仿真结果表明:混频器的增益为15dB,ⅡP3为-4.5dBm,NF为17dB,最大瞬态功耗为9.3mW,直流功耗为9.2mW.并对该混频器的噪声特性和线性度进行了分析.     

2～12 GHz CMOS超宽带低噪声放大器设计

提出了一种基于双反馈电流复用结构的新型CMOS超宽带(UWB)低噪声放大器(LNA),放大器工作在2～12 GHz的超宽带频段,详细分析了输入输出匹配、增益和噪声系数的性能。设计采用TSMC 0.18μm RF CMOS工艺,在1.4 V工作电压下,放大器的直流功耗约为13mW(包括缓冲级)。仿真结果表明,在2～12 GHz频带范围内,功率增益为15.6±1.4 dB,输入、输出回波损耗分别低于-10.4和-11.5 dB,噪声系数(NF)低于3 dB(最小值为1.96 dB),三阶交调点IIP3为-12 dBm,芯片版图面积约为712μm×614μm。     

（英）CMOS毫米波低功耗超宽带共栅低噪声放大器

本文陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA)。该LNA用标准90-nm RF CMOS工艺实现并具有如下特征：在28.5到39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27到42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2 dB,平均NF在27-42 GHz频段内为5.1 dB;S₁₁在整个测试频段内小于-11 dB。40 GHz处输入三阶交调点(IIP3)的测试值为 2 dBm。整个电路的直流功耗为5.3 mW。包括焊盘在内的芯片面积为0.58*0.48 mm2_。     

A High Gain and Low Supply Voltage LNA for the Direct Conversion Application With 4-KV HBM ESD Protection in 90-nm RF CMOS

A 2.4-GHz low noise amplifier (LNA) for the direct conversion application with high power gain, low supply voltage and plusmn4 KV human body model (HBM) electrostatic discharge (ESD) protection level implemented by a 90-nm RF CMOS technology is demonstrated. At 12.9 mA of current consumption with a supply voltage of 1.0 V, the LNA delivers a power gain of 21.9 dB and the noise figure (NF) of 3.2 dB, while maintaining the input and output return losses below -11 dB and -18.3 dB, respectively. The power gain and NF are only 0.2 dB lower and 0.64 dB higher than those of LNA without ESD protection     

Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

A CMOS RF (radio frequency) front-end for digital radio broadcasting applications is presented that contains a wideband LNA, I/Q-mixers and VGAs, supporting other various wireless communication standards in the ultra-wide frequency band from 200 kHz to 2 GHz as well. Improvement of the NF (noise figure) and IP3 (third-order intermodulation distortion) is attained without significant degradation of other performances like voltage gain and power consumption. The NF is minimized by noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The dB-in-linear VGA (variable gain amplifier) exploits a single PMOS to achieve exponential gain control. The circuit is fabricated in 0.18-μm CMOS technology. The S_(11) of the RF front-end is lower than -11.4 dB over the whole band of 200 kHz-2 GHz. The variable gain range is 12-42 dB at 0.25 GHz and 4-36 dB at 2 GHz. The DSB NF at maximum gain is 3.1-6.1 dB. The IIP3 at middle gain is -4.7 to 0.2 dBm. It consumes a DC power of only 36 mW at 1.8 V supply.     

S波段低功耗单片集成低噪声放大器

报道了S波段低功耗单片前置放大器的研制结果。该单片电路采用1μm×600μmGaAsE－MESFET、源反馈电感以及具有平面结构的集总参数LC匹配元件。用离子注入技术保证电路具有较好的一致世。在2．3GHz频率点测试结果如下：Ga＝80dB，NF＝2．06dB／2．0V，2．2mA；Ga＝10．5dB，NF＝2．25dB／3．0V，4．8mA。测试结果与设计目标基本一致，这一结果说明在低功耗应用选取GaAsE－MESFET作有原器件是可行的。     

32-GHz cryogenically cooled HEMT low-noise amplifiers

The cryogenic noise temperature performances of a two-stage and a three-stage 32-GHz HEMT (high-electron-mobility transistor) amplifier were evaluated. The amplifiers utilize quarter-micrometer conventional AlGaAs/GaAs HEMT devices, hybrid matching input and output microstrip circuits, and a cryogenically stable DC biasing network. The noise temperature measurements were performed in the frequency range of 31 to 33 GHz over a physical temperature range of 300 to 12 K. Across the measurement band, the amplifiers displayed a broadband response, and the noise temperature was observed to decrease by a factor of ten in cooling from 300 to 15 K. The lowest noise temperature measured for the two-stage amplifier at 32 GHz was 35 K with an associated gain of 16.5 dB, while for the three-stage amplifier it was 39 K with an associated gain of 26 dB. It was further observed that both amplifiers were insensitive to light     

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.     

A 400 MHz Low Noise Amplifier at Cryogenic Temperature for Superconductor Filter System

A cryogenic low noise amplifier （LNA） using Agilent high electron mobility transistor （HEMT） for 380 MHzto 480 MHz is designed and fabricated, and the excellent cryogenic performance in superconducting receiver front-end for communication system is achieved. A special input impedance matching topology is implemented to provide low noise figure （NF） and good input matching in this cryogenic LNA design. The measurement results show that the NF is within 0.25 dB from the minimum NF of a single transistor, the power gain is above 20 dB, the flatness is within 1 dB, and the maximum input return loss is lower than -20 dB in bandwidth.     

L 波段宽带低温低噪声放大器的设计与测量*

高电子迁移率晶体管(HEMT)的小信号等效电路低温模型是研制致冷低噪声放大器(LNA)与研究晶 体管微波特性的基础。该文通过测量HEMT 器件在低温环境下直流参数与散射参数(S 参数),构建了包含噪声参 量的小信号等效电路,并据此设计了一款覆盖L 波段的宽带低温低噪声放大器(LNA),工作频率1 ~2GHz,相对带宽 达到66. 7%。在常温下放大器功率增益大于28dB,噪声温度小于39K;当环境温度制冷至11K 时,噪声温度为1. 9 ~3. 1K,输入输出端口的回波损耗S11 和S22 均优于-10dB,1dB 压缩点输出功率为9. 2dBm,功耗仅为54mW。