A computational study of thin-body, double-gate, Schottky barrier MOSFETs

Nanoscale Schottky barrier MOSFETs (SBFETs) are explored by solving the two-dimensional Poisson equation self-consistently with a quantum transport equation. The results show that for SBFETs; with positive, effective metal-semiconductor barrier heights, the on-current is limited by tunneling through a barrier at the source. If, however, a negative metal-semiconductor barrier height could be achieved, on-current of SBFETs would approach that of a ballistic MOSFET. The reason is that the gate voltage would then modulate a thermionic barrier rather than a tunneling barrier, a process similar to ballistic MOSFETs and one that delivers more current.     

Performance Comparison of Graphene Nanoribbon FETs With Schottky Contacts and Doped Reservoirs

We present an atomistic 3-D simulation study of the performance of graphene-nanoribbon (GNR) Schottky-barrier field-effect transistors (SBFETs) and transistors with doped reservoirs (MOSFETs) by means of the self-consistent solution of the Poisson and SchrÖdinger equations within the nonequilibrium Green's function (NEGF) formalism. Ideal MOSFETs show slightly better electrical performance for both digital and terahertz applications. The impact of nonidealities on device performance has been investigated, taking into account the presence of single vacancy, edge roughness, and ionized impurities along the channel. In general, MOSFETs show more robust characteristics than SBFETs. Edge roughness and single-vacancy defect largely affect the performance of both device types.      

Ultrathin gate oxide CMOS with nondoped selective epitaxial Sichannel layer

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO₂-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated     

On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L/sub min//spl ap/4.5(t/sub Si/+(/spl epsiv//sub Si///spl epsiv//sub I/)t/sub I/), where t/sub Si/ is the silicon thickness, and /spl epsiv//sub I/ and t/sub I/ are the permittivity and thickness of the gate insulator. With t/sub Si/ limited to /spl ges/ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L/sub min/=20 nm is projected for oxides, and L/sub min/=10 nm for high-/spl kappa/ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.     

Sub-60-nm quasi-planar FinFETs fabricated using a simplifiedprocess

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V_g-V _t=V_d=1 V. The electrical gate oxide thickness in these devices is 21 Å, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness     

Analysis of leakage currents and impact on off-state powerconsumption for CMOS technology in the 100-nm regime

Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications     

Reliability issues in submicron MOSFETs with oxynitride gate dielectrics

A review of critical reliability issues in submicron MOSFETs with oxynitride gate dielectrics is presented. We have focussed our attention on: substrate and gate currents in short channel MOSFETs, hot carrier induced MOSFET degradation under DC and AC stress, gate-induced drain leakage current and its enhancement due to stress, neutral trap generation due to electrical stress and degradation of analog MOSFET parameters. We have also discussed the problems of radiation induced neutral trap generation and boron penetration through the gate dielectric, which arise due to the advanced processing techniques utilized in submicron MOSFET processing. It is concluded that the use of oxynitride gate dielectrics can effectively solve several reliability issues encountered in scaling down MOSFETs to submicron dimensions.     

Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges

As the channel length rapidly shrinks down to the nanoscale regime, the multiple gate MOSFETs structures have been considered as potential candidates for a CMOS device scaling due to its good short-channel-effects (SCEs) immunity. Therefore, in this work we investigate the scaling capability of Double Gate (DG) and Gate All Around (GAA) MOSFETs using an analytical analysis of the two dimensional Poisson equation in which the hot-carrier induced interface charge effects have been considered. Basing on this analysis, we have found that the degradation becomes more important when the channel length gets shorter, and the minimum surface potential position is affected by the hot-carrier induced localized interface charge density. Using this analysis, we have studied the scaling limits of DG and GAA MOSFETs and compared their performances including the hot-carrier effects. Our obtained results showed that the analytical analysis is in close agreement with the 2-D numerical simulation over a wide range of devices parameters. The proposed analytical approach may provide a theoretical basis and physical insights for multiple gate MOSFETs design including the hot-carrier degradation effects.     

注F MOSFET漏电流的辐照和退火行为

分析研究了不同偏置辐照和退火条件下，Ｐ沟和Ｎ沟ＭＯＳＦＥＴ的漏电流变化特性。结果表明，ＰＭＯＳＦＥＴ的辐射感生漏电流与栅偏压的依赖关系类似于辐照陷阱电荷的栅偏压关系；注ＦＰＭＯＳＦＥＴ的辐射感生漏电流增长小于未注Ｆ样品；ＮＭＯＳＦＥＴ辐照后漏电流随时间的退火呈现下降、重新增长和趋于饱和的特征，注Ｆ对退人过程中漏电流的重新增长有一定的抑制作用。     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.     

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N⁺ polysilicon gate device with highly doped Si layer, an asymmetrical P⁺/N⁺ polysilicon gate device with low doped Si layer and a mid-gap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P⁺/N⁺ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET.     

Strained Si/SiGe MOS technology: Improving gate dielectric integrity

Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance gains in short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to the lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed.     

Effects of the post nitridation anneal temperature on performances of the nano MOSFET with ultra-thin (<2.5 nm) plasma nitrided gate dielectric

A post nitridation annealing (PNA) is used to improve performances of the metal oxide semiconductor field effect transistor (MOSFETs) with nano scale channel and pulsed radio frequency decoupled plasma nitrided ultra-thin (<50 Å) gate dielectric. Effects of the PNA temperature on the gate leakage and the device performances are investigated in details. For a n-type MOSFET, as the PNA temperature rises from 1000 to 1050 °C, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements in performance are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. Most of all, the high temperature PNA does not degrade the gate oxide integrity.     

Hole mobility enhancement and Si cap optimization in nanoscale strained Si1−xGex PMOSFETs

P-channel metal-oxide-semiconductor field-effect-transistors (PMOSFETs) with a Si_1−xGe_x/Si heterostructure channel were fabricated. Peak mobility enhancement of about 41% in Si_1−xGe_x channel PMOSFETs was observed compared to Si channel PMOSFETs. Drive current enhancement of about 17% was achieved for 70 nm channel length (L_G) Si_0.9Ge_0.1 PMOSFETs with SiO₂ gate dielectric. This shows the impact of increased hole mobility even for ultra-small geometry of MOSFETs and modest Ge mole fractions. Comparable short channel effects were achieved for the buried channel Si_1−xGe_x devices with L_G=70 nm, by Si cap optimization, compared to the Si channel devices. Drive current enhancement without significant short channel effects (SCE) and leakage current degradation was observed in this work.     

Three-dimensional analytical subthreshold models for bulk MOSFETs

Three-dimensional device-physics-based analytical models are developed for subthreshold conduction in uniformly doped small geometry (i.e., simultaneously short channel and narrow width) bulk MOSFETs, for various isolation schemes. Inverse-narrow width effects, where the threshold voltage decreases with decreasing channel width, are predicted by the model for trench isolated MOSFETs. For LOGOS isolated MOSFETs, conventional narrow width effects, where the threshold voltage increases due to decreasing channel width, are predicted. The narrow width effects are found to be comparable to the short channel effects in the absence of significant applied drain biases. However, for larger drain biases, the short channel effects outweigh the narrow width effects due to the weaker potential perturbation at the device width edges compared to the drain end. Unlike the threshold voltage, the subthreshold swing of the device is found to increase with reduced device dimensions regardless of the isolation scheme since both conventional and inverse narrow width effects result in weaker control of the surface potential by the gate     

Limit of gate oxide thickness scaling in MOSFETs due to apparentthreshold voltage fluctuation induced by tunnel leakage current

We report on a new roadblock which will limit the gate oxide thickness scaling of MOSFETs. It is found that statistical distribution of direct tunnel leakage current through 1.2 to 2.8 nm thick gate oxides induces significant fluctuations in the threshold voltage and transconductance when the gate oxide tunnel resistance becomes comparable to gate poly-Si resistance. By calculating the measured tunnel current based on multiple scattering theory, it is shown that the device characteristics fluctuations will be problematic when the gate oxide thickness is scaled down to less than 1 nm     

A novel hetero-junction Tunnel-FET using Semiconducting silicide–Silicon contact and its scalability

A new type of silicon-based Tunneling FET (TFET) using semiconducting silicide Mg₂Si/Si hetero-junction as source-channel structure is proposed and the device simulation has been presented. With narrow bandgap of silicide and the conduction and valence band discontinuous at the hetero-junction, larger drain current and smaller subthreshold swing than those of Si homo-junction TFET can be obtained. Structural optimization study reveals that low Si channel impurity concentration and the alignment of the gate electrode edge to the hetero-junction lead to better performance of the TFET. Scaling of the gate length increases the off-state leakage current, however, the drain voltage (V_d) reduction in accordance with the gate scaling suppresses the phenomenon, keeping its high drivability.     

A Three-Dimensional Simulation Study of the Performance of Carbon Nanotube Field-Effect Transistors With Doped Reservoirs and Realistic Geometry

This paper simulates the expected device performance and scaling perspectives of carbon nanotube (CNT) field-effect transistors with doped source and drain extensions. The simulations are based on the self-consistent solution of the three-dimensional Poisson–SchrÖdinger equation with open boundary conditions, within the nonequilibrium Green's function formalism, where arbitrary gate geometry and device architecture can be considered. The investigation of short channel effects for different gate configurations and geometry parameters shows that double-gate devices offer quasi-ideal subthreshold slope and drain-induced barrier lowering without extremely thin gate dielectrics. Exploration of devices with parallel CNTs shows that on currents per unit width can be significantly larger than the silicon counterpart, while high-frequency performance is very promising.     

The Geometry Effect of Contact Etch Stop Layer Impact on Device Performance and Reliability for 90-nm SOI nMOSFETs

The thickness effects of a high-tensile-stress contact etch stop layer (HS CESL) and the impact of layout geometry (length of diffusion (LOD) and gate width) on the mobility enhancement of lang100rang/(100) 90-nm silicon-on-insulator (SOI) n-channel MOSFETs (nMOSFETs) were studied in detail. Additionally, the low-frequency characteristics were inspected using low-frequency noise investigation for floating body (FB)-SOI nMOSFETs. Experimental results show that a device with a 1100-Aring HS CESL has worse characteristics and hot-carrier-induced degradations than a device with a 700-Aring; HS CESL due to larger stress-induced defects. The lower plateau of the Lorentzian noise spectrum that was observed from the input-referred voltage noise S_vg implies a higher leakage current for devices with a 1100-Aring HS CESL. On the other hand, it was found that devices with narrow gate widths have higher driving capacity for a larger fringing electric field and higher compressive stress in the direction perpendicular to the channel. Because of the more serious impact of compressive stress in a direction parallel to the channel, a device with shorter LOD experiences more serious performance degradation     

High-current snapback characteristics of MOSFETs

The high-current snapback characteristics of MOSFETs with different channel lengths and widths, gate oxide thicknesses, and substrate dopings were studied to determine their effectiveness in electrostatic discharge stress protection. Filamentary conduction was not observed for currents up to 7 mA/μm of channel width for a pulsewidth of 500 ns. MOSFETs with shorter channel lengths require lower voltages to sustain the same current, independent of gate oxide thickness. Increasing the substrate doping does not necessarily reduce the high current voltage. These trends can be explained using a simple lateral n-p-n bipolar transistor snapback model