In Situ Comparison of Si/High- $kappa$ and $hbox{Si}/ hbox{SiO}_{2}$ Channel Properties in SOI MOSFETs

Detailed measurements of front- and back-channel characteristics in advanced SOI MOSFETs (ultrathin Si film, high-kappa, metal gate, and selective epitaxy of source/drain) are used to reveal and compare the transport properties at the corresponding Si/high- kappa (HfO₂ or HfSiON) and Si/SiO₂ interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage, and subthreshold swing. As compared with Si/SiO₂, the low-field mobility is lower at the Si/high-kappa interface and increases less rapidly at low temperature, reflecting additional scattering mechanisms governed by high-kappa and neutral defects.     

High Mobility Strained Ge pMOSFETs With High-κ/Metal Gate

Compressively strained Ge long channel ring-type pMOSFETs with high-kappa Si/SiO₂/HfO₂/TiN gate stacks are fabricated on Si_0.2Ge_0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm²/ Vldrs and up to a four times enhancement over the Si/SiO₂ universal curve are observed. Parasitic conduction within the Si-cap layers degrades the mobility at large vertical fields, although up to a 2.5 times enhancement over universal remains at a field of 0.9 MV/cm.     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

Flicker-Noise Improvement in 100-nm $L_{g} hbox{Si}_{0.50}hbox{Ge}_{0.50}$ Strained Quantum-Well Transistors Using Ultrathin Si Cap Layer

This letter presents a record low flicker-noise spectral density in biaxial compressively strained p-channel 100-nm L_gSi_0.50Ge_0.50 quantum-well FETs (QWFETs) with ultrathin Si (~2 nm) barrier layer and 1-nm EOT hafnium silicate gate dielectric. The normalized power spectral density of I_d fluctuations (S_Id/I_d ²) in Si_0.50Ge_0.50 QWFETs exhibits significant improvement by ten times over surface channel unstrained Si pMOSFETs at high V_g due to strong confinement of holes within the high-mobility QW and strong quantization in the ultrathin Si barrier layer enabled by low-thermal-budget device processing. The noise behavior in strained QW devices is found to evolve from being correlated mobility fluctuation dominated across most of V_g range to being Hooge mobility fluctuation dominated at very high V_g.     

Impacts of additive uniaxial strain on hole mobility in bulk Si and strained-Si p-MOSFETs

Hole mobility changes under uniaxial and combinational stress in different directions are characterized and analyzed by applying additive mechanical uniaxial stress to bulk Si and SiGe-virtual-substrate-induced strained-Si (s-Si) p-MOSFETs (metal-oxide-semiconductor field-effect transistors) along <110> and <100> channel directions. In bulk Si, a mobility enhancement peak is found under uniaxial compressive strain in the low vertical field. The combination of (100) direction uniaxial tensile strain and substrate-induced biaxial tensile strain provides a higher mobility relative to the (110) direction, opposite to the situation in bulk Si. But the combinational strain experiences a gain loss at high field, which means that uniaxial compressive strain may still be a better choice. The mobility enhancement of SiGe-induced strained p-MOSFETs along the (110) direction under additive uniaxial tension is explained by the competition between biaxial and shear stress.     

Efficiency Improvement of GaN-Based LEDs With $ hbox{SiO}_{2}$ Microrod Array and Textured Sidewalls

High-performance nitride-based light-emitting diodes (LEDs) grown with SiO₂ microrod array have been demonstrated. The light output power of LEDs with SiO₂ microrod array was 9.03% higher than conventional LEDs at the injection current of 20 mA. The improvement contributed to the enhancement of the light extraction efficiency, and epitaxial GaN film quality improved by direct heteroepitaxial lateral overgrowth with SiO₂ microrod array. The light output power could be further enhanced by about 18.36% as compared with the conventional LEDs when adopting the textured sidewall surface which use buffered oxide etch to remove SiO₂ microrod arrays and use NaOH to etch the sidewall again into an inverted pyramid shape. After the texturing process, the LEDs show higher electroluminescence intensity and broader far-field pattern. Furthermore, the LEDs with SiO₂ microrod array and additional wet-etching process will not affect the electrical property.     

Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- $k$ FETs

This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivability of pFETs with the solid-phase epitaxial (SPE) extension junction, but reducing the thermal budget deteriorates the poly-gate depletion and the electron mobility. Metal gate, however, prevents the depletion problem and leads to higher drain currents and better threshold-voltage (V_TH) roll-offs when processed with tilted extension implantation combined with SPE + FLA than when processed with untilted extension implantation combined with spike rapid thermal annealing. Reducing the thermal budget is also effective in obtaining low V_TH values in p-metal/HfSiON gate because of the reduced vacancy formation. Moreover, cluster-boron implantation for pFETs has superiority over monomer-boron implantation with Ge postamorphous implantation in terms of V_TH roll-offs and I_on-I_off's if FLA is used as activation. The superior electrical characteristics of full-metal- gate HfSiON transistors whose gate length is less than 50 nm, which are fabricated by using the FLA process, are demonstrated.     

Double-Gate Tunnel FET With High-κ Gate Dielectric

In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO₂, while the subthreshold slope for fixed values of V_g remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an I_on/I_off ratio of more than 2 times 10¹¹ is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.     

Effects of Channel Width on Stress Enhancement for Damascene-Gate nFETs With Top-Cut Tensile-Stress Liner

This letter provides channel-stress behavior results induced by a local strain technique which consists of the process combination of a damascene-gate and top-cut tensile stress SiN liner for narrow channel-width nFETs using 3-D stress simulations and demonstrations. The dummy-gate removal, which is an intrinsic step in the damascene-gate process, is found to enhance tensile channel stress along the gate length at the edge of the channel beside the shallow trench isolation. In consequence of a mobility boost due to the high tensile stress, drain-current enhancement in the saturation is achieved for the damascene-gate nFETs with the narrow channel width and short gate length.     

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Transient charging and discharging of border traps in the dual-layer HfO₂/SiO₂ high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO₂ high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10^-8- 10^-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling     

Oxynitridation using radical-oxygen and -nitrogen for high-performance and highly reliable n/pFETs

We report the importance of oxynitridation using radical-oxygen and -nitrogen to form a low-leakage and highly reliable 1.6-nm SiON gate-dielectric without performance degradation in n/pFETs. It was found that oxidation using radical-oxygen forms high-density 1.6-nm SiO/sub 2/, which is ten times more reliable than low-density SiO/sub 2/ formed by oxygen-ions in n/pFETs and is suitable for the base layer of nitridation. Nitrifying SiO/sub 2/ using radical-nitrogen facilitates surface nitridation of SiO/sub 2/, maintains an ideal SiON-Si substrate interface, and reduces the gate leakage current. The 1.6-nm SiON formed by radical-oxygen and -nitrogen produces comparable drivability in n/pFETs, has one and half orders of magnitude less gate leakage in nFETs, one order of magnitude less gate leakage in pFETs, and is ten times more reliable in n/pFETs than 1.6-nm SiO/sub 2/ formed by radical-oxygen.     

Performance and hot-carrier reliability of 100 nm channel lengthjet vapor deposited Si3N4 MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si₃N₄ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO₂ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si₃N₄ barrier (2.1 eV) is lower than the Si-SiO₂ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO₂ MOSFETs     

单轴附加应变对体硅及应变硅p-MOSFETs空穴迁移率的影响

Hole mobility changes under uniaxial and combinational stress in different directions are characterized and analyzed by applying additive mechanical uniaxial stress to bulk Si and SiGe-virtual-substrate-induced strained- Si（s-Si）p-MOSFETs（metal-oxide-semiconductor field-effect transistors）along 110 and 100 channel directions. In bulk Si,a mobility enhancement peak is found under uniaxial compressive strain in the low vertical field.The combination of 100 direction uniaxial tensile strain and substrate-induced biaxial tensile strain provides a higher mobility relative to the 110 direction,opposite to the situation in bulk Si.But the combinational strain experiences a gain loss at high field,which means that uniaxial compressive strain may still be a better choice.The mobility enhancement of SiGe-induced strained p-MOSFETs along the 110 direction under additive uniaxial tension is explained by the competition between biaxial and shear stress.     

High-κ Metal Gate MOSFETs: Impact of Extrinsic Process Condition on the Gate-Stack Quality—A Mobility Study

The effects of source/drain activation thermal budget and premetallization degas conditions on interfacial regrowth, carrier mobility, and defect densities are examined for SiO₂/HfO₂/TaN stacks. We observe a correlation between the mobility degradation and the interfacial re-growth possible with the thermal budget employed. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-kappa bulk, as detected by both pulsed current-voltage and charge-pumping measurements. Two junction activation processes have been applied: a conventional process (peak temperature of 1000 degC spike for t=1 s) and a Solid Phase Epitaxial Re-growth (SPER) (peak temperature of 650 degC for t=60 s). For 1000 degC spike-annealed films, where the highest SiO₂/IL defect density is observed, the consequent mobility degradation is explained by a transition region between HfO₂ and the IL which increases for high-temperature processing     

<100>沟道方向对高迁移率双轴应变硅p-MOSFET的作用

双轴应变技术被证实是一种能同时提高电子和空穴迁移率的颇有前景的方法;<100>沟道方向能有效地提升空穴迁移率.研究了在双轴应变和<100>沟道方向的共同作用下的空穴迁移率.双轴应变通过外延生长弛豫SiGe缓冲层来引入,其中,弛豫SiGe缓冲层作为外延底板,对淀积在其上的硅帽层形成拉伸应力.沟道方向的改变通过在版图上45°旋转器件来实现.这种旋转使得沟道方向在(001)表面硅片上从<110>晶向变成了<100>晶向.对比同是<110>沟道的应变硅pMOS和体硅pMOS,迁移率增益达到了130%;此外,在相同的应变硅pMOS中,沟道方向从<110>到(100)的改变使空穴迁移率最大值提升了30%.讨论和分析了这种双轴应变和沟道方向改变的共同作用下迁移率增强的机理.     

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Newly proposed mobility-booster technologies are demonstrated for metal/high- $k$ gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/$ hbox{HfO}_{2}$ gate stacks with $T_{rm inv} = hbox{1.4} hbox{nm}$ on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using $hbox{HfSi}_{x}/hbox{HfO}_{2}$ gate stacks with $T_{rm inv} = hbox{1.4} hbox{nm}$. High-performance n- and pFETs are achieved with $I_{rm on} = hbox{1300}$ and 1000 $muhbox{A}/muhbox{m} hbox{at} I_{rm off} = hbox{100} hbox{nA}/mu hbox{m}$, $V_{rm dd} = hbox{1.0} hbox{V}$, and a gate length of 40 nm, respectively.      

Transport model in n++-poly/SiOx/SiO2/p-sub MOS capacitors for low-voltage nonvolatile memoryapplications

The origin of enhanced injection in n⁺⁺-poly/SiO_x /SiO₂/p-sub MOS capacitors under accumulation is investigated. Starting from experimental evidences as the structural homogeneity of the off-stochiometric oxide and the temperature dependence of current in n⁺⁺-poly/SiO_x/p-sub capacitors, we developed a new transport model. In this picture, transport consists on the Poole-Frenkel and multistep tunneling of the SiO_x barrier and the Fowler-Nordheim (FN) tunnel of the SiO ₂ barrier, the latter definitely limiting the current flowing through the MOS. The model explains how the presence of two barriers and an accelerating electric field in the SiO_x gives rise to the injection enhancement, respect to the case of a single conventional n ⁺⁺-poly/SiO₂ barrier. In fact, after the trap-assisted tunnel of the first barrier, the electron arrives at the SiO_x/SiO₂ interface with an excess energy furnished by the electric field. There, it sees an FN barrier lower than in the conventional case. Experiment and model calculations are in excellent agreement     

Germanium MOSFETs With CeO2/HfO2/ TiN Gate Stacks

Long-channel Ge pMOSFETs and nMOSFETs were fabricated with high-kappa CeO₂/HfO₂/TiN gate stacks. CeO₂ was found to provide effective passivation of the Ge surface, with low diode surface leakage currents. The pMOSFETs showed a large I _ON/I_OFF ratio of 10⁶, a subthreshold slope of 107 mV/dec, and a peak mobility of approximately 90 cm² /Vmiddots at 0.25 MV/cm. The nMOSFET performance was compromised by poor junction formation and demonstrated a peak mobility of only ~3 cm²/Vmiddots but did show an encouraging I_ON/I _OFF ratio of 10⁵ and a subthreshold slope of 85 mV/dec     

Dielectric breakdown mechanism of thin-SiO2 studied bythe post-breakdown resistance statistics

The dielectric breakdown mechanism of SiO₂ has been discussed on the basis of the experimental results of the post-breakdown resistance (R_bd) distribution. We have noticed for the first time that R_bd of SiO₂ in MOS devices is strongly related to the SiO₂ breakdown characteristics such as the polarity dependence or the oxide field dependence of Q_bd. In this paper, we discuss the dielectric breakdown mechanism of SiO₂ from the viewpoint of the statistical correlation between the R _bd distribution, the Q_bd. distribution, and the emission energy just at the SiO₂ breakdown, by changing the stress polarity, stress field, and the oxide thickness. For complete dielectric breakdown, it has been clarified that the R_bd distribution under the substrate electron injection is clearly different from that under the gate electron injection. We have also found that, irrespective of the stress current density, the gate oxide thickness and the stressing polarity, R_bd can be uniquely expressed by the energy dissipation at the occurrence of dielectric breakdown of SiO₂ for the complete breakdown. Furthermore, it has been clarified that R_bd does not depend on the energy dissipation at the occurrence of quasidielectric breakdown     

Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon–Carbon Source/Drain Regions

We report the demonstration of a novel strained silicon-on-insulator N-MOSFET featuring silicon-carbon (Si_1-yC_y) source and drain (S/D) regions, tantalum nitride metal gate, and hafnium-aluminum oxide high-k gate dielectric. Due to the lattice mismatch between Si_0.99C_0.01 S/D stressors and Si, a lateral tensile strain is induced in the transistor channel, leading to substantial electron mobility enhancement. At a fixed OFF-state leakage of 100 nA/mum, the Sii-j/C_1-yC_y S/D N-MOSFET having a width of 4.7 mum achieves a drive current Josat enhancement of 16% over a control N-MOSFET. This iDsat enhancement, which is primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate length LG due to an increased strain level in the transistor channel as the Si_1-yC_y S/D stressors are placed in closer proximity. Slightly improved series resistance with Si_1-yC_y S/D regions in a strained N-MOSFET accounted for approximately 2% I_Dsat gain. In addition, a reduction of device width is found to reduce the drive current enhancement of the N-MOSFETs due to the presence of a transverse compressive strain in the transistor channel induced by the isolation regions.