具有预加重功能的LVDS驱动电路

文章提出了LVDS预加重功能的驱动输出电路，这种预加重功能能够解决信号在长距离传输时所遇到的干扰问题。在这里介绍了两种可实现方法：用电阻改变电流和用双流源提供电流的方法，电阻法是利用并联电路使电阻减小电流增大的方法实现预加重的．双流源法是通过控制为电路提供预加重电流的那一部分电流源的开启和关闭的方法来实现预加重的。并采用0．25μmCMOS工艺对以上这两种电路方案进行了仿真，而且得到的仿真波形基本一致。     

一种低电压高频率采用自举电路的BiCMOS驱动电路

本文给出一种适用于低电压、高开关频率升压型DC—DC转换器的BiCMOS驱动电路。该驱动电路采用自举升压技术，它的工作电压最低可达1．5V，在负载电容为60pF条件下，工作频率高达5MHz。文章详细的介绍了此驱动电路设计思想，并且给出最终设计电路。电路基于Samsung AHP615 BiCMOS工艺设计，经Hspice仿真验证达到设计目标。     

适用于无源超高频RFID标签的高效率整流电路

基于动态阈值补偿技术,提出了一种适用于无源超高频RFID标签的高效率整流电路。该整流电路可以根据MOS管的工作状态对MOS管阈值电压进行动态补偿,使得MOS管同时具有低的导通电压和反向泄漏电流,从而实现高的功率转换效率。采用该整流电路的无源超高频RFID标签芯片在0.18 μm CMOS工艺下设计实现。测试结果表明,在驱动80 kΩ负载时,整流电路的功率转换效率最高可达53.7%。相比于传统整流电路,转换效率提高了约20％。     

一种适于低压高频DC-DC的自举BiCMOS驱动电路

本文给出一种适用于低电压高开关频率升压型DC-DC转换器的BiCMOS驱动电路。该驱动电路采用自举升压技术，工作电压最低可达1．5V，在负载电容为60pF条件下，工作频率高达5MHz。文章详细的介绍了此驱动电路的设计思想，并且给出了最终设计电路。     

一种片上集成低压高精度电流检测电路

提出了一种应用于电流模PWM DC-DC转换器的片上集成电流检测电路.它利用检测电阻和检测晶体管的结合,实现电感电流的检测;同时,在I-V转换电路中,运用结构简单的电流镜连接的共栅放大器实现反馈控制.在10～600 mA电感电流范围内,都可以得到高精度的检测电流,最小检测误差为0.04%.该电路在VTHN=0.735 V、|VTHP|=0.941 V的0.5 μm 1P2M CMOS工艺条件下,电路最低工作电压为1.5 V.     

一种适用于Boost电路的自适应斜坡补偿电路

设计了一种适用于峰值电流模式Boost电路的自适应斜坡补偿电路。电路通过动态检测Boost电路的输入输出电压,产生随Boost电路开关控制信号占空比变化的斜坡电压,实现补偿斜坡斜率的最优化。由于本设计采用了高精度减法器,斜坡补偿精度得到提高,在消除次谐波振荡、提升Boost电路稳定性的同时,将补偿对Boost电路的负面影响最小化,保证了Boost电路的带载能力和动态响应速度。采用SMIC 0.18μm CMOS工艺完成电路设计和版图绘制,并进行了后仿验证,结果显示,工作电压为3.3 V时,在不同工作条件下,随着开关占空比的变化,补偿斜率可以实现自适应调整,与理论最佳补偿斜率的误差范围仅为1.39%～2.33%。     

用于高侧开关的短路限流及保护电路

提出了一种用于高侧开关的短路限流及保护电路。电路采用二级保护的方式,当短路检测电压不为零且低于参考电压时,限制栅源电压,对电路限流;当短路检测电压高于参考电压时,则延时一段时间后关断功率管。芯片采用0.18μm 100 V BCD工艺流片。测试结果表明,在先工作后短路和先短路后工作两种情况下,功率管均处于正常工作状态。电路工作电压范围为4～80 V,短路延时时间约200μs,输出最大可持续电流可达80 A。     

半导体激光器混沌电路延时反馈控制方法

由于当前方法未能建立物理模型,导致混沌电路延时反馈控制复杂度和控制耗时增加,容错率下降,为此提出一种半导体激光器混沌电路延时反馈控制方法。组建半导体激光器混沌电路延时反馈条件下激光器电流激发混沌的物理模型,获取激光器非线性增益和线宽增强因子特性,并获取控制延迟可控条件。分析延迟量和反馈增益的解析关系,获取目标周期轨道控制参数的分岔图,以此为依据进行半导体激光器混沌电路延时反馈控制。实验结果表明,所提方法能够有效降低混沌电路延时反馈控制复杂度和控制耗时,大幅度提升容错率。     

Buck控制器中仿真电流模式控制电路的设计

论述了一种应用于Buck型开关电源控制器的仿真电流模式控制方法及相应的电路设计。该技术可用于新一代符合VRMIO标准的处理器供电电路。分析了传统电流模式控制在此应用条件下的局限性，提出了利用仿真电流模式实现Buck型开关电源的电流跟踪控制，并分析了电路的工作原理及设计实现。电路采用1．5μm BCD工艺实现。电路与系统的仿真结果表明，所预期的设计要求均已实现。     

利用关键测试点数据检修彩电各部分电路故障

（续上期）６伴音电路伴音电路包括伴音中频信号处理电路和伴音功放电路。６．１外部工作条件①伴音中频信号处理电路工作电压为１２V；②伴音功放电路有的为一组工作电压，其值在１６V以上，有的为两组工作电压，一个为９V，另一个为１６V以上，伴音控制电压要合适；③要引入正常的第二伴音信号；④对多制式机制式切换电压要正确。６．２关键测试点伴音电路的关键测试点有电源、伴音控制端、伴音制式切换末端、伴音功放中点电压。６．３各测试点能说明的问题①电源电压。其值与数据表中给出的值或图标值相比上下不超过１．５V，可视为正…     

A novel CMOS exponential transconductor operating in weak inversion

A novel CMOS exponential transconductor which employs only three NMOS transistors operating in weak inversion, is presented. The main advantage of the proposed circuit is its wide range of exponential behaviour, which reaches up to five decades of current range, and above 10 μA to an input voltage range of 800 mV. The physical realisation is achieved in two forms: in the first one, the circuit is implemented with discrete MOS transistor arrays by CD4007 series; in the second one, the circuit is fully integrated in a 0.5 μm CMOS standard process. Simulated and experimental results of the proposed exponential transconductor are also presented.     

GaAs数字电路输入输出接口电路的设计

本文讨论了ＧａＡｓ电路和ＳｉＥＣＬ电路的输入输出接口问题，对ＧａＡｓ电路中ＢＦＬ、ＤＣＦＬ、ＳＤＦＬ等电路形式的典型输入输出接口电路进行了分析研究，用电路模拟程序计算并给出了ＢＦＬ输入输出接口电路的转移特性曲线。     

Switched-current (SI) integrators with reduced effect of transistor mismatches

Switched-current (SI) circuits are widely used for analog sampled-data signal processing, due to their compatibility to the pure digital CMOS process. As their main building blocks are current mirrors, they suffer from the effects of MOS transistor parameters mismatch. In this paper, the Functional Block Diagram (FBD) of already known integrator circuits is modified in such a way that the number of required current mirrors is reduced. Thus, the behavior of the derived integrator topologies, with respect to the effect of MOS transistor parameters mismatch, is improved.A comparison is performed, concerning the performance of the proposed bilinear integrator circuits and those that are already introduced in the literature. For this purpose, a fifth-order Chebyshev lowpass SI filter transfer function was simulated. In the case of the proposed filter configurations, the obtained results show that their performance is improved in terms of the effects of MOS transistor parameters mismatch, DC power dissipation, and total required silicon area.     

A 1.5 V Current-Mode CMOS RMS-to-DC Converter

A very low voltage, current-mode CMOS RMS-to-DC converter is presented. It is fully designed using MOS Translinear techniques. More specifically, its main building blocks are a squarer/divider and a geometric-mean cell which are obtained by using simple second-order MOS Translinear loops in a folded configuration, leading to a very regular and compact implementation. A novel biasing technique is employed for such loops, allowing them to operate at supply voltages as low as 1.5 V. Experimental results for a prototype IC demonstrating the correct operation of the circuit are included.     

High-efficiency bipolar transconductors composed of hyperbolic function circuits with an intermediate voltage terminal and a triple-tail cell

Relatively high transconductance in bipolar devices contributes to the economy of power dissipation on analog integrated circuits. Recently, a high-speed transistor, such as the HBT attracts attention of researchers and developers in electronic communication industries and is expected to be applied to RF circuits. In this paper, high-efficiency bipolar transconductors are presented. The proposed circuits are composed of a hyperbolic function circuit with an intermediate voltage terminal and a triple-tail cell. The parameter values for linearisation are all integers. The values can be realised precisely. The linearity of the proposed transconductors is superior to the triple-tail cell. The linear input range is 1.5 times as wide as that of the conventional triple-tail cell. Nevertheless, the power dissipation is lower than the triple-tail cell. Further, sensitivity analysis shows that the proposed transconductors have lower sensitivity than the triple-tail cell. These properties are confirmed by SPICE simulation.     

A New Static Differential CMOS Logic with Superior Low Power Performance

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Delay optimization of the new circuits was performed. It showed the fully static behavior of these circuits. Their performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. Spice simulations using a 0.18 m technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.Muhammad E.S. Elrabaa received his B.Sc. degree in computer Engineering from Kuwait University, Kuwait in 1989, and his M.A.Sc. and PhD degrees in Electrical Engineering from the University of Waterloo, Waterloo, Canada, in 1991 and 1995, respectively. His graduate research dealt with Digital BiCMOS ICs and Low-Power circuit techniques. From 1995 till 1998, he worked as a senior circuit designer with Intel Corp., in Portland, Oregon, USA. He designed and developed low power digital circuits for Microprocessors. From 1998 till 2001 he was with the EE department, UAE University as an assistant professor. In 2001, he joined the computer Engineering department, KFUPM University. His current research interests include reconfigurable computing, low-power circuits, and communication circuits. He authored and co-authored several papers, a book and holds two US patents.     

Current-mode capacitorless integrators and differentiators for implementing emulators of fractional-order elements

Fractional-order capacitor and inductor emulator, implemented using current-mirrors as active elements and MOS transistors as capacitors, is introduced in this paper. Current-mirror integrators are used for performing the required current-mode integration/differentiation operation within the emulator stage. Also, a voltage-to-current converter, implemented using an Operational Transconductance Amplifier, is utilized for realizing the required interface of the input signal. Thus, the proposed emulator is simultaneously capacitorless and resistorless and offers the advantage of electronic tuning of the characteristics as well as of the type of the emulated fractional-order element. In addition, a modified version of the emulator that allows current excitation is proposed. The evaluation of the behavior of the proposed schemes has been performed using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 μm CMOS process.     

Switched-Current Wave Filters with Reduced Number of Current Inversions

Switched-current wave filters offer very simple structures, as their main building blocks are current mirrors. On the other hand, the achieved accuracy is mainly degraded due to the effect of MOS transistor parameters mismatch. In this Letter, new configurations of serial and parallel adaptors that are used in the simulation of inductances and capacitors of the LC ladder prototype are introduced. These have been implemented using an appropriate sharing of the delay that should be presented between the incident and reflected waves at a port of adaptor, and a 3-phase clocking scheme. The number of required current inversions and consequently the effect of mismatching are reduced in the proposed configurations.     

含源T形电路和含源Ⅱ形电路的等效变换

本文讨论了含源T形电路和含源Ⅱ形电路的等效变换,扩展了T形电路和Ⅱ形电路等效变换的内容。根据含独立电源二端口网络的特性方程,推导了含源T形电路和含源Ⅱ形电路等效变换的条件。含源T形电路和含源Ⅱ形电路等效变换的结果不具有唯一性,但可通过附加一些条件使变换结果唯一,本文给出了这些附加条件。并通过实例说明了推导结果的正确性。本文的分析对电路教学具有一定的价值,可供教学参考。     

Trading off circuit lines and gate costs in the synthesis of reversible logic

Motivated by its application in several emerging technologies, the synthesis of reversible circuits has received significant attention in the last decade. The proposed methods can roughly be divided into two different categories: (A) approaches ensuring the minimal number of circuit lines and (B) hierarchical approaches. Both synthesis paradigms have significant differences with respect to the gate costs and the number of lines in the resulting circuits. Hence, designers often have to deal with unsatisfactory results were either the gate costs or the number of circuit lines is disproportionately large.