基于嵌入式linux系统的NAND Flash设计与实现

本系统选用ARM9系列的S3C2440A芯片作为CPU。由于S3C2440A内部集成了NANDFlash控制器,所以本系统的硬件部分只要简单地外接NAND F1ash等外围电路即可,附带上串口可以用于NANDFlash设备驱动程序的调试与加载,从而实现嵌入式Linux系统的NANDFlash存储模块加载与卸载。为嵌入式Linux终端上实现yaffs文件系统提供了基础。     

基于软件无线电的近距离扩频测距算法

对基于软件无线电的近距离扩频测距算法进行了研究.论述了直接序列扩频测距的原理,研究了近距离测距的回波模型.从理论上分析了由于体目标引起的引信回波信号的多普勒展宽和距离展宽问题,以及它们对近距离扩频测距的影响.提出采用正交接收机结构来消除载波随机相位对测距的影响.最后对算法进行了软件仿真,对文章的研究工作进行了总结.     

铝包钢丝拉拔工艺设计与试验

选用连续挤压包覆法生产的铝包钢丝毛坯,采用强制润滑拉拔技术进行拉拔试验研究.通过试验、比较筛选了适合铝包铜丝拉拔的耐温耐压润滑剂.在对铝包钢丝拉拔工艺进行合理设计的基础上,拉制出了产品.对产品的机械性能和电性能进行了测试,并对断口进行了扫描电镜的观察.结果表明,双金属的结合性能良好,各项性能指标均达到相关标准.这一试验研究对铝包钢丝的生产有指导意义.     

不同工艺制备的ta-C和ta-C:N薄膜表面粗糙度研究

采用FCVA工艺成功制备了ta-C薄膜,采用ECR-CVD工艺对部分ta-C薄膜试样进行氮等离子体处理,制备了ta-C:N薄膜.对两种薄膜的表面粗糙度与元素含量、沉积工艺参数之间的关系进行了研究.通过AFM对薄膜表面粗糙度进行了分析,通过XPS对薄膜的元素含量进行了分析.试验结果显示,沉积条件对薄膜厚度和元素含量具有明显的影响.对ta-C薄膜进行氮等离子体处理后,其表面粗糙度有一个明显的起伏变化.研究结果表明,氮能改变DLC薄膜表面的粗糙度.元素含量也随着薄膜的厚度变化而变化.     

网络蠕虫的演化

针对复杂生态环境中网络蠕虫对传播率的演化选择问题,给出了一个蠕虫传播模型.运用动力学分析方法得到了模型的平衡态及其稳定性条件,并进行了仿真验证.在理论分析的基础上,利用随机算法仿真了不同传播率对蠕虫传播的影响.仿真结果表明,复杂生态环境更有利于具有小传播率的蠕虫.对该类蠕虫,进一步仿真了防病毒技术对其影响.结果表明,加...     

烧结NdFeB永磁材料力学性能及超声波加工的研究

对烧结NdFeB永磁材料力学性能进行了试验研究,并对其进行了超声波加工试验,试验结果表明了超声波加工的可行性.找寻了加工参数对加工效果的影响规律,建立起两者之间的关系.实验结果对实际生产具有一定的指导意义.     

网络蠕虫的演化

针对复杂生态环境中网络蠕虫对传播率的演化选择问题,给出了一个蠕虫传播模型.运用动力学分析方法得到了模型的平衡态及其稳定性条件,并进行了仿真验证.在理论分析的基础上,利用随机算法仿真了不同传播率对蠕虫传播的影响.仿真结果表明,复杂生态环境更有利于具有小传播率的蠕虫.对该类蠕虫,进一步仿真了防病毒技术对其影响.结果表明,加强杀毒系统对小传播率蠕虫的查杀能力和引入竞争性蠕虫能有效遏制该类蠕虫的传播     

高温闪速炉炉结爆破拆除

叙述对吹炼炉炉结高温凝结物的爆破拆除.施工与安全防护.重点分析了在保证不停产情况下对炉结进行爆破,如何对炸药雷管有效实施隔热,以保证爆破能顺利进行.从实践中找到了解决的方法,确保了爆破安全,圆满完成了爆破任务.     

线性切割器正交优化设计与数值模拟研究

为研究线性切割器结构参数对侵彻深度的影响,利用正交表设计了主要结构参数.利用LSDYNAED模拟了全部情况.利用极差法对数值计算结果进行分析,得到优化结果.最后对优化结果的爆轰过程、射流形成以及侵彻靶板进行了分析.结果表明,交互列对切割器的优化设计有很大影响.并且线性切割器形成的射流头部短小,杵体被拉得很长,并且两翼很长.     

工作研究用于生产线再设计:案例研究

对一条实际的生产线进行了再设计.根据从现场获得的数据,应用MOD法确定了各动作的标准作业时间.在此基础上对各个工作站的工作任务进行了重新设计,使得生产线尽可能平衡.同时对生产线的布局进行了改进.结果系统的产能提高71.9%,工件的传送时间降低26.4%.     

基于 NAND Flash 的嵌入式文件系统设计

主要介绍了针对 NAND Flash 型存储器设计的嵌入式文件系统. 其硬件平台是为了顺应多功能、大容量集成化存储的需求而开发的基于 ADSP-BF532 芯片与 NAND Flash 结合的高性能嵌入式存储系统. 此存储系统采用了多片并行流水的存储模式,开发出独特有效的闪存管理技术与改良的文件系统,通过设置访问权限实现多用户管理,使得处理器、存储器以及文件管理层软件的多方优势得以充分发挥.     

NAND Flash 图像记录系统底层写入控制技术

为提高图像记录系统中 NAND flash 阵列的存储带宽,分别研究和实现了 NAND flash 的片内交叉写入、片内并行写入和片内交叉并行写入控制技术,在此基础上提出了片内交叉写入和片外2级流水线结合的写入方法,该方法利用两组 NAND flash 片内交叉写入的命令地址和数据加载时间来填补烧写时间.最后用硬件方式在 FPGA中分别实现了上述各种写入控制方式的控制器.实验结果表明:本文实现的片内并行写入和片内交叉并行写入是普通写入方式速度的1.48903倍和3.27706倍,而本文提出的写入控制方法的写入速度是普通写入方式的3.96038倍,高于片外4级流水线的性能情况下,将 FPGA 管脚资源占用节省20%,有效降低了成本和记录系统实现难度.     

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.     

基于VPX标准的RapidIO交换和Flash存储模块设计

针对某阵列信号处理系统中的互连总线和数据存储问题,提出了基于VPX标准的RapidIO交换和Flash存储模块的设计方案,并完成了该模块的软硬件设计.介绍了新一代高速串行总线RapidIO和VPX标准,根据VPX标准设计板卡,利用Tsi578交换机设计RapidIO网络实现多DSP系统的并行处理结构.研究了RapidI...     

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon memory device with different tunneling oxide thicknesses

Nanoscale two-bit/cell NAND-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with different tunneling oxide thicknesses were designed to reduce the short channel effect and the coupling interference. The process step and the electrical characteristics of the proposed SONOS memory devices were simulated by using SUPREM-4 and MEDICI, respectively. The short channel effect in the nanoscale two-bit/cell SONOS devices was decreased than that of the conventional devices due to a larger effective channel length. The drain current at the on-state of the proposed NAND SONOS memory devices decreased than that of the conventional NAND SONOS devices due to the high channel resistivity. The I on/I off ratio of the proposed NAND SONOS memory devices was larger than that of the conventional memory devices due to the dramatic decrease in the subthreshold current of the proposed devices. The electrical characteristics of the NAND SONOS memory devices with different tunneling oxide thicknesses were better than those of the conventional NAND SONOS devices.     

Janus Graphene Liquid Crystalline Fiber with Tunable Properties Enabled by Ultrafast Flash Reduction

Flash photothermal treatment via Xenon lamp with a broad wavelength spectrum can effectively remove oxygen functionalities and restore sp² domains at graphitic carbon materials. The chemical composition and relevant structure formation of flash reduced graphene oxide liquid crystal (GOLC) fibers are investigated in accordance with flash irradiation conditions. Owing to the spatial controllability of reduction level via anisotropic flash irradiation, the mechanical properties and electrical conductivity of graphene fibers can be delicately counterbalanced to attain desired properties. High sensitivity humidity sensors can be fabricated from the flash reduced fibers demonstrating notably higher sensitivity over the thermally reduced counterparts. This ultrafast flash reduction holds great promise for multidimensional macroscopic GO based structures, enabling a wide range of potential applications, including textile electronics and wearable sensors.     

闪烧合成高熵氧化物陶瓷(MgCoNiCuZn)O的性能

闪烧技术是一种温度场与电场耦合的烧结技术,具有低温快速传质的特性,在高熵陶瓷的合成上具有显著的优势。本研究通过闪烧法合成了相对致密的高熵氧化物陶瓷(MgCoNiCuZn)O,并与传统烧结试样的性能进行了对比。在室温,电场强度为50 V/cm,电流密度为300 mA/mm²条件下闪烧,物相转变的时间仅为10 s。闪烧试样最高相对密度为94%,比传统烧结试样最高密度提高了22.8%。闪烧试样的最高硬度5.05GPa,比传统烧结试样高3.95 GPa。当频率<2Hz时,闪烧试样的介电常数比传统烧结试样高一个数量级。闪烧试样性能的提高,一方面与临界电场加速传质,提高材料致密度有关;另一方面与临界电场引入额外的缺陷有关。     

Nanocrystalline Nd–Fe–B Anisotropic Magnets by Flash Spark Plasma Sintering

Flash spark plasma sintering (flash SPS) is an attractive method to obtain Nd–Fe–B magnets with anisotropic magnetic properties when starting from melt-spun powders. Compared to the benchmark processing route via hot pressing with subsequent die upsetting, flash SPS promises electroplasticity as an additional deformation mechanism and reduced tool wear, while maximizing magnetic properties by tailoring the microstructure—fully dense and high texture. A detailed parameter study is conducted to understand the influence of Flash SPS parameters on the densification and magnetic properties of commercial MQU-F powder. It is revealed that the presintering conditions and preheating temperature before applying the power pulse play a major role for tailoring grain size and texture in the case of hot deformation via Flash SPS. Detailed microstructure and magnetic domain evaluation disclose the texture enhancement with increasing flash SPS temperature at the expense of coercivity. The best compromise between remanence and coercivity (1.37 T and 1195 kA m⁻¹, respectively) is achieved through a combination of presintering at 500 °C for 120 s and preheating temperature of 600 °C, resulting in a magnet with energy product (BH)_max of 350 kJm⁻³. These findings show the potential of flash SPS to obtain fully dense anisotropic nanocrystalline magnets with high magnetic performance.     

Electrical characteristics of nanoscale NAND silicon-oxide-nitride-oxide-silicon flash memory devices fabricated on SOI substrates

NAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with double gates fabricated on silicon-on-insulator (SOI) substrates were proposed. The current-voltage characteristics related to the programming operation of the designed nanoscale NAND SONOS flash memory devices on a SOI substrate and on the conventional bulk-Si substrate were simulated and compared in order to investigate device characteristics of the scaled-down memory devices. The simulation results showed that the short channel effect and the subthreshod leakage current for the memory device with a large spacer length were lower than that of the memory device with a small spacer length due to increase of the effective channel length. The device performance of the memory device utilizing the SOI substrate exhibited a smaller subthreshold swing and a larger drain current level in comparison with those on the bulk-Si substrate. These improved electrical characteristices for the SOI devices could be explained by comparing the electric field distribution in a channel region for both devices.     

Four‐Bits‐Per‐Cell Operation in an HfO2‐Based Resistive Switching Device

The quadruple‐level cell technology is demonstrated in an Au/Al₂O₃/HfO₂/TiN resistance switching memory device using the industry‐standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self‐compliance and gradual set‐switching behaviors, the device shows 6σ reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 µA. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash. A relatively minor improvement in the material and circuitry may enable even a five‐bits‐per‐cell technology, which can hardly be imagined in NAND flash, whose state‐of‐the‐art multiple‐cell technology is only at three‐level (eight states) to this day.